Tilted ion implantation as a cost-efficient sublithographic

Size: px

Start display at page:

Download "Tilted ion implantation as a cost-efficient sublithographic"

Alicia Collins
6 years ago
Views:

1 Tilted ion implantation as a cost-efficient sublithographic patterning technique Sang Wan Kim 1,a), Peng Zheng 1, Kimihiko Kato 1, Leonard Rubin 2, Tsu-Jae King Liu 1 1 Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, California Axcelis Technologies, 108 Cherry Hill Drive, Beverly, Massachusetts a) Electronic mail: swkim83@berkeley.edu Abstract Tilted ion implantation (TII) is experimentally demonstrated to be a promising approach to pattern features smaller than pre-existing mask features on the surface of a wafer substrate. Key to this approach is a substantial change in the etch rate of a thin masking layer by TII. 15 -tilted Ar + implantation into a 10 nm-thick thermally grown silicon dioxide (SiO 2 ) masking layer at a dose of cm -2 enhances its etch rate in dilute hydrofluoric acid (DHF) solution by a factor of approximately 9. Features defined by TII are shown to be self-aligned to the pre-existing mask features and to have critical dimensions that can be adjusted by changing the implant tilt angle (θ) and/or geometrical dimensions of the pre-existing mask features. In this work, trenches of width as small as ~9 nm and sub-20 nm holes are achieved by TII-enhanced patterning. 1

2 I. INTRODUCTION Scaling of integrated circuit (IC) feature sizes beyond the resolution limit of immersion lithography has been enabled by multiple-patterning techniques 1-3. However, their significant incremental cost is of concern for further increasing the density of transistors on an IC chip 2-4. Although so-called next-generation lithography techniques such as extreme ultraviolet lithography (EUVL), directed self-assembly (DSA) and nanoimprint lithography (NIL) have been extensively investigated, technical challenges hinder their practical application in high-volume manufacturing (HVM) 5-9. Therefore, a more cost-efficient approach is needed to sustain Moore s Law. Tilted ion implantation (TII) recently has been proposed as a cost-efficient technique for defining sub-lithographic features, as illustrated in Figure By using TII in conjunction with patterned photoresist (PR) and/or hard-mask features formed on the surface of a wafer substrate, sub-lithographic implanted regions aligned to the PR/hard-mask features can be formed. A substantial difference in etch rates of implanted vs. unimplanted regions allows for the implanted regions to be distinguished during a subsequent etch process step, so that the thin masking layer is patterned with sublithographic features. In this paper, the versatility of this technique for forming sublithographic features and pitch-halving is discussed. 2

3 l h (a) FIG. 1. (Color online) Schematic cross-sections illustrating the concept of TII-enhanced patterning. (a) Mask features serve to block incoming ions (whose trajectories are indicated by the arrows) from reaching a thin masking layer coating the surface of the wafer substrate. (b) The implanted region of the thin masking layer has a dimension x that is smaller than the mask-defined feature of size l. II. EXPERIMENTAL A. SiO 2 etch rate enhancement by Ar + implantation Previous work has shown that the etch rate of silicon dioxide (SiO 2 ) in hydrofluoric acid (HF) solution can be significantly enhanced by ion implantation, if the damage induced is greater than a certain threshold level (e.g., cm -3 for SiO 2 ) 13. For the purpose of patterning fine features in a SiO 2 masking layer, the layer thickness should be very thin to avoid significant lateral etching during the post-implantation wet etch process. Thus, the effect of TII on the etch rate of ultra-thin SiO 2 layers is investigated in this work. Figure 2 plots the measured etch rate in dilute hydrofluoric (DHF) acid solution (200:1 H 2 O:HF) for 10 nm-thick thermally grown SiO 2 layers. Ar + implantation was performed at 15 tilt angle, 3.0 kev acceleration energy, and cm -2 dose. 3

4 Damage [x10 22 /cm 3 ] Clearly the etch rate is significantly enhanced, by a factor of ~9, for the implanted SiO 2 layer vs. the unimplanted SiO 2 layer. By comparing the etch rate of the implanted SiO 2 layer against the simulated damage concentration profile obtained using SRIM 14, it can be seen that the etch rate correlates well with structural damage induced by TII. Etch rate [Å/sec] implant condition 3.0 kev, 15º, 3X10 14 cm -2 ~9X no implant SiO 2 Depth [Å] FIG. 2. (Color online) Measured etch rate (left y-axis) of 10 nm-thick thermal SiO 2 layers in DHF solution, as a function of depth. Simulated damage (right y-axis) in a 10 nm-thick SiO 2 layer induced by tilted ion implantation. (The experimental and simulated Ar + implant conditions are the same: 15 tilt angle, 3.0 kev acceleration energy, and cm -2 dose. SRIM simulation was performed with full damage cascades 13, 14. B. Hard-mask formation To demonstrate the applicability of TII for defining nanometer-scale features, spacer lithography 3 was used in conjunction with conventional 248 nm deep-ultraviolet (DUV) lithography to form amorphous silicon () hard-mask features with sub-100 nm dimensions over a thermally oxidized silicon wafer substrate, as shown in Figure 3. After the hard-mask layer was deposited onto the thin thermal SiO 2 layer by low-pressure chemical vapor deposition (LPCVD), a layer of low-temperature-deposited oxide (LTO) was deposited to serve as a hard-mask layer for patterning the hard-mask layer. Then 4

a sacrificial layer of was deposited and patterned by DUV lithography, after which sub-100 nm-wide LTO spacers were formed along the sidewalls of the patterned sacrificial by conformal deposition

3(b) and (e)] and then the spacers served as a mask for RIE of the LTO hard-mask layer.

5 a sacrificial layer of was deposited and patterned by DUV lithography, after which sub-100 nm-wide LTO spacers were formed along the sidewalls of the patterned sacrificial by conformal deposition (LPCVD) and reactive ion etching (RIE) [Figs. 3(a) and (d)]. Next the sacrificial features were removed by a selective RIE process [Figs. 3(b) and (e)] and then the spacers served as a mask for RIE of the LTO hard-mask layer. Finally, the pattern of the spacers was transferred to the hard-mask layer with the aid of the LTO hard-mask [Figs. 3(c) and (f)]. LTO LTO LTO LTO Thermal SiO 2 Thermal SiO 2 Thermal SiO 2 Si (a) Si (b) Si (c) LTO LTO LTO LTO LTO (d) (e) (f) FIG. 3. (Color online) Cross-sectional schematics (a-c) and scanning electron microscope images (d-f) illustrating the spacer lithography process used to form sub-lithographic hard-mask features. 5

6 III. RESULTS AND DISCUSSION A. Sub-lithographic patterning From Figure 1 it can be seen that the TII-defined feature size (x) is determined by the implant tilt angle (θ) as well as the mask feature spacing (l), effective height (h) and sidewall angle ( ): x l h(tanθ cot ) (1) Figure 4 shows technology computer-aided design (TCAD) simulations of the implanted Ar profile within the thin SiO 2 masking layer, for different tilt angles. As θ increases from 5 to 25, x decreases from ~200 nm to 100 nm. 260 nm Argon (cm -3 ) 2.0X X X X X X nm = nm (a) 70 nm (b) Doping Conc. [cm -3 ] (c) different implant angles Location [nm] FIG. 4. (Color online) Effect of implant tilt angle θ on TII-defined feature size x, for fixed hard-mask geometry (l = 220 nm, h = 260 nm, = 90 ). (a, b) Contour plots of Ar + 6

7 concentration (cm -3 ) and (c) extracted Ar concentration as a function of location between the hard-mask features. (The origin corresponds to the right edge of the left hard mask feature.) Figures 5 (a) and (b) show experimental results obtained with Ar + implant tilt angles of 15 and 20, respectively. These samples were subjected to DHF etch followed by RIE of the crystalline silicon (c-si) substrate, which allows the implanted regions to be easily distinguished. The hard mask for the sample shown in Figure 5(a) was not patterned with the aid of a LTO hard-mask layer; therefore it was etched during the Si RIE process. Taking this into consideration, the angle measured from the edge of the remaining hard-mask feature to the edge of the etched c-si region matches the expected value of 15. In addition, the length of the sub-lithographic feature defined by TII (i.e., x = ~156.3 nm) corresponds well with the simulation result shown in Figure 4(a). The sample shown in Figure 5(b) had a thinner hard-mask layer which was patterned using a LTO hard-mask. After all of the process steps, ~24.2 nm-thick LTO remained on top of the hard-mask features. The angle measured from the edge of the remaining LTO hard-mask feature to the edge of the unetched c-si region matches the expected value of 20. 7

15 49.7 100 nm 73.8 (i) (iii) (ii) 257.3 156.3 Si substrate 66.5 73.0 (a) 20 (iii) (i) (ii) 100 nm SiO 2 20 83.7 223.3 Si substrate 24.2 234.5 65.1 (b) FIG. 5.

The Ar + implant conditions were: 3.0 kev acceleration energy, 3 10 14 cm -2 dose, (a) 15 and (b) 20 tilt angle.

8 nm 73.8 (i) (iii) (ii) Si substrate (a) 20 (iii) (i) (ii) 100 nm SiO Si substrate (b) FIG. 5. (Color online) Cross-sectional SEM images of samples comprising a 10 nm-thick SiO 2 masking layer and hard-mask features, after tilted Ar + implantation, DHF etch and Si RIE process steps. The Ar + implant conditions were: 3.0 kev acceleration energy, cm -2 dose, (a) 15 and (b) 20 tilt angle. (i) corresponds to etched c-si regions, (ii) corresponds to unetched c-si regions protected during the Si RIE process by the (unimplanted portion of the) SiO 2 masking layer, and (iii) corresponds to hard-mask features. B. Self-alignment to pre-existing mask features Figure 6 shows a plan-view SEM image of a sample with etched c-si features defined by 15 TII. It can be seen that these features are self-aligned to the pre-existing a- Si hard-mask features, i.e. the shape of the hard-mask line edge is reproduced with good fidelity. 8

(i) (ii) (iii) 39.7 71.9 91.8 300 nm Mag = 150 K X FIG. 6. (Color online) Plan-view SEM showing the self-aligned nature of TII-patterned features, especially at the black-circled area.

9 (i) (ii) (iii) nm Mag = 150 K X FIG. 6. (Color online) Plan-view SEM showing the self-aligned nature of TII-patterned features, especially at the black-circled area. (i) corresponds to etched c-si regions, (ii) corresponds to unetched c-si regions, and (iii) corresponds to hard-mask features. C. Pitch-halving Double tilted (positive-angle and negative-angle) Ar + implantation was performed on another sample to demonstrate the feasibility of pitch-halving by TII-enhanced patterning. The implant conditions were the same as for the sample of Figure 5(a) except that two implants were performed, one at θ = 15 and the other at θ = 15. Figure 7(a) shows the results obtained for different values of hard-mask spacing (l). Considering that l is ~61.4 nm for the leftmost set of features, the local half-pitch of the etched c- Si is ~20.5 nm. For the rightmost set of features with smaller l in Figure 7(a) there is no feature defined by the 15 o implant; this is likely due to asymmetry of the hard-mask spacers, i.e. variations in h and (cf. Eq. (1)) between the left spacer and the right spacer. Figure 7(b) shows a set of hard-mask features with much wider spacing so that the implanted regions overlap, i.e. the central region was subjected to double tilted Ar + implantation. The 50 s DHF dip was insufficient to completely remove singly implanted regions of the SiO 2 masking layer (total implanted dose = cm -2 (i)), but sufficient 9

to completely remove the doubly implanted region (total implanted dose = 6 10 14 cm -2 (i)).

These results indicate that the TII technique can be used to define various patterns by adjusting the implant dose and masking-layer etch time. 61.4 64.1 100 nm 200:1 DHF 75 sec (ii) (iii) 92.

10 to completely remove the doubly implanted region (total implanted dose = cm -2 (i)). This is not surprising given that the enhancement in etch rate of SiO 2 is dependent on the amount of structural damage and hence the implant dose 13. These results indicate that the TII technique can be used to define various patterns by adjusting the implant dose and masking-layer etch time nm 200:1 DHF 75 sec (ii) (iii) 92.8 SiO (i) (a) Si substrate 100 nm (ii) 200:1 DHF 50 sec X X10 14 (i) (iii) 48.4 Si substrate (b) FIG. 7. (Color online) Cross-sectional SEM images showing the feasibility of double TII for double-patterning. Ar + implantation was performed at positive and negative tiltangles (±15 with 3.0 kev acceleration energy and cm -2 dose). Afterwards the samples were etched in DHF for (a) 75 sec and (b) 50 sec and subjected to Si RIE. (i) corresponds to etched c-si regions, (ii) corresponds to unetched c-si regions, and (iii) corresponds to hard-mask features. D. Demonstration of sub-10 nm features Figure 8 shows that the local density of etched c-si features is double that of the hard-mask features. In addition, sub-10 nm (local) half-pitch features are achieved, self-aligned to the hard-mask features. In short, the TII-enhanced patterning approach can be used to define sub-10 nm features. 10

(i) 23.8 (ii) 9.5 27.6 (iii) 64.0 53.6 9.0 200 nm FIG. 8.

Double-tilted ion implantation is effective for doubling the density of features. E.

substrate. Figure 9 shows results obtained with round hard-mask features (i.e., holes) and a single Ar + implant at 3.

11 (i) 23.8 (ii) (iii) nm FIG. 8. (Color online) Plan-view SEM image showing that the edges of the etched c-si regions are self-aligned to the edges of the hard-mask features. Double-tilted ion implantation is effective for doubling the density of features. E. Contact hole formation TII-enhanced patterning also can be used in conjunction with non-linear preexisting masking features on the surface of a wafer substrate. Figure 9 shows results obtained with round hard-mask features (i.e., holes) and a single Ar + implant at 3.0 kev acceleration energy, cm -2 dose, and 15 tilt angle. Figure 9(b) shows a ~18.6 nm ellipse-shaped etched hole defined by TII. (It should be noted that the shape of the hard mask can be adjusted to achieve a round TII-defined hole.) (a) (b) θ (c) θ (i) (ii) (iii) (b) 73.8 Silicon Silicon Silicon S 400 nm 100 nm imp r 11

12 FIG. 9. (Color online) (a, b) SEM images showing that TII-enhanced patterning can be used to define sub-lithographic holes. (The residues of SiO 2 masking layer (ii) outside of the hard-mask features (iii) are attributed to incomplete removal of the sacrificial a- Si layer shown in Figure 3(a).) (c) Schematic illustrations showing how TII defines a sub-lithographic ellipse-shaped hole within a lithographically defined round hole. IV. CONCLUSION TII is demonstrated to be an effective approach for defining sub-lithographic features and increasing the density of features self-aligned to pre-existing mask features. TII-defined feature dimensions are controlled by the implant tilt angle, and also depend on the geometrical dimensions of the pre-existing mask features. Using double TII, the density of features can be doubled; local half-pitch as small as ~9.0 nm was experimentally demonstrated. Because ion implantation is a well-established and relatively low cost process, TII-enhanced patterning can be easily adopted in HVM to help extend Moore s Law. ACKNOWLEDGMENTS The authors thank Applied Materials, Inc. and Lam Research Corporation for supporting this work. The tilted ion implantation processes were performed by Axcelis Technologies, Inc. The wafers were processed in the Marvell Nanofabrication Laboratory at the University of California, Berkeley. This work was supported in part by the National Science Foundation within the Directorate for Engineering through the Center for Energy Efficient Electronics Science under Award

13 REFERENCES 1 Y.-K. Choi, T.-J. King, and C. Hu, IEEE T. Electron Dev., 49, 436 (2002). 2 A. Yen, Advanced lithography R&D for 5 nm and beyond, Int. El. Devices Meet., Short Course (2015). 3 International Technology Roadmap for Semiconductors, 4 J. Finder, M. Dusa, B. Vleeming, B. Hepp, M. Maenhoudt, S. Cheng, and T. Vandeweyer, J. Micro-Nanolith. MEM. 8, (2009). 5 N. Mojarad, M. Hojeij, L. Wang, J. Gobrecht, and Y. Ekinci, Nanoscale 7, 4031 (2015). 6 A. Pirati, et al., SPIE Proc. Ser. 9776, 97760A (2016). 7 S.-J. Jeong, J. Y. Kim, B. H. Kim, H.-S. Moon, and S. O. Kim, Mater. Today 16, 468 (2013). 8 M. Muramatsu, et al., SPIE Proc. Ser. 9777, 97770F (2016). 9 X. Guo, et al., J. Vac. Sci. Technol. B 32, 06FG06, (2014). 10 S. W. Kim, P. Zheng, K. Kato, L. Rubin and T.-J. K. Liu, SPIE Proc. Ser. 9777, 97771B (2016). 11 R. Divakaruni, S. Kudelka, H. Tews, I. McStay, K.-H. Lee, and U. Schroeder, U.S. Patent No. 6,498,061 (2000) 12 P.-I. Lee, C.-Y. Lee, and C.-L. Cheng, U.S. Patent No. 7,316,978 (2005) 13 X. Sun, Q. Lu, H. Takeuchi, S. Balasubramanian and T.-J. K. Liu, Electrochem. Solid. St. 10, D89 (2007)

14 FIGURE CAPTIONS FIG. 1. (Color online) Schematic cross-sections illustrating the concept of TII-enhanced patterning. (a) Mask features serve to block incoming ions (whose trajectories are indicated by the arrows) from reaching a thin masking layer coating the surface of the wafer substrate. (b) The implanted region of the thin masking layer has a dimension x that is smaller than the mask-defined feature of size l. FIG. 2. (Color online) Measured etch rate (left y-axis) of 10 nm-thick thermal SiO 2 layers in DHF solution, as a function of depth. Simulated damage (right y-axis) in a 10 nm-thick SiO 2 layer induced by tilted ion implantation. (The experimental and simulated Ar + implant conditions are the same: 15 tilt angle, 3.0 kev acceleration energy, and cm -2 dose. SRIM simulation was performed with full damage cascades 13, 14.) FIG. 3. (Color online) Cross-sectional schematics (a-c) and scanning electron microscope images (d-f) illustrating the spacer lithography process used to form sub-lithographic hard-mask features. FIG. 4. (Color online) Effect of implant tilt angle θ on TII-defined feature size x, for fixed hard-mask geometry (l = 220 nm, h = 260 nm, = 90 ). (a, b) Contour plots of Ar + concentration (cm -3 ) and (c) extracted Ar concentration as a function of location between the hard-mask features. (The origin corresponds to the right edge of the left hard mask feature.) FIG. 5. (Color online) Cross-sectional SEM images of samples comprising a 10 nm-thick SiO 2 masking layer and hard-mask features, after tilted Ar + implantation, DHF etch and Si RIE process steps. The Ar + implant conditions were: 3.0 kev acceleration energy, cm -2 dose, (a) 15 and (b) 20 tilt angle. (i) corresponds to etched c-si regions, (ii) 14

15 corresponds to unetched c-si regions protected during the Si RIE process by the (unimplanted portion of the) SiO 2 masking layer, and (iii) corresponds to hard-mask features. FIG. 6. (Color online) Plan-view SEM showing the self-aligned nature of TII-patterned features, especially at the black-circled area. (i) corresponds to etched c-si regions, (ii) corresponds to unetched c-si regions, and (iii) corresponds to hard-mask features. FIG. 7. (Color online) Cross-sectional SEM images showing the feasibility of double TII for double-patterning. Ar + implantation was performed at positive and negative tilt-angles (±15 with 3.0 kev acceleration energy and cm -2 dose). Afterwards the samples were etched in DHF for (a) 75 sec and (b) 50 sec and subjected to Si RIE. (i) corresponds to etched c-si regions, (ii) corresponds to unetched c-si regions, and (iii) corresponds to hard-mask features. FIG. 8. (Color online) Plan-view SEM image showing that the edges of the etched c-si regions are self-aligned to the edges of the hard-mask features. Double-tilted ion implantation is effective for doubling the density of features. FIG. 9. (Color online) (a, b) SEM images showing that TII-enhanced patterning can be used to define sub-lithographic holes. (The residues of SiO 2 masking layer (ii) outside of the hard-mask features (iii) are attributed to incomplete removal of the sacrificial a- Si layer shown in Figure 3(a).) (c) Schematic illustrations showing how TII defines a sublithographic ellipse-shaped hole within a lithographically defined round hole. 15

There s Plenty of Room at the Bottom and at the Top

14 nm chip X SEM from www.intel.com/content/dam/www/public/us/en/documents/pdf/foundry/mark bohr 2014 idf presentation.pdf There s Plenty of Room at the Bottom and at the Top Tsu Jae King Liu Department