Homework 2 due on Wednesday Quiz #2 on Wednesday Midterm project report due next Week (4 pages)

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1 EE241 - Spring 2013 Advanced Digital Integrated Circuits Lecture 12: SRAM Design ECC Timing Announcements Homework 2 due on Wednesday Quiz #2 on Wednesday Midterm project report due next Week (4 pages) Title Authors Abstract (5 sentences) Introduction Problem statement Solutions to the problem Your proposed solution/comparison/metric How will you prove it? Expected results Conclusion References 2 1

2 Reading H. Partovi, Clocked storage elements, Ch. 11 in Design of High-Performance Microprocessor Circuits, by Chandrakasan, Bowhill, Fox 3 Outline Last lecture SRAM assist techniques This lecture ECC in SRAM Back to timing 4 2

3 SRAM F. Redundancy and ECC Multi-bit Errors Kawahara, ISSCC 07 tutorial 6 3

4 Multi-bit Errors Kawahara, ISSCC 07 tutorial 7 Multi-bit Errors 8 4

5 Multi-bit Errors: Interleaving 9 SRAM G. Options for scaling 5

Vmin Scaling Projections Itoh, ISSCC 09 11 SRAM Scaling Approaching fundamental limits: Don t scale cell size

6 Vmin Scaling Projections Itoh, ISSCC SRAM Scaling Approaching fundamental limits: Don t scale cell size Increase transistor count (from 6) Change technology (e.g. double-gate FETs) edram ReRAM Or something else 12 6

SRAM Alternatives 8-T SRAM Dual-port read/write capability (register file-like cells) N0, N1 separates read and write No Read SNM constraint Half-selected

Chang, VLSI Circuits 2005 13 Alternatives: Thin-Body MOSFETs Thin body suppresses short channel effects Channel lightly doped higher carrier mobility T OX

7 SRAM Alternatives 8-T SRAM Dual-port read/write capability (register file-like cells) N0, N1 separates read and write No Read SNM constraint Half-selected cells still undergo read stress no single cell write capability Stacked transistors reduce leakage L. Chang, VLSI Circuits Alternatives: Thin-Body MOSFETs Thin body suppresses short channel effects Channel lightly doped higher carrier mobility T OX scaling not needed less reliability issues Double-gate structure is scalable to L g <10nm L g Gate Gate Source Drain T Si Source Drain T Si Buried Oxide Substrate Gate Ultra-Thin Body (UTB) Double-Gate (DG) 14 7

8 6-FinFET SRAM Cell FIN = 175mV 2FIN 1FIN = - 240mV 175mV 475nm Vsn2 (V) FIN - 240mV Cell Area = 0.36 m High V T NPD Φ GATE, N/P = 4.75eV Vsn1 (V) 175mV nominal SNM w/ 0.36 m 2 cell area (45nm) 15 6-FinFET SRAM Cell: 2 Fins Access NPD Load FIN = 175mV 2FIN 1FIN = - 175mV 240mV 475nm Vsn2 (V) FIN - 240mV 880nm Cell Area = 0.42 m High V T NPD Φ GATE, N/P = 4.75eV Vsn1 (V) 240mV SNM w/ 0.42 m 2 cell area 36% SNM improvement w/ 17% area penalty 16 8

Bulk-Si FinFETs Lee, VLSI 04, Kavaleros, VLSI 06

be made on bulk-si wafers lower cost improved thermal

with planar bulk-si MOSFETs is possible 17 edram

9 Bulk-Si FinFETs Lee, VLSI 04, Kavaleros, VLSI 06 Process flow illustration from Lee, VLSI 04 FinFETs can be made on bulk-si wafers lower cost improved thermal conduction to mitigate self-heating effects integration with planar bulk-si MOSFETs is possible 17 edram Process cost: Added trench capacitor Barth, ISSCC 07, Wang, IEDM

10 4. Design for performance A. Timing Flip-Flop Parameters D Q D PW m T H T SU Q T CQ Delays can be different for rising and falling data transitions 20 10

11 Latch Parameters D Q Unger and Tan Trans. on Comp. 10/86 D PW m T H T SU Q T CQ T DQ Delays can be different for rising and falling data transitions 21 Example Clock System Courtesy of IEEE Press, New York

12 Clock Nonidealities Clock skew Spatial variation in temporally equivalent clock edges; deterministic + random, t SK Clock jitter Temporal variations in consecutive edges of the clock signal; modulation + random noise Cycle-to-cycle (short-term) - t JS Long-term - t JL Variation of the pulse width for level-sensitive clocking 23 Clock Skew and Jitter 1 t SK 2 t JS Both skew and jitter affect the effective cycle time Only skew affects the race margin, if jitter is from the source Distribution-induced jitter affects both 24 12

13 Clock Uncertainties Devices 2 4 Power Supply 3 Interconnect 6 Capacitive Load 1 Clock Generation 5 Temperature 7 Coupling to Adjacent Lines Sources of clock uncertainty 25 Clock Constraints in Edge-Triggered Systems Courtesy of IEEE Press, New York

14 Latch timing t DQ D Q When data arrives to transparent latch Latch is a soft barrier t CQ When data arrives to closed latch Data has to be re-launched 27 Single-Phase Clock with Latches Latch Unger and Tan Trans. on Comp. 10/86 Logic T skl T skl T skt T skt In Rabaey Chapter 10: T sk T skl T skt PW t CY 28 14

15 Preventing Late Arrivals t CY PW T SU Data must arrive T CQ T LM T SU T SU PW T DQ TLM T SU 29 Preventing Late Arrivals t CY Tskl Tskt TSU TCQM PW, max T TDQM LM Or: tcy TCQM TLM TSU Tskl Tskt PW t T T CY DQM LM 30 15

16 Preventing Premature Arrivals PW T H T CQ T Lm Two cases, reduce to one: TLm Tskl Tskt TH PW TCQm 31 Single-Latch Timing Summary Bounds on logic delay: Latch t CY Tskl Tskt TSU TCQM PW, max T TDQM TLm Tskl Tskt TH PW TCQm LM Logic Solutions: 1) Balance logic delays 2) Locally generated short PW 32 16

17 Next Lecture Back to timing and performance 33 17

EE241 - Spring 2007 Advanced Digital Integrated Circuits. Announcements

EE241 - Spring 2007 Advanced Digital Integrated Circuits Lecture 25: Synchronization Timing Announcements Homework 5 due on 4/26 Final exam on May 8 in class Project presentations on May 3, 1-5pm 2 1 Project