EE241 - Spring 2007 Advanced Digital Integrated Circuits. Announcements

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1 EE241 - Spring 2007 Advanced Digital Integrated Circuits Lecture 25: Synchronization Timing Announcements Homework 5 due on 4/26 Final exam on May 8 in class Project presentations on May 3, 1-5pm 2 1

2 Project Reports and Presentations Should be in paper format max of 6 pages Title of the project/ your names and addresses Abstract (100 words) Motivation Problem statement Possible solutions from literature (from midterm report) Proposed comparison/solution. Discuss why did you select this particular one. Conditions/assumptions of your design Analysis: Does it work? Analytical analysis, simulation results. Conclusion. What is this approach good for? What else could be done? References Due on May 2, at 6pm (on the web), both the report and the slides Time = 2min + 5min/person (two person teams get 12minutes) 3 Class Material Last lecture Flip-flops Today s lecture Synchronization Timing 4 2

3 Timing Overview Synchronization Approaches Synchronous Systems Timing methodologies Latching elements Clock distribution Clock generation Asynchronous Systems 5 References Chapter 10 in Rabaey Chapter 11 in Bowhill Clocked storage elements, by H. Partovi High-speed CMOS design styles, Bernstein, et al, Kluwer Unger/Tan IEEE Trans. Comp. 10/86 Harris/Horowitz JSSC 11/97 Messerschmitt JSAC 10/90 Stojanović/Oklobdžija JSSC 4/99 6 3

4 Issues in Timing D. Messerschmitt, Oct 1990 Boolean signal - stream of 0 s and 1 s, generated by saturating circuits and bistable memory elements but finite rise and fall times inter-symbol interference metastability leads to non-deterministic behavior signal transitions are crucial typically defined with respect to slicer/sampler associated clock with uniformly spaced transitions 7 Issues in Timing Clock signal : f + Δf dφ/dt average frequency instantaneous frequency deviation Single Boolean signal equal Isochronous f + Δf = constant not equal Anisochronous f + Δf constant 8 4

5 Issues in Timing Two Boolean Signals together Synchronous f + Δf identical Δφ(t) = 0 (or known) middle Mesochronous Δφ(t) variable (but bounded) Asynchronous not together different Heterochronous Nominally Different freq near Plesiochronous Average Frequency almost the same 9 Some Definitions Signals that can only transition at predetermined times with respect to a signal clock are called {syn,meso,plesio}chronous An asynchronous signal can transition at any arbitrary time. 10 5

6 Some Definitions (contd) Synchronous Signal: exactly the same frequency as local clock, and fixed phase offset to that clock. Mesochronous Signal: exactly the same frequency as local clock, but unknown phase offset. Plesiochronous Signal: frequency nominally the same as local clock, but slightly different Mesochronous and plesiochronous concepts are very useful for the design of systems with long interconnections, and/or multiple clock domains 11 Mesochronous Interconnect clock synchronous island Data synchronous island Phase Generator Select Clock (local) Phase Detect Data R1 R2 Local Synchronization samples in certainty period of signal 12 6

7 Mesochronous Communication Variable Delay Line Block A R 1 D 1 Interconnect Delay D 2 D3 R 2 D 4 Block B A B Control Timing Recovery 13 Plesiochronous Communication Timing Cloc k C Clock C 2 1 Recovery Originating Module C 3 FIFO Receiving Module Does only marginally deal with fast variations in data delay 14 7

8 Anisochronous Interconnect 15 Synchronous Pipelined Datapath In R1 D Q Logic Block #1 R2 D Q Logic Block #2 R3 D Q Logic Block #3 R4 D Q CLK t pd,reg t pd1 t pd2 t pd3 16 8

9 Latch Parameters D Q Unger and Tan Trans. on Comp. 10/86 D PW m T H T SU Q T -Q T D-Q Delays can be different for rising and falling data transitions 17 Flip-Flop (Register) Parameters D Q D PW m T H T SU Q T -Q Delays can be different for rising and falling data transitions 18 9

10 Example Clock System Courtesy of IEEE Press, New York Clock Nonidealities Clock skew Spatial variation in temporally equivalent clock edges; deterministic + random, t SK Clock jitter Temporal variations in consecutive edges of the clock signal; modulation + random noise Cycle-to-cycle (short-term) t JS Long term t JL Variation of the pulse width for level sensitive clocking 20 10

11 Clock Skew and Jitter 1 t SK 2 t JS Both skew and jitter affect the effective cycle time Only skew affects the race margin 21 Clock Uncertainties 4 Power Supply Devices 2 3 Interconnect 6 Capacitive Load 1 Clock Generation 5 Temperature 7 Coupling to Adjacent Lines Sources of clock uncertainty 22 11

12 Clock Skew # of registers Earliest occurrence of edge Nominal δ/2 Latest occurrence of edge Nominal + δ /2 Insertion delay Max skew delay δ 23 Clock Constraints in Edge-Triggered Systems Courtesy of IEEE Press, New York

13 Flip-Flop Based Timing φ Logic delay Skew Flip-flop delay Flip -flop Logic T SU φ = 0 T -Q φ = 1 Illustration idea from Horowitz, VLSI Latch timing t D-Q D Q When data arrives to transparent latch Latch is a soft barrier t -Q When data arrives to closed latch Data has to be re-launched 26 13

14 Single-Phase Clock with Latches φ Latch Unger and Tan Trans. on Comp. 10/86 Logic T skl T skl T skt T skt In Chapter 10: T = T + T sk skl skt PW P 27 Preventing Late Arrivals P PW T SU Data must arrive T -Q T LM T SU T SU PW T D-Q TLM T SU 28 14

15 Preventing Late Arrivals Tskl + Tskt + TSU + Tclk QM PW, P max + T TD QM LM Or: P T clk QM + T LM + T SU + T skl + T skt PW P T D + T QM LM 29 Preventing Premature Arrivals PW T H T -Q T Lm Two cases, reduce to one: T Lm T skl + T skt + T H + PW T Qm 30 15

16 Single-Latch Timing Bounds on logic delay: φ Tskl + Tskt + TSU + Tclk QM PW, P max + TLM TD QM Latch T Lm T skl + T skt + T H + PW T Qm Logic Either balance logic delays or make PW short 31 Latch-Based Design L1 latch is transparent when f = 0 f L2 latch is transparent when f = 1 L1 Latch Logic L2 Latch Logic 32 16

17 Latch-Based Timing As long as transitions are within the assertion period of the latch, no impact of position of clock edges 33 Latch Design and Hold Times 34 17

18 Latch-Based Timing Longest path P 2T + T + T D QM LHM Independent of skew Short paths LLM T CLLm T SK + T H T Qm T CLHm T SK + T H T Qm Same as register-based design but holds for both clock edges 35 Latch-Based Timing φ Static logic Skew L1 Latch Logic L2 Latch φ = 1 L2 latch L1 latch Logic Long path φ = 0 Can tolerate skew! Short path 36 18

Dynamic Logic with Latches Edges become hard Time available to logic is P 2T D-Q From [Harris] 37 Latches with Dynamic Logic Phase1-domino evaluates Phase2-domino precharges Clock evaluates logic and

19 Dynamic Logic with Latches Edges become hard Time available to logic is P 2T D-Q From [Harris] 37 Latches with Dynamic Logic Phase1-domino evaluates Phase2-domino precharges Clock evaluates logic and opens subsequent latch: L2 latch φ = 0 L1 latch Static signals driving dynamic logic must be either non-inverting or stable before evaluation φ = 1 Phase2-domino evaluates Short path Phase1-domino precharges 38 19

20 Soft-Edge Properties of Latches Slack passing logical partition uses left over time (slack) from the previous partition Time borrowing logical partition utilizes a portion of time allotted to the next partition Makes most impact in unbalanced pipelines Bernstein et al, Chapter 8, Partovi, Chap Slack-Passing and Cycle Borrowing For N stage pipeline, overall logic delay should be < N Tcl 40 20

21 Slack Passing Example Edge Triggered: T = 125 nsec Latch-based: T = 100 nsec 41 21

Lecture 27: Latches. Final presentations May 8, 1-5pm, BWRC Final reports due May 7 Final exam, Monday, May :30pm, 241 Cory

Lecture 27: Latches. Final presentations May 8, 1-5pm, BWRC Final reports due May 7 Final exam, Monday, May :30pm, 241 Cory EE241 - Spring 2008 Advanced Digital Integrated Circuits Lecture 27: Latches Timing Announcements Wrapping-up the class: Final presentations May 8, 1-5pm, BWRC Final reports due May 7 Final exam, Monday,