EECS 427 Lecture 14: Timing Readings: EECS 427 F09 Lecture Reminders

Size: px
Start display at page:

Download "EECS 427 Lecture 14: Timing Readings: EECS 427 F09 Lecture Reminders"

Transcription

1 EECS 427 Lecture 14: Timing Readings: EECS 427 F09 Lecture 14 1 Reminders CA assignments Please submit CA6 by tomorrow noon CA7 is due in a week Seminar by Prof. Bora Nikolic SRAM variability in space and time 11 am, Friday 11/6, 3427 EECS HW4 (detailed proposal) is due 11/ weeks away You should have completed your schematic design and simulation and started block layouts by then uiz 2 on Monday 11/ weeks away Your chance to improve your performance in uiz 1 EECS 427 F09 Lecture

2 Synchronous Timing CLK In R Combinational 1 R 2 Out EECS 427 F09 Lecture 14 3 Latch Parameters t hold T t su t c-q t d-q elays can be different for rising and falling data transitions EECS 427 F09 Lecture

3 Register (FF) Parameters T t hold t su t c-q elays can be different for rising and falling data transitions EECS 427 F09 Lecture 14 5 More Precise Setup efinition t t Setup time is a fairly vague concept The correct data can be captured but the delay can be greatly affected Where is the threshold? Minimum - delay is the fastest possible way to transfer input to output, related to the sum of T setup and T clk- EECS 427 F09 Lecture 14 6 t 3

4 Setup Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 M - elay Inv1 CP T - ata Clock t=0 EECS 427 F09 Lecture 14 7 Setup Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 M - elay Inv1 CP T - ata Clock t=0 EECS 427 F09 Lecture

5 Setup Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 M - elay Inv1 CP T - ata Clock t=0 EECS 427 F09 Lecture 14 9 Setup Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 M - elay Inv1 T - CP ata Clock t=0 EECS 427 F09 Lecture

6 Setup Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 M - elay T - Inv1 CP ata Clock t=0 EECS 427 F09 Lecture and setup time summary efine setup time as the point at which CLK- delay rises 5% beyond nominal Nominal is measured when data arrives much earlier than CLK edge This corresponds roughly to where the total - delay is minimized EECS 427 F09 Lecture

7 Clock Waveform Nonidealities Clock skew Spatial variation in temporally equivalent clock edges, Clock jitter Temporal variations in consecutive edges of the clock signal Cycle-to-cycle (short-term) t JS Long term t JL Variation of the pulse width (duty cycle) Important for level sensitive (latch-based) clocking EECS 427 F09 Lecture Clock Skew and Jitter t JS Both skew and jitter impact the effective cycle time EECS 427 F09 Lecture

8 Clock Uncertainties evices 2 4 Power Supply 3 Interconnect t 6 Capacitive Load 1 Clock Generation 5 Temperature 7 Coupling to Adjacent Lines Sources of clock uncertainty EECS 427 F09 Lecture Jitter Sources Caused by variations in clock period that result from: Phased-lock loop (PLL) oscillation frequency Various noise sources affecting clock generation and distribution Ex. Power supply noise which dynamically alters the drive strength of intermediate buffer stages Cypress Semi EECS 427 F09 Lecture

9 IBM microprocessor clock skew # of paths EECS 427 F09 Lecture Idealized View of Clock Skew # of registers Earliest occurrence of edge Nominal /2 Latest occurrence of edge Nominal + /2 Clock network delay Max skew delay EECS 427 F09 Lecture

10 Positive and Negative Skew In R1 Combinational R2 Combinational R3 CLK t CLK1 t CLK2 t CLK3 delay (a) Positive skew delay In R1 Combinational R2 Combinational R3 t CLK1 t CLK2 t CLK3 delay delay CLK (b) Negative skew EECS 427 F09 Lecture Positive Skew, > 0 T CLK CLK1 1 T CLK 3 CLK2 2 4 t hold Launching edge arrives before the receiving edge Good for performance, bad for hold time Key: Hold time violations cannot be fixed by running the clock slower! EECS 427 F09 Lecture

11 Negative Skew, < 0 T CLK + CLK1 1 T CLK 3 CLK2 2 4 Receiving edge arrives before the launching edge Bad for performance, good for hold time violations EECS 427 F09 Lecture Timing Constraints In R1 Combinational R2 CLK t CLK1 t CLK2 t c q t c q, cd t su, t hold t logic t logic, cd Minimum cycle time: T t c-q + t su + t logic - Worst case is when receiving edge arrives early (negative ) EECS 427 F09 Lecture

12 Timing Constraints In R1 Combinational R2 CLK t CLK1 t CLK2 t c q t c q, cd t su, t hold t logic t logic, cd Hold time constraint: t (c-q, cd) + t (logic, cd) > t hold + Worst case is when receiving edge arrives late (positive skew) Race between data and clock cd: contamination delay (fastest possible delay) EECS 427 F09 Lecture Impact of Jitter T CLK CLK -t ji tte r t jitter In REGS CLK t c-q, t c-q, cd t su, t hold t jitter Combinational t logic t logic, cd 24 EECS 427 F09 Lecture 14 12

13 Longest Path T - T T LM T SU T JI + JI Latest point of launching Earliest arrival of next cycle 25 EECS 427 F09 Lecture 14 Clock Constraints If launching edge is late and receiving edge is early, the data will not be too late if: T c-q + T LM + T SU < T T JI,1 T JI,2 - Minimum cycle time is determined by the maximum delays through the logic T c-q + T LM + T SU T JI < T Skew can be either positive or negative 26 EECS 427 F09 Lecture 14 13

14 Shortest Path Earliest point of launching T - T Lm T H Nominal clock edge ata must not arrive before this time 27 EECS 427 F09 Lecture 14 Clock Constraints If launching edge is early and receiving edge is late: T c-q + T LM T JI,1 < T H + T JI,2 + Minimum logic delay T c-q + T LM < T H + 2T JI + 28 EECS 427 F09 Lecture 14 14

15 How to counter Clock Skew? Negative Skew REG REG. REG log Out In REG Positive Skew Clock istribution ib ti ata and Clock Routing 29 EECS 427 F09 Lecture 14 Latch timing t - When data arrives to transparent latch Latch is a soft barrier t - When data arrives to closed latch ata has to be re-launched 30 EECS 427 F09 Lecture 14 15

16 Single-Phase Clock with Latches Latch T skl T skl T skt T skt PW P 31 EECS 427 F09 Lecture 14 Latch-Based esign L1 latch is transparent when = 0 L2 latch is transparent when = 1 L1 Latch L2 Latch 32 EECS 427 F09 Lecture 14 16

17 Slack-borrowing In L1 CLB_A L2 L1 CLB_B t a pd,a b c t pd,b db d e CLK1 CLK2 CLK1 T CLK CLK1 CLK2 slack passed to next stage t pd,a t t pd,b t a valid b valid c valid e valid d valid 33 EECS 427 F09 Lecture 14 Conclusions Clocks strongly impact IC performance (timing) and are not ideal Skew and jitter are commonly discussed non-idealities Skew is typically larger and more heavily focused on More on skew later in class when we discuss clock distribution techniques Rough rule of thumb: skew should be kept < 10% of clock period Sequential elements eat up a significant amount of total timing budget + power resources They are therefore extremely important to design carefully Robustness is critical as well EECS 427 F09 Lecture

The Linear-Feedback Shift Register

The Linear-Feedback Shift Register EECS 141 S02 Timing Project 2: A Random Number Generator R R R S 0 S 1 S 2 1 0 0 0 1 0 1 0 1 1 1 0 1 1 1 0 1 1 0 0 1 1 0 0 The Linear-Feedback Shift Register 1 Project Goal Design a 4-bit LFSR SPEED, SPEED,

More information

GMU, ECE 680 Physical VLSI Design 1

GMU, ECE 680 Physical VLSI Design 1 ECE680: Physical VLSI Design Chapter VII Timing Issues in Digital Circuits (chapter 10 in textbook) GMU, ECE 680 Physical VLSI Design 1 Synchronous Timing (Fig. 10 1) CLK In R Combinational 1 R Logic 2

More information

Timing Issues. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolić. January 2003

Timing Issues. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolić. January 2003 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolić Timing Issues January 2003 1 Synchronous Timing CLK In R Combinational 1 R Logic 2 C in C out Out 2

More information

EE115C Winter 2017 Digital Electronic Circuits. Lecture 19: Timing Analysis

EE115C Winter 2017 Digital Electronic Circuits. Lecture 19: Timing Analysis EE115C Winter 2017 Digital Electronic Circuits Lecture 19: Timing Analysis Outline Timing parameters Clock nonidealities (skew and jitter) Impact of Clk skew on timing Impact of Clk jitter on timing Flip-flop-

More information

Xarxes de distribució del senyal de. interferència electromagnètica, consum, soroll de conmutació.

Xarxes de distribució del senyal de. interferència electromagnètica, consum, soroll de conmutació. Xarxes de distribució del senyal de rellotge. Clock skew, jitter, interferència electromagnètica, consum, soroll de conmutació. (transparències generades a partir de la presentació de Jan M. Rabaey, Anantha

More information

Lecture 9: Sequential Logic Circuits. Reading: CH 7

Lecture 9: Sequential Logic Circuits. Reading: CH 7 Lecture 9: Sequential Logic Circuits Reading: CH 7 Sequential Logic FSM (Finite-state machine) Inputs Current State COMBINATIONAL LOGIC Registers Outputs = f(current, inputs) Next state 2 storage mechanisms

More information

Issues on Timing and Clocking

Issues on Timing and Clocking ECE152B TC 1 Issues on Timing and Clocking X Combinational Logic Z... clock clock clock period ECE152B TC 2 Latch and Flip-Flop L CK CK 1 L1 1 L2 2 CK CK CK ECE152B TC 3 Clocking X Combinational Logic...

More information

EE241 - Spring 2007 Advanced Digital Integrated Circuits. Announcements

EE241 - Spring 2007 Advanced Digital Integrated Circuits. Announcements EE241 - Spring 2007 Advanced Digital Integrated Circuits Lecture 25: Synchronization Timing Announcements Homework 5 due on 4/26 Final exam on May 8 in class Project presentations on May 3, 1-5pm 2 1 Project

More information

EECS 427 Lecture 15: Timing, Latches, and Registers Reading: Chapter 7. EECS 427 F09 Lecture Reminders

EECS 427 Lecture 15: Timing, Latches, and Registers Reading: Chapter 7. EECS 427 F09 Lecture Reminders EECS 427 Lecture 15: Timing, Latches, and Registers Reading: Chapter 7 1 Reminders CA assignments CA7 is due Thursday at noon ECE Graduate Symposium Poster session in ECE Atrium on Friday HW4 (detailed

More information

EE141- Spring 2007 Digital Integrated Circuits

EE141- Spring 2007 Digital Integrated Circuits EE141- Spring 27 igital Integrated Circuits Lecture 19 Sequential Circuits 1 Administrative Stuff Project Ph. 2 due Tu. 5pm 24 Cory box + email ee141- project@bwrc.eecs.berkeley.edu Hw 8 Posts this Fr.,

More information

Lecture 27: Latches. Final presentations May 8, 1-5pm, BWRC Final reports due May 7 Final exam, Monday, May :30pm, 241 Cory

Lecture 27: Latches. Final presentations May 8, 1-5pm, BWRC Final reports due May 7 Final exam, Monday, May :30pm, 241 Cory EE241 - Spring 2008 Advanced Digital Integrated Circuits Lecture 27: Latches Timing Announcements Wrapping-up the class: Final presentations May 8, 1-5pm, BWRC Final reports due May 7 Final exam, Monday,

More information

Homework 2 due on Wednesday Quiz #2 on Wednesday Midterm project report due next Week (4 pages)

Homework 2 due on Wednesday Quiz #2 on Wednesday Midterm project report due next Week (4 pages) EE241 - Spring 2013 Advanced Digital Integrated Circuits Lecture 12: SRAM Design ECC Timing Announcements Homework 2 due on Wednesday Quiz #2 on Wednesday Midterm project report due next Week (4 pages)

More information

Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. November Digital Integrated Circuits 2nd Sequential Circuits

Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. November Digital Integrated Circuits 2nd Sequential Circuits igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic esigning i Sequential Logic Circuits November 2002 Sequential Logic Inputs Current State COMBINATIONAL

More information

Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits A Design Perspective igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic esigning Sequential Logic Circuits November 2002 Naming Conventions In our text: a latch is level sensitive

More information

Designing Sequential Logic Circuits

Designing Sequential Logic Circuits igital Integrated Circuits (83-313) Lecture 5: esigning Sequential Logic Circuits Semester B, 2016-17 Lecturer: r. Adam Teman TAs: Itamar Levi, Robert Giterman 26 April 2017 isclaimer: This course was

More information

Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits A Design Perspective igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic esigning Sequential Logic Circuits November 2002 Sequential Logic Inputs Current State COMBINATIONAL LOGIC

More information

9/18/2008 GMU, ECE 680 Physical VLSI Design

9/18/2008 GMU, ECE 680 Physical VLSI Design ECE680: Physical VLSI esign Chapter IV esigning Sequential Logic Circuits (Chapter 7) 1 Sequential Logic Inputs Current State COMBINATIONAL LOGIC Registers Outputs Next state 2 storage mechanisms positive

More information

GMU, ECE 680 Physical VLSI Design

GMU, ECE 680 Physical VLSI Design ECE680: Physical VLSI esign Chapter IV esigning Sequential Logic Circuits (Chapter 7) 1 Sequential Logic Inputs Current State COMBINATIONAL LOGIC Registers Outputs Next state 2 storage mechanisms positive

More information

Jin-Fu Li Advanced Reliable Systems (ARES) Lab. Department of Electrical Engineering. Jungli, Taiwan

Jin-Fu Li Advanced Reliable Systems (ARES) Lab. Department of Electrical Engineering. Jungli, Taiwan Chapter 7 Sequential Circuits Jin-Fu Li Advanced Reliable Systems (ARES) Lab. epartment of Electrical Engineering National Central University it Jungli, Taiwan Outline Latches & Registers Sequencing Timing

More information

Final presentations May 8, 1-5pm, BWRC Final reports due May 7, 8pm Final exam, Monday, May :30pm, 241 Cory

Final presentations May 8, 1-5pm, BWRC Final reports due May 7, 8pm Final exam, Monday, May :30pm, 241 Cory EE241 - Spring 2008 Advanced Digital Integrated Circuits Lecture 28: Latch-Based iming Conclusion Announcements Wrapping-up the class: Final presentations May 8, 1-5pm, BWRC Final reports due May 7, 8pm

More information

Lecture 9: Clocking, Clock Skew, Clock Jitter, Clock Distribution and some FM

Lecture 9: Clocking, Clock Skew, Clock Jitter, Clock Distribution and some FM Lecture 9: Clocking, Clock Skew, Clock Jitter, Clock Distribution and some FM Mark McDermott Electrical and Computer Engineering The University of Texas at Austin 9/27/18 VLSI-1 Class Notes Why Clocking?

More information

Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits A Design Perspective Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Designing Sequential Logic Circuits November 2002 Sequential Logic Inputs Current State COMBINATIONAL

More information

CMPEN 411. Spring Lecture 18: Static Sequential Circuits

CMPEN 411. Spring Lecture 18: Static Sequential Circuits CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 18: Static Sequential Circuits [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp11

More information

L4: Sequential Building Blocks (Flip-flops, Latches and Registers)

L4: Sequential Building Blocks (Flip-flops, Latches and Registers) L4: Sequential Building Blocks (Flip-flops, Latches and Registers) Acknowledgements: Lecture material adapted from R. Katz, G. Borriello, Contemporary Logic esign (second edition), Prentice-Hall/Pearson

More information

CSE241 VLSI Digital Circuits Winter Lecture 07: Timing II

CSE241 VLSI Digital Circuits Winter Lecture 07: Timing II CSE241 VLSI Digital Circuits Winter 2003 Lecture 07: Timing II CSE241 L3 ASICs.1 Delay Calculation Cell Fall Cap\Tr 0.05 0.2 0.5 0.01 0.02 0.16 0.30 0.5 2.0 0.04 0.32 0.178 0.08 0.64 0.60 1.20 0.1ns 0.147ns

More information

Problem Set 9 Solutions

Problem Set 9 Solutions CSE 26 Digital Computers: Organization and Logical Design - 27 Jon Turner Problem Set 9 Solutions. For each of the sequential circuits shown below, draw in the missing parts of the timing diagrams. You

More information

Y. Tsiatouhas. VLSI Systems and Computer Architecture Lab

Y. Tsiatouhas. VLSI Systems and Computer Architecture Lab CMOS INTEGRATE CIRCUIT ESIGN TECHNIUES University of Ioannina Memory Elements and other Circuits ept. of Computer Science and Engineering Y. Tsiatouhas CMOS Integrated Circuit esign Techniques Overview.

More information

ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2018

ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2018 ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2018 ΔΙΑΛΕΞΕΙΣ 12-13: esigning ynamic and Static CMOS Sequential Circuits ΧΑΡΗΣ ΘΕΟΧΑΡΙΔΗΣ (ttheocharides@ucy.ac.cy) (ack: Prof. Mary Jane Irwin and

More information

Clock Strategy. VLSI System Design NCKUEE-KJLEE

Clock Strategy. VLSI System Design NCKUEE-KJLEE Clock Strategy Clocked Systems Latch and Flip-flops System timing Clock skew High speed latch design Phase locked loop ynamic logic Multiple phase Clock distribution Clocked Systems Most VLSI systems are

More information

Timing Constraints in Sequential Designs. 63 Sources: TSR, Katz, Boriello & Vahid

Timing Constraints in Sequential Designs. 63 Sources: TSR, Katz, Boriello & Vahid Timing Constraints in Sequential esigns 63 Sources: TSR, Katz, Boriello & Vahid Where we are now. What we covered last time: FSMs What we ll do next: Timing constraints Upcoming deadlines: ZyBook today:

More information

UNIVERSITY OF CALIFORNIA

UNIVERSITY OF CALIFORNIA UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on April 14, 2004 by Brian Leibowitz (bsl@eecs.berkeley.edu) Jan Rabaey Homework

More information

CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues

CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan,

More information

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #9 EECS141 PROBLEM 1: TIMING Consider the simple state machine shown

More information

L4: Sequential Building Blocks (Flip-flops, Latches and Registers)

L4: Sequential Building Blocks (Flip-flops, Latches and Registers) L4: Sequential Building Blocks (Flip-flops, Latches and Registers) Acknowledgements:., Materials in this lecture are courtesy of the following people and used with permission. - Randy H. Katz (University

More information

Sequential Logic Worksheet

Sequential Logic Worksheet Sequential Logic Worksheet Concept Inventory: Notes: D-latch & the Dynamic Discipline D-register Timing constraints for sequential circuits Set-up and hold times for sequential circuits 6.004 Worksheet

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 18: March 27, 2018 Dynamic Logic, Charge Injection Lecture Outline! Sequential MOS Logic " D-Latch " Timing Constraints! Dynamic Logic " Domino

More information

Integrated Circuits & Systems

Integrated Circuits & Systems Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 18 CMOS Sequential Circuits - 1 guntzel@inf.ufsc.br

More information

Clock signal in digital circuit is responsible for synchronizing the transfer to the data between processing elements.

Clock signal in digital circuit is responsible for synchronizing the transfer to the data between processing elements. 1 2 Introduction Clock signal in digital circuit is responsible for synchronizing the transfer to the data between processing elements. Defines the precise instants when the circuit is allowed to change

More information

TAU 2014 Contest Pessimism Removal of Timing Analysis v1.6 December 11 th,

TAU 2014 Contest Pessimism Removal of Timing Analysis v1.6 December 11 th, TU 2014 Contest Pessimism Removal of Timing nalysis v1.6 ecember 11 th, 2013 https://sites.google.com/site/taucontest2014 1 Introduction This document outlines the concepts and implementation details necessary

More information

ALU, Latches and Flip-Flops

ALU, Latches and Flip-Flops CSE14: Components and Design Techniques for Digital Systems ALU, Latches and Flip-Flops Tajana Simunic Rosing Where we are. Last time: ALUs Plan for today: ALU example, latches and flip flops Exam #1 grades

More information

Timing Analysis with Clock Skew

Timing Analysis with Clock Skew , Mark Horowitz 1, & Dean Liu 1 David_Harris@hmc.edu, {horowitz, dliu}@vlsi.stanford.edu March, 1999 Harvey Mudd College Claremont, CA 1 (with Stanford University, Stanford, CA) Outline Introduction Timing

More information

MODULE 5 Chapter 7. Clocked Storage Elements

MODULE 5 Chapter 7. Clocked Storage Elements MODULE 5 Chapter 7 Clocked Storage Elements 3/9/2015 1 Outline Background Clocked Storage Elements Timing, terminology, classification Static CSEs Latches Registers Dynamic CSEs Latches Registers 3/9/2015

More information

Fundamentals of Computer Systems

Fundamentals of Computer Systems Fundamentals of Computer Systems Sequential Logic Stephen A. Edwards Columbia University Summer 2017 State-Holding Elements Bistable Elements S Latch Latch Positive-Edge-Triggered Flip-Flop Flip-Flop with

More information

Hold Time Illustrations

Hold Time Illustrations Hold Time Illustrations EE213-L09-Sequential Logic.1 Pingqiang, ShanghaiTech, 2018 Hold Time Illustrations EE213-L09-Sequential Logic.2 Pingqiang, ShanghaiTech, 2018 Hold Time Illustrations EE213-L09-Sequential

More information

Lecture #4: Potpourri

Lecture #4: Potpourri Lecture #4: Potpourri Paul Hartke Phartke@stanford.edu Stanford EE183 April 15, 2002 Tutorial/Verilog Questions? Tutorial is mostly done, right? Due tonight at Midnight (Mon 4/14/02) Turn in copies of

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 23: April 17, 2018 I/O Circuits, Inductive Noise, CLK Generation Lecture Outline! Packaging! Variation and Testing! I/O Circuits! Inductive

More information

L15: Custom and ASIC VLSI Integration

L15: Custom and ASIC VLSI Integration L15: Custom and ASIC VLSI Integration Average Cost of one transistor 10 1 0.1 0.01 0.001 0.0001 0.00001 $ 0.000001 Gordon Moore, Keynote Presentation at ISSCC 2003 0.0000001 '68 '70 '72 '74 '76 '78 '80

More information

5. Sequential Logic x Computation Structures Part 1 Digital Circuits. Copyright 2015 MIT EECS

5. Sequential Logic x Computation Structures Part 1 Digital Circuits. Copyright 2015 MIT EECS 5. Sequential Logic 6.004x Computation Structures Part 1 igital Circuits Copyright 2015 MIT EECS 6.004 Computation Structures L5: Sequential Logic, Slide #1 Something We Can t Build (Yet) What if you were

More information

Sequential vs. Combinational

Sequential vs. Combinational Sequential Circuits Sequential vs. Combinational Combinational Logic: Output depends only on current input TV channel selector (-9) inputs system outputs Sequential Logic: Output depends not only on current

More information

Skew-Tolerant Circuit Design

Skew-Tolerant Circuit Design Skew-Tolerant Circuit Design David Harris David_Harris@hmc.edu December, 2000 Harvey Mudd College Claremont, CA Outline Introduction Skew-Tolerant Circuits Traditional Domino Circuits Skew-Tolerant Domino

More information

ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering

ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering TIMING ANALYSIS Overview Circuits do not respond instantaneously to input changes

More information

Chapter 13. Clocked Circuits SEQUENTIAL VS. COMBINATIONAL CMOS TG LATCHES, FLIP FLOPS. Baker Ch. 13 Clocked Circuits. Introduction to VLSI

Chapter 13. Clocked Circuits SEQUENTIAL VS. COMBINATIONAL CMOS TG LATCHES, FLIP FLOPS. Baker Ch. 13 Clocked Circuits. Introduction to VLSI Chapter 13 Clocked Circuits SEQUENTIAL VS. COMBINATIONAL CMOS TG LATCHES, FLIP FLOPS SET-RESET (SR) ARBITER LATCHES FLIP FLOPS EDGE TRIGGERED DFF FF TIMING Joseph A. Elias, Ph.D. Adjunct Professor, University

More information

Clocking Issues: Distribution, Energy

Clocking Issues: Distribution, Energy EE M216A.:. Fall 2010 Lecture 12 Clocking Issues: istribution, Energy Prof. ejan Marković ee216a@gmail.com Clock istribution Goals: eliver clock to all memory elements with acceptable skew eliver clock

More information

TAU 2015 Contest Incremental Timing Analysis and Incremental Common Path Pessimism Removal (CPPR) Contest Education. v1.9 January 19 th, 2015

TAU 2015 Contest Incremental Timing Analysis and Incremental Common Path Pessimism Removal (CPPR) Contest Education. v1.9 January 19 th, 2015 TU 2015 Contest Incremental Timing nalysis and Incremental Common Path Pessimism Removal CPPR Contest Education v1.9 January 19 th, 2015 https://sites.google.com/site/taucontest2015 Contents 1 Introduction

More information

Efficient Circuit Analysis under Multiple Input Switching (MIS) Anupama R. Subramaniam

Efficient Circuit Analysis under Multiple Input Switching (MIS) Anupama R. Subramaniam Efficient Circuit Analysis under Multiple Input Switching (MIS) by Anupama R. Subramaniam A Dissertation Presented in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy Approved

More information

Digital System Clocking: High-Performance and Low-Power Aspects. Vojin G. Oklobdzija, Vladimir M. Stojanovic, Dejan M. Markovic, Nikola M.

Digital System Clocking: High-Performance and Low-Power Aspects. Vojin G. Oklobdzija, Vladimir M. Stojanovic, Dejan M. Markovic, Nikola M. Digital System Clocking: High-Performance and Low-Power Aspects Vojin G. Oklobdzija, Vladimir M. Stojanovic, Dejan M. Markovic, Nikola M. Nedovic Wiley-Interscience and IEEE Press, January 2003 Nov. 14,

More information

EE241 - Spring 2006 Advanced Digital Integrated Circuits

EE241 - Spring 2006 Advanced Digital Integrated Circuits EE241 - Spring 2006 Advanced Digital Integrated Circuits Lecture 20: Asynchronous & Synchronization Self-timed and Asynchronous Design Functions of clock in synchronous design 1) Acts as completion signal

More information

EECS150 - Digital Design Lecture 17 - Sequential Circuits 3 (Counters)

EECS150 - Digital Design Lecture 17 - Sequential Circuits 3 (Counters) EECS150 - Digital Design Lecture 17 - Sequential Circuits 3 (Counters) March 19&21, 2002 John Wawrzynek Spring 2002 EECS150 - Lec13-seq3 version 2 Page 1 Counters Special sequential circuits (FSMs) that

More information

Time Allowed 3:00 hrs. April, pages

Time Allowed 3:00 hrs. April, pages IGITAL ESIGN COEN 32 Prof. r. A. J. Al-Khalili Time Allowed 3: hrs. April, 998 2 pages Answer All uestions No materials are allowed uestion a) esign a half subtractor b) esign a full subtractor c) Using

More information

Reducing Delay Uncertainty in Deeply Scaled Integrated Circuits Using Interdependent Timing Constraints

Reducing Delay Uncertainty in Deeply Scaled Integrated Circuits Using Interdependent Timing Constraints Reducing Delay Uncertainty in Deeply Scaled Integrated Circuits Using Interdependent Timing Constraints Emre Salman and Eby G. Friedman Department of Electrical and Computer Engineering University of Rochester

More information

Chapter 7 Sequential Logic

Chapter 7 Sequential Logic Chapter 7 Sequential Logic SKEE2263 Digital Systems Mun im/ismahani/izam {munim@utm.my,e-izam@utm.my,ismahani@fke.utm.my} March 28, 2016 Table of Contents 1 Intro 2 Bistable Circuits 3 FF Characteristics

More information

EE382 Processor Design Winter 1999 Chapter 2 Lectures Clocking and Pipelining

EE382 Processor Design Winter 1999 Chapter 2 Lectures Clocking and Pipelining Slide 1 EE382 Processor Design Winter 1999 Chapter 2 Lectures Clocking and Pipelining Slide 2 Topics Clocking Clock Parameters Latch Types Requirements for reliable clocking Pipelining Optimal pipelining

More information

Constraining and Analyzing Source-Synchronous Interfaces

Constraining and Analyzing Source-Synchronous Interfaces Constraining and Analyzing Source-Synchronous Interfaces December 2007, ver. 2.0 Application Note 433 Introduction This application note describes techniques for constraining and analyzing source-synchronous

More information

EECS 427 Lecture 8: Adders Readings: EECS 427 F09 Lecture 8 1. Reminders. HW3 project initial proposal: due Wednesday 10/7

EECS 427 Lecture 8: Adders Readings: EECS 427 F09 Lecture 8 1. Reminders. HW3 project initial proposal: due Wednesday 10/7 EECS 427 Lecture 8: dders Readings: 11.1-11.3.3 3 EECS 427 F09 Lecture 8 1 Reminders HW3 project initial proposal: due Wednesday 10/7 You can schedule a half-hour hour appointment with me to discuss your

More information

Motivation for CDR: Deserializer (1)

Motivation for CDR: Deserializer (1) Motivation for CDR: Deserializer (1) Input data 1:2 DMUX 1:2 DMUX channel 1:2 DMUX Input clock 2 2 If input data were accompanied by a well-synchronized clock, deserialization could be done directly. EECS

More information

An Analytical Model for Interdependent Setup/Hold-Time Characterization of Flip-flops

An Analytical Model for Interdependent Setup/Hold-Time Characterization of Flip-flops An Analytical Model for Interdependent Setup/Hold-Time Characterization of Flip-flops Hadi Ahmadi Balef 1, Hailong Jiao 1, José Pineda de Gyvez 1, Kees Goossens 1, 1 Eindhoven University of Technology,

More information

EECS150 - Digital Design Lecture 18 - Counters

EECS150 - Digital Design Lecture 18 - Counters EECS150 - Digital Design Lecture 18 - Counters October 24, 2002 John Wawrzynek Fall 2002 EECS150 - Lec18-counters Page 1 Counters Special sequential circuits (FSMs) that sequence though a set outputs.

More information

EECS150 - Digital Design Lecture 18 - Counters

EECS150 - Digital Design Lecture 18 - Counters EECS50 - Digital Design Lecture 8 - Counters October 24, 2002 John Wawrzynek Fall 2002 EECS50 - Lec8-counters Page Counters Special sequential circuits (FSMs) that sequence though a set outputs. Examples:

More information

EE371 - Advanced VLSI Circuit Design

EE371 - Advanced VLSI Circuit Design EE371 - Advanced VLSI Circuit Design Midterm Examination May 7, 2002 Name: No. Points Score 1. 18 2. 22 3. 30 TOTAL / 70 In recognition of and in the spirit of the Stanford University Honor Code, I certify

More information

Lecture 25. Dealing with Interconnect and Timing. Digital Integrated Circuits Interconnect

Lecture 25. Dealing with Interconnect and Timing. Digital Integrated Circuits Interconnect Lecture 25 Dealing with Interconnect and Timing Administrivia Projects will be graded by next week Project phase 3 will be announced next Tu.» Will be homework-like» Report will be combined poster Today

More information

EEC 216 Lecture #3: Power Estimation, Interconnect, & Architecture. Rajeevan Amirtharajah University of California, Davis

EEC 216 Lecture #3: Power Estimation, Interconnect, & Architecture. Rajeevan Amirtharajah University of California, Davis EEC 216 Lecture #3: Power Estimation, Interconnect, & Architecture Rajeevan Amirtharajah University of California, Davis Outline Announcements Review: PDP, EDP, Intersignal Correlations, Glitching, Top

More information

EE 560 CHIP INPUT AND OUTPUT (I/0) CIRCUITS. Kenneth R. Laker, University of Pennsylvania

EE 560 CHIP INPUT AND OUTPUT (I/0) CIRCUITS. Kenneth R. Laker, University of Pennsylvania 1 EE 560 CHIP INPUT AND OUTPUT (I/0) CIRCUITS 2 -> ESD PROTECTION CIRCUITS (INPUT PADS) -> ON-CHIP CLOCK GENERATION & DISTRIBUTION -> OUTPUT PADS -> ON-CHIP NOISE DUE TO PARASITIC INDUCTANCE -> SUPER BUFFER

More information

Chapter 3. Chapter 3 :: Topics. Introduction. Sequential Circuits

Chapter 3. Chapter 3 :: Topics. Introduction. Sequential Circuits Chapter 3 Chapter 3 :: Topics igital esign and Computer Architecture, 2 nd Edition avid Money Harris and Sarah L. Harris Introduction Latches and Flip Flops Synchronous Logic esign Finite State Machines

More information

EE141. Lecture 28 Multipliers. Lecture #20. Project Phase 2 Posted. Sign up for one of three project goals today

EE141. Lecture 28 Multipliers. Lecture #20. Project Phase 2 Posted. Sign up for one of three project goals today EE141-pring 2008 igital Integrated ircuits Lecture 28 Multipliers 1 Announcements Project Phase 2 Posted ign up for one of three project goals today Graded Phase 1 and Midterm 2 will be returned next Fr

More information

Review: Designing with FSM. EECS Components and Design Techniques for Digital Systems. Lec 09 Counters Outline.

Review: Designing with FSM. EECS Components and Design Techniques for Digital Systems. Lec 09 Counters Outline. Review: esigning with FSM EECS 150 - Components and esign Techniques for igital Systems Lec 09 Counters 9-28-0 avid Culler Electrical Engineering and Computer Sciences University of California, Berkeley

More information

Digital Circuits ECS 371

Digital Circuits ECS 371 Digital Circuits ECS 371 Dr. Prapun Suksompong prapun@siit.tu.ac.th Lecture 18 Office Hours: BKD 3601-7 Monday 9:00-10:30, 1:30-3:30 Tuesday 10:30-11:30 1 Announcement Reading Assignment: Chapter 7: 7-1,

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS

More information

CPE/EE 422/522. Chapter 1 - Review of Logic Design Fundamentals. Dr. Rhonda Kay Gaede UAH. 1.1 Combinational Logic

CPE/EE 422/522. Chapter 1 - Review of Logic Design Fundamentals. Dr. Rhonda Kay Gaede UAH. 1.1 Combinational Logic CPE/EE 422/522 Chapter - Review of Logic Design Fundamentals Dr. Rhonda Kay Gaede UAH UAH Chapter CPE/EE 422/522. Combinational Logic Combinational Logic has no control inputs. When the inputs to a combinational

More information

Last lecture Counter design Finite state machine started vending machine example. Today Continue on the vending machine example Moore/Mealy machines

Last lecture Counter design Finite state machine started vending machine example. Today Continue on the vending machine example Moore/Mealy machines Lecture 2 Logistics HW6 due Wednesday Lab 7 this week (Tuesday exception) Midterm 2 Friday (covers material up to simple FSM (today)) Review on Thursday Yoky office hour on Friday moved to Thursday 2-:2pm

More information

Introduction EE 224: INTRODUCTION TO DIGITAL CIRCUITS & COMPUTER DESIGN. Lecture 6: Sequential Logic 3 Registers & Counters 5/9/2010

Introduction EE 224: INTRODUCTION TO DIGITAL CIRCUITS & COMPUTER DESIGN. Lecture 6: Sequential Logic 3 Registers & Counters 5/9/2010 EE 224: INTROUCTION TO IGITAL CIRCUITS & COMPUTER ESIGN Lecture 6: Sequential Logic 3 Registers & Counters 05/10/2010 Avinash Kodi, kodi@ohio.edu Introduction 2 A Flip-Flop stores one bit of information

More information

King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department

King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department Page 1 of 13 COE 202: Digital Logic Design (3-0-3) Term 112 (Spring 2012) Final

More information

Generalized FSM model: Moore and Mealy

Generalized FSM model: Moore and Mealy Lecture 18 Logistics HW7 is due on Monday (and topic included in midterm 2) Midterm 2 on Wednesday in lecture slot cover materials up to today s lecture Review session Tuesday 4:15pm in EEB125 Last lecture

More information

Sequential Circuit Timing. Young Won Lim 11/6/15

Sequential Circuit Timing. Young Won Lim 11/6/15 Copyright (c) 2011 2015 Young W. Lim. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published

More information

Next, we check the race condition to see if the circuit will work properly. Note that the minimum logic delay is a single sum.

Next, we check the race condition to see if the circuit will work properly. Note that the minimum logic delay is a single sum. UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on May 1, 2003 by Dejan Markovic (dejan@eecs.berkeley.edu) Prof. Jan Rabaey EECS

More information

University of Toronto. Final Exam

University of Toronto. Final Exam University of Toronto Final Exam Date - Apr 18, 011 Duration:.5 hrs ECE334 Digital Electronics Lecturer - D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last

More information

Itanium TM Processor Clock Design

Itanium TM Processor Clock Design Itanium TM Processor Design Utpal Desai 1, Simon Tam, Robert Kim, Ji Zhang, Stefan Rusu Intel Corporation, M/S SC12-502, 2200 Mission College Blvd, Santa Clara, CA 95052 ABSTRACT The Itanium processor

More information

Chapter 7. Sequential Circuits Registers, Counters, RAM

Chapter 7. Sequential Circuits Registers, Counters, RAM Chapter 7. Sequential Circuits Registers, Counters, RAM Register - a group of binary storage elements suitable for holding binary info A group of FFs constitutes a register Commonly used as temporary storage

More information

CSE 140 Midterm 2 - Solutions Prof. Tajana Simunic Rosing Spring 2013

CSE 140 Midterm 2 - Solutions Prof. Tajana Simunic Rosing Spring 2013 CSE 140 Midterm 2 - Solutions Prof. Tajana Simunic Rosing Spring 2013 Do not start the exam until you are told. Write your name and PID at the top of every page. Do not separate the pages. Turn off and

More information

Models for representing sequential circuits

Models for representing sequential circuits Sequential Circuits Models for representing sequential circuits Finite-state machines (Moore and Mealy) Representation of memory (states) Changes in state (transitions) Design procedure State diagrams

More information

Frequency Detection of CDRs (1)

Frequency Detection of CDRs (1) Frequency Detection of CDs (1) ecall that faster PLL locking can be accomplished by use of a phase-frequency detector (PFD): V in V up V up V dn -4 π -2 π +2 π +4 π φ in φ out 2V swing V f V dn K pd =

More information

Digital Logic Design - Chapter 4

Digital Logic Design - Chapter 4 Digital Logic Design - Chapter 4 1. Analyze the latch circuit shown below by obtaining timing diagram for the circuit; include propagation delays. Y This circuit has two external input and one feedback

More information

EECS 151/251A Homework 5

EECS 151/251A Homework 5 EECS 151/251A Homework 5 Due Monday, March 5 th, 2018 Problem 1: Timing The data-path shown below is used in a simple processor. clk rd1 rd2 0 wr regfile 1 0 ALU REG 1 The elements used in the design have

More information

MASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences

MASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences MASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences Analysis and Design of Digital Integrated Circuits (6.374) - Fall 2003 Quiz #2 Prof. Anantha Chandrakasan

More information

Laboratory Exercise #8 Introduction to Sequential Logic

Laboratory Exercise #8 Introduction to Sequential Logic Laboratory Exercise #8 Introduction to Sequential Logic ECEN 248: Introduction to Digital Design Department of Electrical and Computer Engineering Texas A&M University 2 Laboratory Exercise #8 1 Introduction

More information

State & Finite State Machines

State & Finite State Machines State & Finite State Machines Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell University See P&H Appendix C.7. C.8, C.10, C.11 Stateful Components Until now is combinatorial logic Output

More information

EE141Microelettronica. CMOS Logic

EE141Microelettronica. CMOS Logic Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit

More information

Chapter 3. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 3 <1>

Chapter 3. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 3 <1> Chapter 3 Digital Design and Computer Architecture, 2 nd Edition David Money Harris and Sarah L. Harris Chapter 3 Chapter 3 :: Topics Introduction Latches and Flip-Flops Synchronous Logic Design Finite

More information

LOGIC CIRCUITS. Basic Experiment and Design of Electronics. Ho Kyung Kim, Ph.D.

LOGIC CIRCUITS. Basic Experiment and Design of Electronics. Ho Kyung Kim, Ph.D. Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Digital IC packages TTL (transistor-transistor

More information

Luis Manuel Santana Gallego 31 Investigation and simulation of the clock skew in modern integrated circuits

Luis Manuel Santana Gallego 31 Investigation and simulation of the clock skew in modern integrated circuits Luis Manuel Santana Gallego 31 Investigation and simulation of the clock skew in modern egrated circuits 3. Clock skew 3.1. Definitions For two sequentially adjacent registers, as shown in figure.1, C

More information

CPE100: Digital Logic Design I

CPE100: Digital Logic Design I Professor Brendan Morris, SEB 3216, brendan.morris@unlv.edu CPE100: Digital Logic Design I Midterm02 Review http://www.ee.unlv.edu/~b1morris/cpe100/ 2 Logistics Thursday Nov. 16 th In normal lecture (13:00-14:15)

More information