EECS 427 Lecture 14: Timing Readings: EECS 427 F09 Lecture Reminders
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1 EECS 427 Lecture 14: Timing Readings: EECS 427 F09 Lecture 14 1 Reminders CA assignments Please submit CA6 by tomorrow noon CA7 is due in a week Seminar by Prof. Bora Nikolic SRAM variability in space and time 11 am, Friday 11/6, 3427 EECS HW4 (detailed proposal) is due 11/ weeks away You should have completed your schematic design and simulation and started block layouts by then uiz 2 on Monday 11/ weeks away Your chance to improve your performance in uiz 1 EECS 427 F09 Lecture
2 Synchronous Timing CLK In R Combinational 1 R 2 Out EECS 427 F09 Lecture 14 3 Latch Parameters t hold T t su t c-q t d-q elays can be different for rising and falling data transitions EECS 427 F09 Lecture
3 Register (FF) Parameters T t hold t su t c-q elays can be different for rising and falling data transitions EECS 427 F09 Lecture 14 5 More Precise Setup efinition t t Setup time is a fairly vague concept The correct data can be captured but the delay can be greatly affected Where is the threshold? Minimum - delay is the fastest possible way to transfer input to output, related to the sum of T setup and T clk- EECS 427 F09 Lecture 14 6 t 3
4 Setup Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 M - elay Inv1 CP T - ata Clock t=0 EECS 427 F09 Lecture 14 7 Setup Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 M - elay Inv1 CP T - ata Clock t=0 EECS 427 F09 Lecture
5 Setup Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 M - elay Inv1 CP T - ata Clock t=0 EECS 427 F09 Lecture 14 9 Setup Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 M - elay Inv1 T - CP ata Clock t=0 EECS 427 F09 Lecture
6 Setup Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 M - elay T - Inv1 CP ata Clock t=0 EECS 427 F09 Lecture and setup time summary efine setup time as the point at which CLK- delay rises 5% beyond nominal Nominal is measured when data arrives much earlier than CLK edge This corresponds roughly to where the total - delay is minimized EECS 427 F09 Lecture
7 Clock Waveform Nonidealities Clock skew Spatial variation in temporally equivalent clock edges, Clock jitter Temporal variations in consecutive edges of the clock signal Cycle-to-cycle (short-term) t JS Long term t JL Variation of the pulse width (duty cycle) Important for level sensitive (latch-based) clocking EECS 427 F09 Lecture Clock Skew and Jitter t JS Both skew and jitter impact the effective cycle time EECS 427 F09 Lecture
8 Clock Uncertainties evices 2 4 Power Supply 3 Interconnect t 6 Capacitive Load 1 Clock Generation 5 Temperature 7 Coupling to Adjacent Lines Sources of clock uncertainty EECS 427 F09 Lecture Jitter Sources Caused by variations in clock period that result from: Phased-lock loop (PLL) oscillation frequency Various noise sources affecting clock generation and distribution Ex. Power supply noise which dynamically alters the drive strength of intermediate buffer stages Cypress Semi EECS 427 F09 Lecture
9 IBM microprocessor clock skew # of paths EECS 427 F09 Lecture Idealized View of Clock Skew # of registers Earliest occurrence of edge Nominal /2 Latest occurrence of edge Nominal + /2 Clock network delay Max skew delay EECS 427 F09 Lecture
10 Positive and Negative Skew In R1 Combinational R2 Combinational R3 CLK t CLK1 t CLK2 t CLK3 delay (a) Positive skew delay In R1 Combinational R2 Combinational R3 t CLK1 t CLK2 t CLK3 delay delay CLK (b) Negative skew EECS 427 F09 Lecture Positive Skew, > 0 T CLK CLK1 1 T CLK 3 CLK2 2 4 t hold Launching edge arrives before the receiving edge Good for performance, bad for hold time Key: Hold time violations cannot be fixed by running the clock slower! EECS 427 F09 Lecture
11 Negative Skew, < 0 T CLK + CLK1 1 T CLK 3 CLK2 2 4 Receiving edge arrives before the launching edge Bad for performance, good for hold time violations EECS 427 F09 Lecture Timing Constraints In R1 Combinational R2 CLK t CLK1 t CLK2 t c q t c q, cd t su, t hold t logic t logic, cd Minimum cycle time: T t c-q + t su + t logic - Worst case is when receiving edge arrives early (negative ) EECS 427 F09 Lecture
12 Timing Constraints In R1 Combinational R2 CLK t CLK1 t CLK2 t c q t c q, cd t su, t hold t logic t logic, cd Hold time constraint: t (c-q, cd) + t (logic, cd) > t hold + Worst case is when receiving edge arrives late (positive skew) Race between data and clock cd: contamination delay (fastest possible delay) EECS 427 F09 Lecture Impact of Jitter T CLK CLK -t ji tte r t jitter In REGS CLK t c-q, t c-q, cd t su, t hold t jitter Combinational t logic t logic, cd 24 EECS 427 F09 Lecture 14 12
13 Longest Path T - T T LM T SU T JI + JI Latest point of launching Earliest arrival of next cycle 25 EECS 427 F09 Lecture 14 Clock Constraints If launching edge is late and receiving edge is early, the data will not be too late if: T c-q + T LM + T SU < T T JI,1 T JI,2 - Minimum cycle time is determined by the maximum delays through the logic T c-q + T LM + T SU T JI < T Skew can be either positive or negative 26 EECS 427 F09 Lecture 14 13
14 Shortest Path Earliest point of launching T - T Lm T H Nominal clock edge ata must not arrive before this time 27 EECS 427 F09 Lecture 14 Clock Constraints If launching edge is early and receiving edge is late: T c-q + T LM T JI,1 < T H + T JI,2 + Minimum logic delay T c-q + T LM < T H + 2T JI + 28 EECS 427 F09 Lecture 14 14
15 How to counter Clock Skew? Negative Skew REG REG. REG log Out In REG Positive Skew Clock istribution ib ti ata and Clock Routing 29 EECS 427 F09 Lecture 14 Latch timing t - When data arrives to transparent latch Latch is a soft barrier t - When data arrives to closed latch ata has to be re-launched 30 EECS 427 F09 Lecture 14 15
16 Single-Phase Clock with Latches Latch T skl T skl T skt T skt PW P 31 EECS 427 F09 Lecture 14 Latch-Based esign L1 latch is transparent when = 0 L2 latch is transparent when = 1 L1 Latch L2 Latch 32 EECS 427 F09 Lecture 14 16
17 Slack-borrowing In L1 CLB_A L2 L1 CLB_B t a pd,a b c t pd,b db d e CLK1 CLK2 CLK1 T CLK CLK1 CLK2 slack passed to next stage t pd,a t t pd,b t a valid b valid c valid e valid d valid 33 EECS 427 F09 Lecture 14 Conclusions Clocks strongly impact IC performance (timing) and are not ideal Skew and jitter are commonly discussed non-idealities Skew is typically larger and more heavily focused on More on skew later in class when we discuss clock distribution techniques Rough rule of thumb: skew should be kept < 10% of clock period Sequential elements eat up a significant amount of total timing budget + power resources They are therefore extremely important to design carefully Robustness is critical as well EECS 427 F09 Lecture
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