CHAPTER 3 MODELS FOR CMOS COMPONENTS

Transcription

1 Chapter 3 Introduction (12/2/6) Page 3.-1 CHAPTER 3 MODELS FOR CMOS COMPONENTS INTRODUCTION Chapter Outline 3.1 Large Signal Transistor Models 3.2 Process, Voltage, and Temperature Variations 3.3 Small Signal Transistor Model 3.4 Passive Component Models 3.5 Matching of Components 3.6 SPICE Models 3.7 Model Extraction 3.8 Summary Chapter 3 Introduction (12/2/6) Page 3.-2 Models Suitable for Understanding Analog Design The model required for analog design with CMOS technology is one that leads to understanding and insight as distinguished from accuracy. Technology Understanding and Usage Updating Model Thinking Model Simple, ±1% to ±5% accuracy Updating Technology Comparison of simulation with expectations Design Decisions- "What can I change to accomplish...?" Expectations "Ballpark" Computer Simulation Extraction of Simple Model Parameters from Computer Models Refined and optimized design Fig.3.-2 This chapter is devoted to the simple model suitable for design not using simulation.

2 Chapter 3 Introduction (12/2/6) Page 3.-3 Categorization of Electrical Models Linearity Linear Nonlinear Time Independent Small-signal, midband R in, A v, R out (.TF) DC operating point i D = f(v D,v G,v S,v B ) (.OP) Time Dependence Time Dependent Small-signal frequency response-poles and zeros (.AC) Large-signal transient response - Slew rate (.TRAN) Based on the simulation capabilities of SPICE. Chapter 3 Section 1 (12/2/6) Page SECTION 3.1 LARGE SIGNAL TRANSISTOR MOSFET MODELS OPERATION OF THE MOSFET TRANSISTOR Formation of the Channel for an Enhancement MOS Transistor Subthreshold (V G <V T ) V B = p+ p- substrate Threshold (V G =V T ) V B = V S = V G =V T V D = Polysilicon p+ ;; n+ ;;; n+ p- substrate p+ V S = V G < V T V D = ;; n + Polysilicon Depletion Region Inverted Region ;;; Polysilicon ;;; n + Strong Threshold (V G >V T ) V B = V S = V G >V T V D = n+ n+ p- substrate Inverted Region CMOS Analog Circuit Design Fig P.E. Allen - 26

3 Chapter 3 Section 1 (12/2/6) Page Transconductance Characteristics of an Enhancement NMOSFET when V DS =.1V V GS V T : V B = p+ p- substrate V GS =2V T : V B = p+ p- substrate V GS =3V T : V B = V S = v G =V T V D =.1V i D Polysilicon n+ n+ ;; ;;; Depletion Region VS = V G = 2V T V D =.1V i D i D Polysilicon ;; n+ ;;;;;; n+ Inverted Region ;;; Polysilicon V S = V G = 3V T V D =.1V i D i D V T V T 2V T 3V T 2V T 3V T v GS v GS p+ n+ n+ p- substrate Inverted Region V T 2V T 3V T v GS Fig Chapter 3 Section 1 (12/2/6) Page Output Characteristics of the Enhancement NMOS Transistor for V GS = 2V T V DS =: V B = V S = v G =2V T VD = V i D Polysilicon i D p+ p- substrate n+ n+ ;; ;;; Inverted Region V DS =.5V T : V B = V S = V G = 2V T V D =.5V T Polysilicon i D p+ ;; n+ ;;;; ;;; n+ i D p- substrate Channel current V DS =V T : V B = V S ;;; = V G = 2V T V D =V T i D i D Polysilicon V GS = 2V T v DS.5V T V T V GS = 2V T v DS.5V T V T V GS = 2V T p+ n+ n+ p- substrate A depletion region forms between the drain and channel.5v T V T v DS Fig.3.1-4

4 Chapter 3 Section 1 (12/2/6) Page Output Characteristics of the Enhanced NMOS when v DS = 2V T V GS =V T : V B = V S = v G =V T V D = 2V T i D p+ p- substrate Polysilicon n+ n+ ;; ;;; V GS =2V T : V B = V S = V G = 2V T V D = 2V T i D Polysilicon p+ ;;;; n+ n+ ;; ;;; i D i D V T V GS =V T 2V T 3V T V GS =2V T v DS p- substrate V GS =3V T : V B = V S ;;; = V G = 3V T V D = 2V T i D Polysilicon i D V T 2V T 3V T V GS =3V T v DS p+ p- substrate n+ n+ Further increase in V G will cause the FET to become active Fig V T 2V T 3V T v DS Chapter 3 Section 1 (12/2/6) Page Output Characteristics of an Enhancement NMOS Transistor 2 VGS = id(μa) 1 VGS = 2.5 SPICE Input File: Output Characteristics for NMOS M1 6 1 MOS1 w=5u l=1.u VGS M2 6 2 MOS1 w=5u l=1.u VGS M3 6 3 MOS1 w=5u l=1.u VGS M4 6 4 MOS1 w=5u l=1.u VGS VGS = 2. VGS = 1.5 VGS = vds (Volts) Fig M5 6 5 MOS1 w=5u l=1.u VGS VDS 6 5.model mos1 nmos (vto=.7 kp=11u +gamma=.4 +lambda=.4 phi=.7).dc vds 5.2.print dc ID(M1), ID(M2), ID(M3), ID(M4), ID(M5).end

5 Chapter 3 Section 1 (12/2/6) Page Transconductance Characteristics of an Enhancement NMOS Transistor V DS = 4V V DS = 3V V DS = 5V id(μa) V DS = 2V V DS = 1V SPICE Input File: Transconductance Characteristics for NMOS M1 1 6 MOS1 w=5u l=1.u VDS M2 2 6 MOS1 w=5u l=1.u VDS M3 3 6 MOS1 w=5u l=1.u VDS M4 4 6 MOS1 w=5u l=1.u VDS v GS (Volts) Fig M5 5 6 MOS1 w=5u l=1.u VDS VGS 6 5.model mos1 nmos (vto=.7 kp=11u +gamma=.4 lambda=.4 phi=.7).dc vgs 5.2.print dc ID(M1), ID(M2), ID(M3), ID(M4), ID(M5).probe.end Chapter 3 Section 1 (12/2/6) Page SIMPLE LARGE SIGNAL MODEL (SAH MODEL) Large Signal Model Derivation 1.) Let the charge per unit area in the channel inversion layer be QI(y) = -Cox[vGS-v(y)-VT] (coul./cm 2 ) 2.) Define sheet conductivity of the inversion layer per square as cm2 coulombs S = μoqi(y) v s cm2 = amps volt = 1 3.) Ohm's Law for current in a sheet is JS = i D dv W = -SEy = -S dy dv = -i D 4.) Integrating along the channel for to L gives /sq. SW dy = L v DSWμ v DSWμ i Ddy = - oqi(y)dv = oc ox [vgs-v(y)-vt] dv 5.) Evaluating the limits gives L id = Wμ ocox (vgs-vt)v(y) - v 2(y) 2 v DS n + n v(y) + dy p Source Drain - y yy+dy L -i D dy μ o Q I (y)w i D dy = -Wμ o Q I (y)dv L id = Wμ ocox v GS + - id (vgs-vt)vds - v DS v DS Fig.11-3

6 Chapter 3 Section 1 (12/2/6) Page Saturation Voltage - V DS (sat) Interpretation of the large signal model: i D Active Region v DS = v GS -V T Saturation Region Increasing values of v GS The saturation voltage for MOSFETs is the value of drain-source voltage at the peak of the inverted parabolas. di D dv DS = μ v DS oc ox W L [(v GS -V T ) - v DS ] = Cutoff Saturation Active v DS (sat) = v GS - V T Useful definitions: μ o C ox W L = K W L = v DS = v GS - V T v DS Fig v GS V T Fig Chapter 3 Section 1 (12/2/6) Page The Simple Large Signal MOSFET Model Regions of Operation of the MOS Transistor: 1.) Cutoff Region: v GS - V T < i D = (Ignores subthreshold currents) 2.) Active Region Output Characteristics of the MOSFET: < v DS < v GS - V T i D /I D v DS = v GS -V T i D = μ ocoxw 2L 2(v GS - V T ) - v DS 1. Active v DS Region Saturation Region 3.) Saturation Region < v GS - V T < v DS id = μ o CoxW 2L v GS - V T Channel modulation effects.25 Cutoff Region v GS -V T V GS -V T v GS -V T V GS -V T v GS -V T V GS -V T v GS -V T V GS -V T v GS -V T = 1. =.867 =.77 =.5 = V GS -V T v DS V GS -V T Fig. 11-5

7 Chapter 3 Section 1 (12/2/6) Page Illustration of the Need to Account for the Influence of v DS on the Simple Sah Model Compare the Simple Sah model to SPICE level 2: 25μA 2μA 15μA i D 1μA 5μA 2 K' = 44.8μA/V k =, v DS (sat) = 1.V 2 K' = 44.8μA/V k=.5, v DS (sat) = 1.V SPICE Level 2 2 K' = 29.6μA/V k =, v (sat) DS = 1.V μa v DS (volts) V GS = 2.V, W/L = 1μm/1μm, and no mobility effects. Chapter 3 Section 1 (12/2/6) Page Modification of the Previous Model to Include the Effects of v DS on V T From the previous derivation: L v DSWμo v DSWμo id dy = - Q I (y)dv = C ox [v GS - v(y) -V T ]dv Assume that the threshold voltage varies across the channel in the following way: V T (y) = V T + kv(y) where V T is the value of V T the at the source end of the channel and k is a constant. Integrating the above gives, or L i D = Wμ oc ox (v GS -V T )v(y) - (1+k) v2 (y) 2 i D = Wμ oc ox L (v GS -V T )v DS - (1+k) v2 DS 2 To find v DS (sat), set the di D /dv DS equal to zero and solve for v DS = v DS (sat), v DS v DS (sat) = v GS - V T 1 + k Therefore, in the saturation region, the drain current is i D = Wμ oc ox 2(1+k)L (v GS - V T ) 2 For k =.5 and K = 44.8μA/V2, excellent correlation is achieved with SPICE 2.

8 Chapter 3 Section 1 (12/2/6) Page Influence of V DS on the Output Characteristics Channel modulation effect: As the value of v DS increases, the B effective L decreases causing the current to increase. Illustration: Note that L eff = L - X d Therefore the model in saturation becomes, i D = K W 2L eff (v GS -V T )2 p- substrate Polysilicon p+ ;;;;;;; n+ n+ di D dv DS = - K W 2L eff 2 (v GS - V T ) 2 dl eff dv DS = i D Leff dx d dv DS i D Therefore, a good approximation to the influence of v DS on i D is V G > V T VD > V DS (sat) i D i D ( = ) + di D dv DS v DS = i D ( = )(1 + v DS ) = K W 2L (v GS-V T ) 2 (1+v DS ) S L eff X d Depletion Region Fig11-6 Chapter 3 Section 1 (12/2/6) Page Channel Length Modulation Parameter, Assume the MOS is transistor is saturated- i D = μc oxw 2L (v GS - V T ) 2 (1 + v DS ) Define i D () = i D when v DS = V. i D () = μc oxw 2L (v GS- V T ) 2 Now, i D = i D ()[1 + v DS ] = i D () + i D () v DS Matching with y = mx + b gives the value of -1 i D3 () i D2 () i D1 () i D V GS3 V GS2 V GS1 v DS

9 Chapter 3 Section 1 (12/2/6) Page Influence of Channel Length on Note that the value of varies with channel length, L. The data below is from a.25μm CMOS technology. Channel Length Modulation (V-1) NMOS PMOS Channel Length (microns) Fig.13-6 Most analog designers stay away from minimum channel length to get better gains and matching at the sacrifice of speed. Chapter 3 Section 1 (12/2/6) Page Influence of the Bulk Voltage on the Large Signal MOSFET Model The components of the threshold voltage V SB = : are: V T = Gate-bulk work function ( MS ) V BS = V V GS + voltage to change the surface potential (-2 F ) p+ p- substrate n+ + voltage to offset the channel-bulk depletion charge (-Q b /C ox ) V SB1 > : V BS1 > V V GS + voltage to compensate the undesired interface charge (-Q ss /C ox ) p+ p- substrate n+ We know that Q b = 2F + vbs V SB2 >V SB1 : V SB2 >V SB1 : V GS Therefore, as the bulk becomes more reverse biased with respect to the source, the threshold voltage must increase to offset the increased channelbulk depletion charge. Polysilicon p+ p- substrate Polysilicon Polysilicon V D > i D n+ V D > n+ V D > n+ n+ i D i D =

10 Chapter 3 Section 1 (12/2/6) Page Influence of the Bulk Voltage on the Large Signal MOSFET Model - Continued Bulk-Source (vbs) influence on the transconductance characteristics- i D Decreasing values of bulk-source voltage V BS = I D v DS > v GS -V T V GS v V T V GS T1 V T2 V T In general, the simple model incorporates the bulk effect into VT by the previously developed relationship: VT(vBS) = VT + 2 f + vbs - 2 f Chapter 3 Section 1 (12/2/6) Page Summary of the Simple Large Signal MOSFET Model N-channel reference convention: Non-saturation- L i D G + v GS D + B v + DS v BS id = Wμ ocox (vgs - VT)vDS - v DS 2 2 (1 + v DS) - - S Fig SaturationiD = Wμ ocox L (vgs-vt)vds(sat) - v DS(sat) 2 2 (1+vDS) = Wμ ocox 2L (vgs-vt) 2 (1+vDS) where: μo = zero field mobility (cm2/volt sec) Cox = gate oxide capacitance per unit area (F/cm2) = channel-length modulation parameter (volts-1) VT = VT + 2 f + vbs - 2 f VT = zero bias threshold voltage = bulk threshold parameter (volts-.5) 2 f = strong inversion surface potential (volts) For p-channel MOSFETs, use n-channel equations with p-channel parameters and invert the current.

11 Chapter 3 Section 1 (12/2/6) Page Silicon Constants Constant Symbol V G k ni o si ox Constant Description Value Units Silicon bandgap (27 C) Boltzmann s constant Intrinsic carrier concentration (27 C) Permittivity of free space Permittivity of silicon Permittivity of SiO x x x o 3.9 o V J/K cm-3 F/cm F/cm F/cm Chapter 3 Section 1 (12/2/6) Page MOSFET Parameters Model Parameters for a Typical CMOS Bulk Process (.25μm CMOS n-well): Parameter Symbol VT K' 2 F Parameter Description Threshold Voltage (V BS = ) Transconductance Parameter (in saturation) Bulk threshold parameter Channel length modulation parameter Surface potential at strong inversion Typical Parameter Value N-Channel P-Channel Units.5± ±.15 V 12. ± 1% 25. ± 1% μa/v2.4.6 (V)1/2.32 (L=L min ).6 (L 2L min ).56 (L=L min ).8 (L 2L min ) (V) V

12 Chapter 3 Section 1 (12/2/6) Page SUBTHRESHOLD MODEL Large-Signal Model for Weak Inversion The electrons in the substrate at the source side can be expressed as, s n p () = n po exp V t The electrons in the substrate at the drain side can be expressed as, n p (L) = n po exp s -v DS V t Therefore, the drain current due to diffusion is, i D = qad n p (L)- n p () n L = W L qxd nn po exp s V t 1 - exp - v DS V t where X is the thickness of the region in which i D flows. In weak inversion, the changes in the surface potential, s are controlled by changes in the gate-source voltage, v GS, through a voltage divider consisting of C ox and C js, the depletion region capacitance. d s C ox dv GS = C ox + C js = 1 n s = v GS n + k 1 = v Poly GS-V T n + k 2 Oxide C ox v Channel GS Dep. where C js φs k 2 = k 1 + V T n Substrate CMOS Analog Circuit Design P.E. Allen - 26 Chapter 3 Section 1 (12/2/6) Page Large-Signal Model for Weak Inversion Continued Substituting the above relationships back into the expression for i D gives, i D = W L qxd nn po exp k 2 V t exp v GS -V T nv t 1 - exp - v DS V t Define I t as k 2 I t = qxd n n po exp V t to get, i D = W L I t exp v GS -V T nv t 1 - exp - v DS V t where n If v DS >, then i D = I W t L exp v GS -V T nv t 1 + v DS V A The boundary between nonsaturated and saturated is found as, V ov = V DS (sat) = V ON = V GS -V T = 2nV t 1μA V GS =V T V GS <V T i D 1V v DS Fig. 14-3

13 Chapter 3 Section 1 (12/2/6) Page SHORT CHANNEL, STRONG INVERSION MODEL What is Velocity Saturation? The most important short-channel 15 effect in MOSFETs is the velocity saturation of carriers in the channel. 5x14 A plot of electron drift velocity 2x14 versus electric field is shown below. An expression for the electron drift velocity as a function of the electric field is, μ n E v d 1 + E/E c where v d = electron drift velocity (m/s) μ n = low-field mobility (.7m2/V s) E c = critical electrical field at which velocity saturation occurs Electron Drift Velocity (m/s) 14 5x Electric Field (V/m) Fig13-1 Chapter 3 Section 1 (12/2/6) Page Short-Channel Model Derivation As before, J D = J S = i D W = Q I (y)v d (y) i D = WQ I (y)v d (y) = WQ I(y)μ n E 1 + E/E c i D 1+ E E c = WQ I (y)μ n E Replacing E by dv/dy gives, i D dv E c dy = WQ dv I(y)μ n dy Integrating along the channel gives, L i D dv v DSWQI E c dy dy = (y)μ n dv The result of this integration is, μ n C ox W i D = v DS E L [2(v GS-V T )v DS -v DS 2] = c L where = 1/(E c L) with dimensions of V μ n C ox W 1 + v DS L [2(v GS-V T )v DS -v DS 2]

14 Chapter 3 Section 1 (12/2/6) Page Saturation Voltage Differentiating i D with respect to v DS and setting equal to zero gives, V DS (sat) = (V GS -V T -1 (V GS -V T ) 1 - (V GS-V T ) 2 + if (V GS -V T ) 2 < 1 Therefore, V DS (sat) V DS (sat) 1 - (V GS-V T ) 2 + Note that the transistor will enter the saturation region for v DS < v GS - V T in the presence of velocity saturation. Chapter 3 Section 1 (12/2/6) Page Large Signal Model for the Saturation Region Assuming that (V GS -V T ) 2 < 1 gives V DS (sat) (V GS -V T ) Therefore the large signal model in the saturation region becomes, K i D = W 2[1 + (v GS -V T )] L [ v GS - V T ]2, v DS (V GS -V T ) 1 - (V GS-V T ) 2 +

15 Chapter 3 Section 1 (12/2/6) Page The Influence of Velocity Saturation on the Transconductance Characteristics The following plot was made for K = 11μA/V2 and W/L = 1: id/w (μa/μm) 1 θ = θ =.2 8 θ =.4 6 θ =.6 4 θ =.8 θ = v GS (V) Fig13-2 Note as the velocity saturation effect becomes stronger, that the drain current-gate voltage relationship becomes linear. Chapter 3 Section 1 (12/2/6) Page Circuit Model for Velocity Saturation A simple circuit model to include the influence of velocity saturation is the following: We know that i D = K W 2L (v GS -V T )2 and v GS = v GS + i D R SX or v GS = v GS - i D R XS Substituting v GS into the current relationship gives, i D = K W 2L (v GS - i D R SX -V T )2 Solving for i D results in, i D = K K W L R SX(v GS -V T ) W L (v GS - V T )2 Comparing with the previous result, we see that = K W L R SX R SX = L K W = 1 E c K W Therefore for K = 11μA/V2, W = 1μm and E c = 1.5x16V/m, we get R SX = 6.6k. G + v GS Fig v GS '- - D R SX S i D

16 Chapter 3 Section 1 (12/2/6) Page Types of Capacitance Physical Picture: CAPACITANCES OF THE MOSFET SiO 2 Source Gate Drain C 1 C 2 C3 FOX C BS C 4 C BD FOX Bulk Fig12-6 MOSFET capacitors consist of: Depletion capacitances Charge storage or parallel plate capacitances Chapter 3 Section 1 (12/2/6) Page MOSFET Depletion Capacitors Model: 1.) vbs FC PB CBS = CJ AS 1 - v BS PB and 2.) vbs> FC PB CBS = MJ + CJSW PS 1 - v BS PB MJSW, CJ AS ( 1- FC) 1+MJ 1 - (1+MJ)FC + MJ V BS PB Source CJSW PS + ( 1 - FC) 1+MJSW 1 - (1+MJSW)FC + MJSW V BS PB where AS = area of the source v BS FC PB PS = perimeter of the source CJSW = zero bias, bulk source sidewall capacitance MJSW = bulk-source sidewall grading coefficient For the bulk-drain depletion capacitance replace "S" by "D" in the above. SiO 2 Polysilicon gate E A D Bulk Fig Drain bottom = ABCD Drain sidewall = ABFE + BCGF + DCGH + ADHE C BS H Drain F B FC PB G C v BS FC PB PB v BS Fig. 12-8

17 Chapter 3 Section 1 (12/2/6) Page Charge Storage (Parallel Plate) MOSFET Capacitances - C 1, C 2, C3 and C 4 LD Mask L Actual L (L eff ) Oxide encroachment Mask W Actual W (W eff ) Overlap capacitances: C1 = C3 = LD W eff Cox = CGSO or CGDO (LD.15 μm for LDD structures) Source-gate overlap capacitance C GS (C 1 ) FOX Source Gate-Channel Capacitance (C 2 ) Gate Gate Bulk Drain-gate overlap capacitance C GD (C 3 ) FOX Drain Channel-Bulk Capacitance (C 4 ) Fig Channel capacitances: C2 = gate-to-channel = CoxW eff (L-2LD) = CoxW eff L eff C4 = voltage dependent channelbulk/substrate capacitance Chapter 3 Section 1 (12/2/6) Page Charge Storage (Parallel Plate) MOSFET Capacitances - C 5 View looking down the channel from source to drain Overlap Overlap Gate FOXC 5 Source/Drain C 5 FOX Bulk Fig12-1 C 5 = CGBO Capacitance values based on an oxide thickness of 14 Å or C ox = F/m 2 : Type P-Channel N-Channel Units CGSO F/m CGDO F/m CGBO F/m CJ F/m 2 CJSW F/m MJ.5.5 MJSW.35.38

18 Chapter 3 Section 1 (12/2/6) Page Expressions for C GD, C GS and C GB Cutoff Region: C GB = C 2 +2C 5 = C ox (W eff )(L eff ) + 2CGBO(L eff ) C GS = C 1 C ox (LD)W eff = CGSO(W eff ) C GD = C 3 C ox (LD)W eff = CGDO(W eff ) Saturation Region: C GB = 2C 5 = CGBO(L eff ) C GS = C 1 +(2/3)C 2 = C ox (LD+.67L eff )(W eff ) = CGSO(W eff ) +.67C ox (W eff )(L eff ) C GD = C 3 C ox (LD)W eff ) = CGDO(W eff ) Nonsaturated Region: C GB = 2 C 5 = 2CGBO(L eff ) C GS = C 1 +.5C 2 = C ox (LD+.5L eff )(W eff ) = (CGSO +.5C ox L eff )W eff C GD = C 3 +.5C 2 = C ox (LD+.5L eff )(W eff ) = (CGDO +.5C ox L eff )W eff Cutoff V B = p+ p- substrate Saturated V B = p+ p- substrate Active V B = p+ p- substrate V S = V G < V T V D > C GS Polysilicon C GD n+ C GB n+ V S = V G >V T V D >V G -V T C GS Polysilicon CGD n+ n+ Inverted Region ;;; Polysilicon V S = C GS V G >V T V D <V G -V T C GD n+ n+ Inverted Region Fig12-11 Chapter 3 Section 1 (12/2/6) Page Illustration of C GD, C GS and C GB Comments on the variation of C BG in the cutoff region: 1 CBG = 1 C C5 C4 1.) For vgs, CGB C2 + 2C5 (C4 is large because of the thin inversion layer in weak inversion where V GS is slightly less than V T )) 2.) For < vgs VT, CGB 2C5 (C4 is small because of the thicker inversion layer in strong inversion) Capacitance C 4 Large C 2 + 2C 5 C C GS C 2 C GS, C C GD 1 +.5C 2 v DS = constant C1, C C GS, C GD C v GD BS = 3 2C C C GB 4 Small 5 vgs Off Saturation Non- Saturation V T v DS +V T Fig12-12

19 Chapter 3 Section 2 (12/2/6) Page SECTION 3.2 PROCESS, VOLTAGE, AND TEMPERATURE (PVT)VARIATIONS OF CMOS TECHNOLOGY PROCESS VARIATIONS How Does Technology Vary? 1.) Thickness variations in layers (dielectrics and metal) t ox (min) t ox (max) 2.) Doping variations n+ p+ p n-well Diffusion Differences ) Process biases differences between the drawn and actual dimensions due to process (etching, lateral diffusion, etc.) Drawn Dimension Actual Dimension Chapter 3 Section 2 (12/2/6) Page Large Signal Model Dependence on Process Variations 1.) Threshold voltage V T = V T + -2 F + v SB - -2 F where V T = MS - 2 F - Q b C ox - Q SS Cox and = 2q si N A Cox If V BS =, then V T is dependent on doping and oxide thickness because F = kt q ln N SUB n i and C ox 1 t ox (Recall that the threshold is also determined by the threshold implant during processing) 2.) Transconductance parameter K = μ o C ox 1 t ox For short channel devices, the mobility is degraded as given by μ o μ eff = 1 + (V GS - V T ) and 2x1-9 m/v t ox

20 Chapter 3 Section 2 (12/2/6) Page Process Variation Corners For strong inversion operation, the primary influence is the oxide thickness, t ox. We see that K will tend to increase with decreasing oxide thickness whereas V T tends to decrease. If the speed of a transistor is increased by increasing K and decreasing V T, then the variation of technology can be expressed on a two-dimensional graph resulting in a rectangular area of acceptable process limitation. PMOS Speed Large Kʼ Small V T Fast PMOS Slow PMOS Small Kʼ Large V T Slow NMOS Acceptable Technology Parameters Fast NMOS NMOS Speed Chapter 3 Section 2 (12/2/6) Page VOLTAGE VARIATION What is Voltage Variation? Voltage variation is the influence of power supply voltage on the component. (There is also power supply influence on the circuit called power supply rejection ratio, PSRR. We will deal with this much later.) Power supply variation comes from: 1.) Influence of depletion region widths on components. 2.) Nonlinearity 3.) Breakdown voltage Note: Because the large-signal model for the MOSFET includes all the influences of voltage on the transistor, we will focus on passive components except for breakdown.

21 Chapter 3 Section 2 (12/2/6) Page Models for Voltage Dependence of a Component 1.) ith-order Voltage Coefficients In general a variable y = f(v) which is a function of voltage, v, can be expressed as a Taylor series, y(v = V ) y(v ) + a 1 (v- V ) + a 2 (v- V ) 2 + a 3 (v- V ) 3 + where the coefficients, a i, are defined as, df(v) 1 a 1 = dv v=v, a 2 = d2 f(v) 2 dv 2 v=v,. The coefficients, a i, are called the first-order, second-order,. voltage coefficients. 2.) Fractional Voltage Coefficient or Voltage Coefficient Generally, only the first-order coefficients are of interest. In the characterization of temperature dependence, it is common practice to use a term called fractional voltage coefficient, VC F, which is defined as, 1 VC F (v=v ) = df(v) f(v=v ) dv v=v parts per million/v (ppm/v) or more simply, VC F = 1 df(v) f(v) dv parts per million/v (ppm/v) Chapter 3 Section 2 (12/2/6) Page Influence of Voltage on a Diffused Resistor Depletion Region Influence of the depletion region on the p + resistor: FOX p + Thickness of p+ Resistor FOX p+ Thickness of p+ Resistor p+ p- substrate n- well STI Depletion region n-well STI Older LOCOS Technology As the voltage at the terminals of the resistor become smaller than the n-well potential, the depletion region will widen causing the thickness of the resistor to decrease. R = L tw V R where V R is the reverse bias voltage from the resistor to the well. This effect is worse for well resistors because the doping concentration of the resistor is smaller. Voltage coefficient for diffused resistors 2-8 ppm/v Voltage coefficient for well resistors 8 ppm/v

22 Chapter 3 Section 2 (12/2/6) Page Voltage Nonlinearity Conductivity modulation: As the current in a resistor increases, the conductivity becomes modulated and the resistance increases. i i = v Example of a n-well resistor: R As the reverse bias voltage across a pn junction becomes large, at some point, called the breakdown voltage, the current will rapidly increase. Both transistors, diodes and depletion capacitors experience this breakdown. Model for current multiplication factor: 1 M = 1 + v R n BV.1A Conductivity modulation i R v Breakdown voltage BV vr Chapter 3 Section 2 (12/2/6) Page TEMPERATURE VARIATIONS Models for Voltage Dependence of a Component 1.) ith-order Temperature Coefficients As for voltage, the temperature dependence can be expressed as, y(t = T ) y(t ) + a 1 (T- T ) + a 2 (T- AT ) 2 + a 3 (T- T ) 3 + where the coefficients, a i, are defined as, df(t) 1 a 1 = dt T=T, a 2 = d2 f(t) 2 dt 2 T=T,. The coefficients, a i, are called the first-order, second-order,. temperature coefficients. 2.) Fractional Temperature Coefficient or Temperature Coefficient Generally, only the first-order coefficients are of interest. In the characterization of temperature dependence, it is common practice to use a term called fractional temperature coefficient, TC F, which is defined as, 1 TC F (T=T ) = df(t) f(t=t ) dt T=T parts per million/ C (ppm/ C) or more simply, 1 TC F = df(t) f(t) dt parts per million/ C (ppm/ C)

23 Chapter 3 Section 2 (12/2/6) Page Temperature Dependence of the MOSFET Transconductance parameter: K (T) = K (T ) (T/T ) -1.5 (Exponent becomes +1.5 below 77 K) Threshold Voltage: V T (T) = V T (T ) + (T-T ) + Typically NMOS = -2mV/ C to 3mV/ C from 2 K to 4 K (PMOS has a + sign) Example Find the value of I D for a NMOS transistor at 27 C and 1 C if V GS = 2V and W/L = 5μm/1μm if K (T ) = 11μA/V 2 and V T (T ) =.7V and T = 27 C and NMOS = -2mV/ C. Solution At room temperature, the value of drain current is, I D (27 C) = 11μA/V2 5μm 2 1μm (2-.7) 2 = 465μA At T = 1 C (373 K), K (1 C)=K (27 C) (373/3) -1.5 =11μA/V 2.72=79.3μA/V2 and V T (1 C) =.7 (.2)(73 C) =.554V I D (1 C) = 79.3μA/V2 5μm 2 1μm (2-.554) 2 = 415μA (Repeat with V GS = 1.5V) Chapter 3 Section 2 (12/2/6) Page Zero Temperature Coefficient (ZTC) Point for MOSFETs For a given value of gate-source voltage, the drain current of the MOSFET will be independent of temperature. Consider the following circuit: Assume that the transistor is saturated and that: I D μ = μ o T -1.5 T o and V T (T) = V T (T o ) + (T-T o ) V GS where = -.23V/ C and T o = 27 C I D (T) = μ Fig oc ox W T -1.5 T [VGS o V T - (T-T o )]2 2L di D dt = -1.5μ oc ox 2T o T T -2.5 T [VGS o -V T -(T-T o )]2+μ o C ox -1.5 T [VGS o -V T -(T-T o )] = V GS V T - (T-T o ) = -4T 3 V GS(ZTC) = V T - T o - 3 Let K = 1μA/V2, W/L = 5 and V T =.71V. At T=27 C(3 K), V GS (ZTC)=.71-(-.23)(3 K)-(.333)(-.23)(3 K)=1.63V At T = 27 C (3 K), I D = (1μA/V2)(5/2)( )2 = 21.2μA At T=2 C(473 K),V GS (ZTC)=.71-(-.23)(3 K)-(.333)(-.23)(473 K)=1.76V

24 Chapter 3 Section 2 (12/2/6) Page Experimental Verification of the ZTC Point The data below is for a 5μm n-channel MOSFET with W/L=5μm/1μm, N A =116 cm-3, t ox = 65Å, u o C ox = 1μA/V2, and V T =.71V. 1 8 V DS = 6V 25 C 1 C 15 C 2 C 25 C ID (A) C 3 C 15 C 2 C 25 C 275 C 25 C 1 C Zero TC Point V GS (V) A similar result holds for the p-channel MOSFET. UDSM technology may not yield a well-defined ZTC point. Chapter 3 Section 2 (12/2/6) Page Bulk-Drain (Bulk-Source) Leakage Currents Cross-section of a NMOS in a p-well: V GS >V T : B S V G > V T VD > V DS (sat) Depletion Polysilicon Region p+ ;;;;;;; n+ n+ p-well n- substrate V GS <V T : V G <V T Fig VD > V DS (sat) B S ;;; Polysilicon p+ n+ ;; n+ Depletion Region p-well n- substrate Fig.3.6-6

25 Chapter 3 Section 2 (12/2/6) Page Temperature Modeling of the PN Junction PN Junctions (Reverse-biased only): i D I s = qa Dppno L p + D nnpo L n qad n2 i L N = KT 3 exp V Go V t Differentiating with respect to temperature gives, di s dt = 3KT 3 T exp V Go V t + qkt 3 V Go KT exp V Go 2 V t = 3I s T + I s V Go T V t TC F = di s I s dt = 3 T + 1 V Go T V t Example Assume that the temperature is 3 (room temperature) and calculate the reverse diode current change and the TC F for a 5 increase. Solution The TC F can be calculated from the above expression as TC F = =.165. Since the TCF is change per degree, the reverse current will increase by a factor of for every degree (or C) change in temperature. Multiplying by five times gives an increase of approximately 2. Thus, the reverse saturation current approximately doubles for every 5 C temperature increase. Experimentally, the reverse current doubles for every 8 C increase in temperature because the reverse current is in part leakage current. Chapter 3 Section 2 (12/2/6) Page Experimental Verification of the PN Junction Temperature Dependence Theory: Leakage Current (A) C 5μm L min I R 2 C Data Symbol Min. L 6 μm 5 μm 4 μm 2 μm 1 C 1V Theory 1-1 matched at 15 C Generation Diffusion Recombination Leakage Leakage 1-12 Dominant Dominant /T ( K-1) Fig I s (T) T 3 exp V G (T) kt

26 Chapter 3 Section 2 (12/2/6) Page Temperature Modeling of the PN Junction Continued PN Junctions (Forward biased v D constant): v D i D I s exp Vt Differentiating this expression with respect to temperature and assuming that the diode voltage is a constant (v D = V D ) gives did dt = i D di s I s dt - 1 V D T Vt i D The fractional temperature coefficient for i D is 1 did i D dt = 1 di s Is dt - V D TV t = 3 T + VGo - VD TV t If V D is assumed to be.6 volts, then the fractional temperature coefficient is equal to.1+( ) =.879. The forward diode current will approx. double for a 1 C. PN Junctions (Forward biased i D constant): V D = V t ln(i D /I s ) Differentiating with respect to temperature gives dvd dt = v D T - V t 1 di s Is dt = v D T - 3V t T - V Go T = - VGo - vd T - 3V t T Assuming that v D = V D =.6 V the temperature dependence of the forward diode voltage at room temperature is approximately -2.3 mv/ C. Chapter 3 Section 2 (12/2/6) Page Resistor Dependence on Temperature Diffused Resistors: The temperature dependence of resistors depends mostly on the doping level of diffused and implanted resistors. As the doping level or sheet resistance increases from 1 / to 4 /, the temperature coefficient varies from about +1 ppm/ C to +4 ppm/ C. Diffused and implanted resistors have good thermal conduction to the substrate or well. Polysilicon Resistors: Typically has a sheet resistance of 2 / to 8 / and has poor thermal conduction because it is electrically isolated by oxide layers. Metal: Metal is often used for resistors and has a positive temperature coefficient. Temperature Coefficients of Resistors: n-well = 4 ppm/ C Diffusion = +15 ppm/ C Polysilicon = 5-2 ppm/ C Ion implanted = +4 ppm/ C Metal = +38 ppm/ C (aluminum)

27 Chapter 3 Section 3 (12/2/6) Page SECTION 3.3 SMALL SIGNAL TRANSISTOR MOSFET MODELS FREQUENCY INDEPENDENT What is a Small Signal Model? The small signal model is a linear approximation of a nonlinear model. Mathematically: i D = 2 (v GS - V T ) 2 Graphically: Large Signal to Small Signal i d = g m v gs i D i D = β(v GS -V T ) 2 i d The large signal curve at point Q has been approximated with a small signal model going through the point Q and having a slope of g m. I D Q i d = g m v gs v gs V T V GS v GS Chapter 3 Section 3 (12/2/6) Page Why Small Signal Models? The small signal model is a linear approximation to the large signal behavior. 1.) The transistor is biased at given DC operating point (Point Q above) 2.) Voltage changes are made about the operating point. 3.) Current changes result from the voltage changes. If the designer is interested in only the current changes and not the DC value, then the small signal model is a fast and simple way to find the current changes given the voltage changes. i d Large Signal Model i d = g m v gs Δi D Δi Dʼ Q v gs ΔV GS

28 Chapter 3 Section 3 (12/2/6) Page How Good is the Small Signal Model? It depends on how large are the changes and how nonlinear is the large signal model. The parameters of the small signal model will depend on the values of the large signal model. The model is a tradeoff in complexity versus accuracy (we will choose simplicity and give up accuracy). What does a simulator do? Exactly the same thing when it makes an ac analysis (i.e. frequency response) Regardless of the approximate nature of the small signal model, it is the primary model used to predict the signal performance of an analog circuit. Chapter 3 Section 3 (12/2/6) Page Small-Signal Model for the Saturation Region The small-signal model is a linearization of the large signal model about a quiescent or operating point. Consider the large-signal MOSFET in the saturation region (v DS v GS V T ) : i D = Wμ ocox 2L (vgs - VT) 2 (1 + vds) The small-signal model is the linear dependence of i d on v gs, v bs, and v ds. Written as, i d g m v gs + g mbs v bs + g ds v ds where g m di D dv GS Q = (V GS-V T ) = 2I D and g ds di D dv DS Q = I D 1 + V DS I D g mbs d D dv BS Q = di D dv GS dv GS dv BS Q = - di D dv T dv T dv BS Q = g m 2 2 F - V = g BS m

29 Chapter 3 Section 3 (12/2/6) Page Small-Signal Model Continued Complete schematic D model: where and g m di D dv GS Q = (V GS-V T ) = 2I D g mbs = D v BS Q = i D v GS v GS v BS Q = - i D v T v T v BS Simplified schematic model: An extremely important assumption: g m 1g mbs 1g ds G S B G G D S D S B G G + v gs - S g di D ds dv DS Q = i D 1 + v DS i D D S Q = B + v bs - g m v gs g mbs v bs g m 2 2 F - V BS = g m G + v gs - S g m v gs r ds r ds i d + D v ds - S Fig i d + D v ds - S Fig Chapter 3 Section 3 (12/2/6) Page An Alternate Way of Deriving the Small Signal Model Large-Signal Characteristics: Ignore channel modulationi = i D = K W 2L (v GS - V T )2 = 2 (v GS - V T )2 and v = v GS = v DS = V T + Small-Signal Characteristics: The small signal model is a linearization of the large signal model at an operating point. i D = 2 (v GS-V T )2(1+v DS ) d + I D = 2 [v gs+(v GS -V T )]2[1+(v ds +V DS )] i d +I D = 2 v gs 2 + (V GS -V T )v gs + 2 (V GS-V T )2 + 2 v gs 2 v ds + (V GS -V T )v gs v ds + 2 (V GS-V T )2 vds + 2 v gs 2 V DS + (V GS -V T )v gs V DS + 2 (V GS-V T )2 VDS Assume that v gs < V GS -V T, v ds < V DS and <<1. Therefore we write: i d +I D (V GS -V T )v gs + 2 (V GS-V T )2 vds + 2 (V GS-V T )2(1+V DS ) i d = (V GS -V T )v gs + 2 (V GS-V T )2 vds = g m v gs +g ds v ds and I D = 2 (V GS-V T )2(1+V DS ) 2i D

30 Chapter 3 Section 3 (12/2/6) Page Small-Signal Model for the Nonsaturated Region gm = i D vgs Q = K WV DS L (1+VDS) K W L V DS gmbs = i D vbs Q = K W VDS 2L 2F - VBS gds = i D vds Q = K W L ( V GS - VT - VDS)(1+VDS) + ID 1+VDS K W L (V GS - V T - VDS) Note: While the small-signal model analysis is independent of the region of operation, the evaluation of the small-signal performance is not. Chapter 3 Section 3 (12/2/6) Page Small Signal Model for the Subthreshold Region If v DS >, then i D = K W x L ev GS/nVt (1 + v DS ) Small-signal model: g m = di D dv GS Q = qi D nkt g ds = di D dv DS Q I D VA

31 Chapter 3 Section 3 (12/2/6) Page FREQUENCY DEPENDENT SMALL SIGNAL MODEL Small-Signal Frequency Dependent Model The depletion capacitors are found by evaluating the large signal capacitors at the DC operating point. The charge storage capacitors are constant for a specific region of operation. G C gb + v gs - S C gd C gs g m v gs v bs + + r ds v ds g mbs v bs - - S C bs i d C bd D B Fig12-13 Chapter 3 Section 3 (12/2/6) Page Gain-bandwidth of the MOSFET (f T ) The short-circuit current gain is measure of the frequency capability of the MOSFET. i Small signal model: out i in Small signal analysis gives, i in i out = g m v gs sc gd v gs and v gs = s(c gs + C gd ) Therefore, i out g m -sc gd i in = s(c gs + C gd ) g m s(c gs + C gd ) Assume V SB = and the MOSFET is in saturation, f T = 1 g m 2 C gs + C gd 1 g m 2 C gs Recalling that V DD C gs 2 3 C oxwl and g m = μ o C ox W L (V GS -V T ) f T = 3 4 μ o L 2 (V GS -V T ) i in + v gs C gs g m v gs C gd C bd i out r ds

32 Chapter 3 Section 3 (12/2/6) Page NOISE MODELS MOS Device Noise at Low Frequencies D D e N 2 D G where S B G Noise Free MOSFET S i n 2 B G * Noise Free MOSFET S B i 2 n = 8kTg m (1+) 3 + KF I D f S C ox L 2 f (amperes2 ) f = bandwidth at a frequency, f = g mbs g m k = Boltzmann s constant KF = Flicker noise coefficient S = Slope factor of the 1/f noise Chapter 3 Section 3 (12/2/6) Page Reflecting the MOSFET Noise to the Gate Dividing i 2 n by g 2 m gives e 2 n = i n 2 g 2 m = 8kT(1+) 3g m + KF It will be convenient to use B = 2C ox K Frequency response of MOSFET noise: Noise Spectral Density KF 2fC ox WL K f (volts2 ) for model simplification. 1/f noise Thermal noise f Corner log 1 f

33 Chapter 3 Section 3 (12/2/6) Page MOSFET Noise Model at High Frequencies At high frequencies, the source resistance can no longer be assumed to be small. Therefore, a noise current generator at the input results. MOSFET Noise Models: G C gd D v in C gs v gs g m v gs r ds i n 2 i o 2 v in G S S Circuit 1: Frequency Dependent Noise Model e i 2 C gd D * i C i 2 gs v gs r ds i o 2 g m v gs S S Circuit 2: Input-referenced Noise Model Chapter 3 Section 3 (12/2/6) Page MOSFET Noise Model at High Frequencies Continued To find e 2 i and i i 2, we will perform the following calculations: e i 2: Short-circuit the input and find i 2 o of both models and equate to get e 2 i. Ckt. 1: i 2 o = i 2 n i 2 n Ckt. 2: i 2 o = g 2 m e i 2+ (C gd ) 2 e 2 e 2 i = g 2 m + (C gd ) 2 i i i 2: Open-circuit the input and find i 2 o of both models and equate to get i 2 i. Ckt. 1: i 2 o = i 2 n Ckt. 2: i 2 o = (1/C gs ) g (1/C ds ) + (1/C gs ) 2 m 2i 2 i i 2 i + 2 (C gs +C ds ) 2 g m 2 2 C gs 2 i n 2 if C gd < C gs i 2 i = 2 C 2 gs g 2 m i 2 n

34 Chapter 3 Section 4 (12/2/6) Page Resistor Models SECTION 3.4 PASSIVE COMPONENT MODELS RESISTOR v i + R(v) i v + R(v) C p C p1 Cp2 Distributed Model Lumped Model ) Large signal i i = v R 2.) Small signal v = Ri 3.) Noise Conductivity modulation e n 2 = 4kTR or i n 2 = 4kTG v Chapter 3 Section 4 (12/2/6) Page Capacitor Models i C p CAPACITOR R p C(v) + v Cp One of the parasitic capacitors is the top plate and the other is associated with the bottom plate. 1.) Large signal C Linear ) Small signal q = Cv i = C(dv/dt) Nonlinear v ) Do capacitors have noise? See next page.

35 Chapter 3 Section 4 (12/2/6) Page Switched Capacitor Circuits - kt/c Noise Capacitors and switches generate an inherent thermal noise given by kt/c. This noise is verified as follows. R An equivalent circuit for a switched on capacitor: v in C vout v in C vout The noise voltage spectral density of switched capacitor above is given as e 2 Ron = 4kTR on Volts 2 /Hz = 2kTR on Volt 2 /Rad./sec. The rms noise voltage is found by integrating this spectral density from to to give v 2 Ron = 2kTR on 1 2d = 2kTR on 1 2 = kt C Volts(rms)2 where 1 = 1/(R on C). Note that the switch has an effective noise bandwidth of 1 f sw = 4R on C Hz which is found by dividing the second relationship by the first. Chapter 3 Section 4 (12/2/6) Page INDUCTOR Inductor Models R = losses of the inductor C p = parasitic capacitance to ground R p = losses due to eddy currents caused by magnetic flux 1.) Large Signal L Linear v + L(i) R C p i C p R p Rp ) Small signal d = Li dt = v = L di dt 3.) Mutual inductance di 1 v 1 = L 1 dt + Mdi 2 dt v 2 = M di 1 dt + L di 2 2 dt k = M L 1 L 2 Nonlinear i i 1 M i 2 i 1 L 1 -M L 2 -M i v 1 L 1 L 2 v 2 v 1 M v

36 Chapter 3 Section 4 (12/2/6) Page INTERCONNECTS Types of Wires 1.) Metal Many layers are available in today s technologies: - Lower level metals have more resistance (7 m/sq.) - Upper level metal has the less resistance because it is thicker (5 m/sq.) 2.) Polysilicon Better resistor than conductor (unpolysicided) (135/sq.) Silicided polysilicon has a lower resistance (5/sq.) 3.) Diffusion Reasonable for connections if silicided (5/sq.) Unsilicided (55/sq.) 4.) Vias Vias are vertical metal (tungsten plugs or aluminum) - Connect metal layer to metal layer (3.5/via) - Connect metal to silicon or polysilicon contact resistance (5/contact) Chapter 3 Section 4 (12/2/6) Page Ohmic Contact Resistance The metal to silicon contact generates resistance because of the presence of a potential barrier between the metal and the silicon. Contact and Via Resistance: Contact System Contact Resistance (/μm 2 ) Al-Cu-Si to 16/sq. base 75 Al-Cu-Si to 5/sq. emitter 4 Al-Cu/Ti-W/PtSi to 16/sq. base 125 Al-Cu/Al-Cu (Via) 5 Al-Cu/Ti-W/Al-Cu (Via) 5 Aluminum Vias Tungsten Plugs Metal 3 Metal 2 Metal 1 Transistors

37 Chapter 3 Section 4 (12/2/6) Page Capacitance of Wires Self, fringing and coupling capacitances: Wide Spacing C Coupling Minimum Spacing C Coupling C Fringe Ground plane C Self C Fringe Capacitance Typical Value Units Metal to diffusion, Self capacitance 33 af/μm 2 Metal to diffusion, Fringe capacitance, minimum spacing 7 af/μm Metal to diffusion, Fringe capacitance, wide spacing 4 af/μm Metal to metal, Coupling capacitance, minimum spacing 85 af/μm Metal to substrate, Self capacitance 28 af/μm 2 Metal to substrate, Fringe capacitance, minimum spacing 4 af/μm Metal to substrate, Fringe capacitance, wide spacing 39 af/μm Chapter 3 Section 4 (12/2/6) Page Example of Coupling between the Input and Output of an Amplifier For the NMOS in the layout below, find the location of the RHP zero caused by the capacitive coupling due only to the metal-to-metal coupling capacitance between V out and V in metal lines. Assume the transconductance is 775μS and C gd = 3fF. v out 5V M2 n-substrate p-well v in Poly Each square is 1m x 1m M1 Ground Metal p+ n Assuming minimum spacing and 4μm of coupling gives C coupling = 3.4fF. The RHP zero is given by, RHP zero = g m C coupling + C gd = 775μS 6.4fF = 1.21x111 radians/sec.(19.3 GHz)

38 Chapter 3 Section 4 (12/2/6) Page Electromigration Electromigration occurs if the current density is too large and the pressure of carrier collisions on the metal atoms causes a slow displacement of the metal. Black s law: 1 MTF = AJ 2 e (E a/kt j ) Metal Where A = rate constant (cm 4 /A 2 /hr) J = current density (A/cm 2 ) E a = activation energy in electron volts (.5eV for Al and.7ev for Cu doped Al) k = Boltzmann s constant (8.6x1-5 ev/k) Electromigration leads to a maximum current density, J max. J max for copper doped aluminum is 5x1 5 A/cm 2 at 85 C. If t = 1, Angstroms and J max = 5x1 5 A/cm 2, then a 1μm wide lead can conduct no more than 5mA at 85 C. Chapter 3 Section 4 (12/2/6) Page Where is AC Ground on the Chip? AC grounds on the chip are any area tied to a fixed potential. This includes the substrate and the wells. All parasitic capacitances are in reference to these points. Intermediate Oxide Layers Salicide VDD GRD p+ Tungsten Plugs Tungsten Plugs Shallow Trench Isolation n+ Metal Vias Sidewall Spacers Shallow Trench Isolation Tungsten Plugs Polycide Protective Insulator Layer Metal Via Salicide Salicide Salicide p+ p+ AC Ground n+ n+ DC and AC Ground GRD Tungsten Plug p+ Shallow Trench Isolation Top Metal Second Level Metal First Level Metal DC Ground n-well p-well Substrate Gate Ox Oxide p+ p p- n- n n+ Poly Salicide Polycide Metal 645-5

39 Chapter 3 Section 4 (12/2/6) Page What is a Ground? Ground is simply another power supply whose value is supposed to be zero and is used as a reference for all other voltages. DC ground is a point in the circuit where the DC voltage is supposed to be zero. AC ground is a point in the circuit where the AC voltage is supposed to be zero. t = C 2 AC Ground V in C1 - + V out AC Ground V DD V SS DC and AC Ground Chapter 3 Section 4 (12/2/6) Page Grounds that are Not Grounds Because of the resistance of wires, current flowing through a wire can cause a voltage drop. An example of good and bad practice: Bad: Circuit A Circuit Circuit B C R R R Better: Circuit A Best: Circuit A I A I A +I B I A +I B +I C 3R Circuit Circuit B C R I C 2R I B I A Circuit B Circuit C R I A R I B R I C 535-4

40 Chapter 3 Section 4 (12/2/6) Page Kelvin Connections Avoid unnecessary ohmic drops. A B A B X Y Ohmic Connection Kelvin Connection In the left-hand connection, an IR drop is experienced between X and Y causing the potentials at A and B to be slightly different. For example, let the current be 1μA and the metal be 3m/sq. Suppose that the distance between X and Y is 1 squares. Therefore, the IR drop is 1μA x 3m/sq. x 1sq. =.3mV Chapter 3 Section 4 (12/2/6) Page MODELING OF SUBSTRATE NOISE How Do Carriers Get Injected into the Substrate? 1.) Hot carriers (substrate current) 2.) Electrostatic coupling (across depletion regions and other dielectrics) 3.) Electromagnetic coupling (parallel conductors) Why is this a Problem? With decreasing channel lengths, more circuitry is being integrated on the same substrate. The result is that noisy circuits (circuits with rapid transitions) are beginning to adversely influence sensitive circuits (such as analog circuits). Present Solution Keep circuit separate by using multiple substrates and put the multiple substrates in the same package.

41 Chapter 3 Section 4 (12/2/6) Page Hot Carrier Injection in CMOS Technology without an Epitaxial Region Noisy Circuits V DD V DD (Analog) Quiet Circuits v in v out R L V GS v in v out Substrate Noise v in V DD (Analog) Digital Ground ;;; n+ n+ ;;;;; p+ p + n+ p+ v in v out V DD (Digital) Hot n- well "AC ground" Carrier Put substrate connections as close to the noise source as possible n+ channel stop (1 Ω-cm) "AC ground" p+ channel stop (1Ω-cm) V GS ;;; n+ n+ p + I D i D Δi D Δi D R L v out Analog Ground Back-gating due to a momentary change in reverse bias p- substrate (1 Ω-cm) V GS v GS Heavily Doped p Lightly Doped p Intrinsic Doping Lightly Doped n Heavily Doped n Metal Fig. SI-1 Chapter 3 Section 4 (12/2/6) Page Hot Carrier Injection in CMOS Technology with an Epitaxial Region Noisy Circuits V DD V DD (Analog) Quiet Circuits v in v out R L V GS v in v out Substrate Noise v in V DD (Analog) Digital Ground ;;; n+ n+ ;;;;; ;;;n+ p+ p + p+ Put substrate connections as close to the noise source as possible Hot Carrier v in v out n- well V DD (Digital) "AC ground" p - epitaxial layer (15 Ω-cm) "AC ground" V GS ;;; n+ n+ p + Reduced back gating due to smaller resistance R L v out Analog Ground p+ substrate (.5 Ω-cm) Heavily Doped p Lightly Doped p Intrinsic Doping Lightly Doped n Heavily Doped n Metal Fig. SI-2

42 Chapter 3 Section 4 (12/2/6) Page Computer Model for Substrate Interference Using SPICE Primitives Noise Injection Model: V DD V DD v in v out Digital Ground ;;; n+ n+ ;;;;; p+ p + n+ Hot n- well ;;;;; Carrier Coupling p+ Hot Carrier v in Coupling v out V DD (Digital) Coupling v in C s3 L 1 C s1 n- well C v s2 out Rs1 Substrate R s2 R s3 C s4 C s5 L 2 L 3 p- substrate C s1 = Capacitance between n-well and substrate C s2, C s3 and C s4 = Capacitances between interconnect lines (including bond pads) and substrate C s5 = All capacitance between the substrate and ac ground R s1, R s2 and R s3 = Bulk resistances in n-well and substrate L 1, L 2 and L 3 = Inductance of the bond wires and package leads Heavily Doped p Lightly Doped p Intrinsic Doping Lightly Doped n Heavily Doped n Metal Fig. SI-6 Chapter 3 Section 4 (12/2/6) Page Computer Model for Substrate Interference Using SPICE Primitives Noise Detection Model: V DD (Analog) R L V GS v in v out Substrate Noise V DD (Analog) V DD V GS v in R L v out Analog Ground R L L 4 C L v out ;;; n+ n+ p + V GS Substrate L 6 C s6 R s4 C s7 C s5 L 5 p- substrate C s5, C s6 and C s7 = Capacitances between interconnect lines (including bond pads) and substrate R s4 = Bulk resistance in the substrate L 4, L 5 and L 6 = Inductance of the bond wires and package leads Heavily Doped p Lightly Doped p Intrinsic Doping Lightly Doped n Heavily Doped n Metal Fig. SI-7

43 Chapter 3 Section 4 (12/2/6) Page Other Sources of Substrate Injection (We do it to ourselves and can t blame the digital circuits.) Substrate BJT Inductor Collector Base Emitter Collector n+ p+ n+ n+ p- well Heavily Doped p Lightly Doped p Intrinsic Doping Lightly Doped n Heavily Doped n Metal Fig. SI-4 Also, there is coupling from power supplies and clock lines to other adjacent signal lines. Chapter 3 Section 4 (12/2/6) Page Summary of Substrate Interference Methods to reduce substrate noise 1.) Physical separation 2.) Guard rings placed close to the sensitive circuits with dedicated package pins. 3.) Reduce the inductance in power supply and ground leads (best method) 4.) Connect regions of constant potential (wells and substrate) to metal with as many contacts as possible. Noise Insensitive Circuit Design Techniques 1.) Design for a high power supply rejection ratio (PSRR) 2.) Use multiple devices spatially distinct and average the signal and noise. 3.) Use quiet digital logic (power supply current remains constant) 4.) Use differential signal processing techniques. Some references 1.) D.K. Su, M.J. Loinaz, S. Masui and B.A. Wooley, Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal IC s, J. of Solid-State Circuits, vol. 28, No. 4, April 1993, pp ) K.M. Fukuda, T. Anbo, T. Tsukada, T. Matsuura and M. Hotta, Voltage-Comparator-Based Measurement of Equivalently Sampled Substrate Noise Waveforms in Mixed-Signal ICs, J. of Solid- State Circuits, vol. 31, No. 5, May 1996, pp ) X. Aragones, J. Gonzalez and A. Rubio, Analysis and Solutions for Switching Noise Coupling in Mixed-Signal ICs, Kluwer Acadmic Publishers, Boston, MA, 1999.