CHAPTER 3 - CMOS MODELS

Transcription

1 Lecture 04

2 Chapter 3 Introduction (4/15/02) Page CHAPTER 3 - CMOS MODELS Chapter Outline 3.1 MOS Structure and Operation 3.2 Large signal MOS models suitable for hand calculations 3.3 Extensions of the large signal MOS model 3.4 Capacitances of the MOSFET 3.5 Small Signal MOS models 3.6 Temperature and noise models for MOS transistors 3.7 BJT models 3.8 SPICE level 2 model 3.9 Models for simulation of MOS circuits 3.10Extraction of a large signal model for hand calculations from the BSIM3 model 3.11Summary Perspective CMOS Technology and Fabrication Analog Integrated Circuit Design CMOS Transistor and Passive Component Modeling Fig.3.0-1

3 Chapter 3 Introduction (4/15/02) Page Philosophy for Models Suitable for Analog Design The model required for analog design with CMOS technology is one that leads to understanding and insight as distinguished from accuracy. Technology Understanding and Usage Updating Model Thinking Model Simple, ±10% to ±50% accuracy Updating Technology Comparison of simulation with expectations Design Decisions- "What can I change to accomplish...?" Expectations "Ballpark" Computer Simulation Extraction of Simple Model Parameters from Computer Models Refined and optimized design Fig This chapter is devoted to the simple model suitable for design not using simulation.

4 Chapter 3 Introduction (4/15/02) Page Categorization of Electrical Models Linearity Linear Nonlinear Time Independent Small-signal, midband R in, A v, R out (.TF) DC operating point i D = f(v D,v G,v S,v B ) (.OP) Time Dependence Time Dependent Small-signal frequency response-poles and zeros (.AC) Large-signal transient response - Slew rate (.TRAN) Based on the simulation capabilities of SPICE.

5 Chapter 3 Section 1 (4/15/02) Page MOS STRUCTURE AND OPERATION Metal-Oxide-Semiconductor Structure Bulk/Substrate Source Gate Drain Thin Oxide (10-100nm 100Å-1000Å) Polysilicon p+ n+ n+ p- substrate Heavily Doped p Lightly Doped p Intrinsic Doping Lightly Doped n Heavily Doped n Fig Terminals: Bulk - Used to make an ohmic contact to the substrate Gate - The gate voltage is applied in such a manner as to invert the doping of the material directly beneath the gate to form a channel between the source and drain. Source - Source of the carriers flowing in the channel Drain - Collects the carriers flowing in the channel Metal

6 Chapter 3 Section 1 (4/15/02) Page Formation of the Channel for an Enhancement MOS Transistor Subthreshold (V G <V T ) V B = 0 V S = 0 V G < V T V D = 0 Polysilicon p+ n+ n+ p- substrate Threshold (V G =V T ) V B = 0 Depletion Region V S = 0 V G =V T V D = 0 Polysilicon p+ p- substrate n+ n+ Inverted Region Strong Threshold (V G >V T ) V B = 0 V S = 0 V G >V T V D = 0 Polysilicon p+ p- substrate n+ n+ Inverted Region Fig

7 Chapter 3 Section 1 (4/15/02) Page Transconductance Characteristics of an Enhancement NMOS FET when V DS = 0.1V V GS V T : V B = 0 V S = 0 v G =V T V D = 0.1V Polysilicon i D i D p+ n+ n+ p- substrate V GS =2V T : V B = 0 Depletion Region VS = 0 V G = 2V T V D = 0.1V 0 0 i D V T 2V T 3V T v GS Polysilicon i D p+ n+ n+ p- substrate V GS =3V T : V B = 0 Inverted Region V S = 0 V G = 3V T V D = 0.1V 0 0 i D V T 2V T 3V T v GS Polysilicon p+ n+ n+ p- substrate Inverted Region 0 0 V T 2V T 3V T v GS Fig

8 Chapter 3 Section 1 (4/15/02) Page Output Characteristics of the Enhancement NMOS Transistor for V GS = 2V T V DS =0: V B = 0 V S = 0 v G =2V T V D = 0V i D Polysilicon i D V GS = 2V T p+ n+ n+ p- substrate V DS =0.5V T : V B = 0 V S = 0 V G = 2V T Inverted Region V D = 0.5V T 0 0 i D 0.5V T V T v DS Polysilicon i D V GS = 2V T p+ n+ n+ p- substrate Channel current V DS =V T : V B = 0 V S = 0 V G = 2V T V D =V T i D Polysilicon 0 0 i D 0.5V T v DS V T V GS = 2V T p+ n+ n+ p- substrate A depletion region forms between the drain and channel V T V T v DS Fig

9 Chapter 3 Section 1 (4/15/02) Page Output Characteristics of the Enhanced NMOS when v DS = 2V T V GS =V T : V B = 0 V S = 0 v G =V T V D = 2V T i D Polysilicon i D p+ n+ n+ p- substrate V GS =2V T : V B = 0 V S = 0 V G = 2V T V D = 2V T 0 0 i D V T V GS =V T 2V T 3V T v DS Polysilicon i D V GS =2V T p+ n+ n+ p- substrate V GS =3V T : V B = 0 V S = 0 V G = 3V T Polysilicon V D = 2V T i D 0 0 i D V T 2V T 3V T V GS =3V T v DS p+ p- substrate n+ n+ Further increase in V G will cause the FET to become active 0 0 V T 2V T 3V T v DS Fig

10 Chapter 3 Section 1 (4/15/02) Page Output Characteristics of an Enhancement NMOS Transistor 2000 VGS = id(µa) 1000 VGS = 2.5 SPICE Input File: 500 Output Characteristics for NMOS M MOS1 w=5u l=1.0u VGS M MOS1 w=5u l=1.0u VGS M MOS1 w=5u l=1.0u VGS M MOS1 w=5u l=1.0u VGS vds (Volts) VGS = 2.0 VGS = 1.5 VGS = 1.0 Fig M MOS1 w=5u l=1.0u VGS VDS model mos1 nmos (vto=0.7 kp=110u +gamma=0.4 +lambda=.04 phi=.7).dc vds print dc ID(M1), ID(M2), ID(M3), ID(M4), ID(M5).end

11 Chapter 3 Section 1 (4/15/02) Page Transconductance Characteristics of an Enhancement NMOS Transistor 6000 V DS = 5V id(µa) V DS = 4V V DS = 3V V DS = 2V V DS = 1V SPICE Input File: Transconductance Characteristics for NMOS M MOS1 w=5u l=1.0u VDS M MOS1 w=5u l=1.0u VDS M MOS1 w=5u l=1.0u VDS M MOS1 w=5u l=1.0u VDS v GS (Volts) M MOS1 w=5u l=1.0u VDS VGS model mos1 nmos (vto=0.7 kp=110u +gamma=0.4 lambda=.04 phi=.7).dc vgs print dc ID(M1), ID(M2), ID(M3), ID(M4), ID(M5).probe.end Fig

12 Chapter 3 Section 2 (4/15/02) Page LARGE SIGNAL FET MODEL FOR HAND CALCULATIONS Large Signal Model Derivation Derivation- 1.) Let the charge per unit area in the channel inversion layer be QI(y) = -Cox[vGS-v(y)-VT] (coul./cm2 ) 2.) Define sheet conductivity of the inversion layer per square as cm2 coulombs σ S = µ o Q I (y) v s cm2 = amps volt = 1 Ω/sq. 3.) Ohm's Law for current in a sheet is JS = i D W = -σ dv SE y = -σ S dy dv = -i D σsw dy = 4.) Integrating along the channel for 0 to L gives L v DS v DS iddy = - WµoQI(y)dv = WµoC ox [vgs-v(y)-vt] dv 0 5.) Evaluating the limits gives 0 id = Wµ oc ox L 2 0 (v GS -V T )v(y) - v 2(y) v DS 0 v GS n + v(y) n + dy p Source Drain - y 0 yy+dy L -i D dy µ o Q I (y)w i D dy = -Wµ o Q I (y)dv L i D = Wµ oc ox + - id (v GS -V T )v DS - v DS Fig v DS

13 Chapter 3 Section 2 (4/15/02) Page Saturation Voltage - V DS (sat) Interpretation of the large signal model: i D v DS = v GS -V T Active Region Saturation Region Increasing values of v GS The saturation voltage for MOSFETs is the value of drain-source voltage at the peak of the inverted parabolas. di D dv DS = µ v oc ox W DS L [(v GS -V T ) - v DS ] = 0 v DS (sat) = v GS - V T Useful definitions: µ o C ox W L = K W L = β v DS Fig Cutoff Saturation Active V T v DS = v GS - V T v GS 0 0 Fig

14 Chapter 3 Section 2 (4/15/02) Page The Simple Large Signal MOSFET Model Regions of Operation of the MOS Transistor: 1.) Cutoff Region: vgs - VT < 0 id = 0 (Ignores subthreshold currents) 2.) Active Region 0 < vds < vgs - VT i D /I D0 id = µ ocoxw 2L 2(vGS - VT) - vds vds ) Saturation Region 0 < vgs - VT < vds id = µ o CoxW 2L vgs - VT 2 Output Characteristics of the MOSFET: Active Region v DS = v GS -V T Saturation Region Channel modulation effects Cutoff Region v GS -V T V GS0 -V T = 1.0 v GS -V T V GS0 -V T = v GS -V T = V GS0 -V T v GS -V T = 0.5 V GS0 -V T v GS -V T V GS0 -V T = 0 v DS V GS0 -V T Fig

15 Chapter 3 Section 2 (4/15/02) Page Influence of V DS on the Output Characteristics Channel modulation effect: As the value of v DS increases, the effective L decreases causing the B current to increase. S Polysilicon V G > V T V D > V DS (sat) Depletion Region Illustration: p+ n+ n+ Note that L eff = L - X d Therefore the model in saturation becomes, i D = K W 2L eff (v GS -V T )2 p- substrate di D dv DS = - K W 2L eff 2 (v GS - V T ) 2 dl eff dv DS = i D Leff dx d dv DS λi D Therefore, a good approximation to the influence of v DS on i D is i D i D (λ = 0) + di D dv DS v DS = i D (λ = 0)(1 + λv D ) = K W 2L (v GS-V T ) 2 (1+λv DS ) L eff X d Fig110-06

16 Chapter 3 Section 2 (4/15/02) Page Channel Length Modulation Parameter, λ Assume the MOS is transistor is saturated- i D = µc oxw 2L (v GS - V T ) 2 (1 + λv DS ) Define i D (0) = i D when v DS = 0V. i D (0) = µc oxw 2L (v GS- V T ) 2 Now, i D = i D (0)[1 + λv DS ] = i D (0) + λi D (0) v DS Matching with y = mx + b gives the value of λ i D3 (0) i D2 (0) i D1 (0) i D V GS3 V GS2 V GS1-1 λ v DS

17 Chapter 3 Section 2 (4/15/02) Page Influence of the Bulk Voltage on the Large Signal MOSFET Model Illustration of the influence of the bulk: V BS0 = 0V VSB0 = 0V: V S = 0 V G > V T V D > 0 Polysilicon i D p+ n+ n+ p- substrate Channel current VSB1>0V: V SB1 > 0V V S = 0 V G > V T V D > 0 Polysilicon Fig A i D p+ n+ n+ p- substrate Channel current VSB2 > V SB1 : V SB2 >V SB1 Fig B V S = 0 V G > V T V D > 0 i D = 0 Polysilicon p+ p- substrate n+ n+ Fig C

18 Chapter 3 Section 2 (4/15/02) Page Influence of the Bulk Voltage on the Large Signal MOSFET Model - Continued Bulk-Source (vbs) influence on the transconductance characteristics- i D Decreasing values of bulk-source voltage V BS = 0 I D v DS v GS -V T V T0 V T1 V T2 V T2 v GS Fig In general, the simple model incorporates the bulk effect into VT by the previously developed relationship: VT(vBS) = VT0 + γ 2 φf + vbs - γ 2 φf

19 Chapter 3 Section 2 (4/15/02) Page Summary of the Simple Large Signal MOSFET Model N-channel reference convention: L Non-saturationiD = Wµ ocox L SaturationiD = Wµ ocox (vgs - VT)vDS - v DS 2 2 (1 + λvds) (vgs-vt)vds(sat) - v DS(sat) 2 2 (1+λvDS) = Wµ ocox 2L (vgs-vt) 2 (1+λvDS) where: µo = zero field mobility (cm2/volt sec) Cox = gate oxide capacitance per unit area (F/cm2) λ = channel-length modulation parameter (volts-1) VT = VT0 + γ 2 φf + vbs - 2 φf VT0 = zero bias threshold voltage γ = bulk threshold parameter (volts-0.5) 2 φf = strong inversion surface potential (volts) For p-channel MOSFETs, use n-channel equations with p-channel parameters and invert current. G + i D v GS D S B + v BS v DS Fig

20 Chapter 3 Section 2 (4/15/02) Page Silicon Constants Constant Symbol V G k ni ε0 εsi εox Constant Description Value Units Silicon bandgap (27 C) Boltzmann s constant Intrinsic carrier concentration (27 C) Permittivity of free space Permittivity of silicon Permittivity of SiO x x x ε0 3.9 ε0 V J/K cm-3 F/cm F/cm F/cm

21 Chapter 3 Section 2 (4/15/02) Page MOSFET Parameters Model Parameters for a Typical CMOS Bulk Process (0.8µm CMOS n-well): Parameter Parameter Typical Parameter Value Symbol Description N-Channel P-Channel Units VT0 Threshold Voltage (V BS = 0) 0.7± ± 0.15 V K' Transconductance Parameter (in saturation) ± 10% 50.0 ± 10% µa/v2 γ Bulk threshold parameter (V)1/2 λ Channel length 0.04 (L=1 µm) 0.05 (L=1 µm) modulation parameter 0.01 (L=2 µm) 0.01 (L=2 µm) (V)-1 2 φf Surface potential at strong inversion V

22 Chapter 3 Section 3 (4/15/02) Page LARGE SIGNAL MODEL EXTENSIONS TO SHORT-CHANNEL MOSFETS Extensions Velocity saturation Weak inversion (subthreshold) Substrate currents Substrate Interference Problems of mixed signal circuits on the same substrate Modeling and potential solutions

23 Chapter 3 Section 3 (4/15/02) Page VELOCITY SATURATION What is Velocity Saturation? The most important short-channel effect in MOSFETs is the velocity 105 saturation of carriers in the channel. A plot of electron drift velocity 5x104 versus electric field is shown below. An expression for the electron drift velocity as a function of the electric field is, v d µ n E 1 + E/E c where v d = electron drift velocity (m/s) µ n = low-field mobility ( 0.07m2/V s) 2x104 E c = critical electrical field at which velocity saturation occurs Electron Drift Velocity (m/s) 104 5x Electric Field (V/m) Fig130-1

24 Chapter 3 Section 3 (4/15/02) Page Important Short Channel Effects 1.) An approximate plot of the n as a function of channel length is shown below where i D (v GS V T )n 2.) Note that the value of λ varies with channel length, L. The data below is from a 0.25µm CMOS technology. Channel Length Modulation (V-1) NMOS PMOS Channel Length (microns) Fig n L L min Fig.130-5

25 Chapter 3 Section 3 (4/15/02) Page SUBTHRESHOLD MOSFET MODEL What is Weak Inversion Operation? Weak inversion operation occurs when the applied gate voltage is below V T and pertains to when the surface of the substrate beneath the gate is weakly inverted. V GS n+ n-channel n+ Diffusion Current p-substrate/well Fig Regions of operation according to the surface potential, φ S (or ψ S ) φ S < φ F : Substrate not inverted φ F < φ S < 2φ F : Channel is weakly inverted (diffusion current) 2φ F < φ S : Strong inversion (drift current)

26 Chapter 3 Section 3 (4/15/02) Page Drift versus Diffusion Current 1.) For strong inversion, the gate voltage controls the charge in the inverted region but not in the depletion region. The concentration of charge across the channel is approximately constant and the current is drift caused by electric field. 2.) For weak inversion, the charge in channel is much less that that in the depletion region and drift current decreases. However, there is a concentration gradient in the channel, that causes diffusion current. The n-channel MOSFET acts like a NPN BJT: the emitter is the source, the base is the substrate and the collector is the drain. Illustration: 10-6 log i D Diffusion Current Drift Current V T V GS Fig

27 Chapter 3 Section 3 (4/15/02) Page Simulation of an n-channel MOSFET in both Weak and Strong Inversion Uses the BSIM model. 100µA ID(M1) 10µA 1µA 100nA i D v GS 10nA 1nA 100pA 0V 0.4V 0.8V 1.2V VGS 1.6V 2V Fig Y. Cheng and C. Hu, MOSFET Modeling & BSIM3 User s Guide, Kluwer Academic Publishers, Boston, 1999.

28 Chapter 3 Section 3 (4/15/02) Page SUBSTRATE CURRENT FLOW IN MOSFETS Impact Ionization Impact Ionization: Occurs because high electric fields cause an impact which generates a hole-electron pair. The electrons flow out the drain and the holes flow into the substrate causing a substrate current flow. Illustration: B p+ p- substrate S n+ V G > V T Polysilicon Fixed Atom V D > V DS (sat) A Free n+ electron Free hole Fig130-7 Depletion Region

29 Chapter 3 Section 3 (4/15/02) Page SUBSTRATE INTERFERENCE IN CMOS CIRCUITS How Do Carriers Get Injected into the Substrate? 1.) Hot carriers (substrate current) 2.) Electrostatic coupling (across depletion regions and other dielectrics) 3.) Electromagnetic coupling (parallel conductors) Why is this a Problem? With decreasing channel lengths, more circuitry is being integrated on the same substrate. The result is that noisy circuits (circuits with rapid transitions) are beginning to adversely influence sensitive circuits (such as analog circuits). Present Solution Keep circuit separate by using multiple substrates and put the multiple substrates in the same package.

30 Chapter 3 Section 3 (4/15/02) Page Hot Carrier Injection in CMOS Technology without an Epitaxial Region Noisy Circuits V DD V DD (Analog) Quiet Circuits v in v out R L V GS v in v out Substrate Noise v in V DD (Analog) Digital Ground v in v out V DD (Digital) n+ channel stop (1 Ω-cm) V GS R L v out Analog Ground p+ n+ n+ n- well Hot Carrier Put substrate connections as close to the noise source as possible p+ p+ n+ "AC ground" "AC ground" p+ channel stop (1Ω-cm) I D n+ n+ i D i D i D p+ Back-gating due to a momentary change in reverse bias p- substrate (10 Ω-cm) V GS v GS Heavily Doped p Lightly Doped p Intrinsic Doping Lightly Doped n Heavily Doped n Metal Fig. SI-01

31 Chapter 3 Section 3 (4/15/02) Page Hot Carrier Injection in CMOS Technology with an Epitaxial Region Noisy Circuits V DD V DD (Analog) Quiet Circuits v in v out R L V GS v in v out Substrate Noise v in V DD (Analog) Digital Ground v in v out V DD (Digital) V GS R L v out Analog Ground p+ n+ n+ p+ p+ n+ n+ n+ p+ Put substrate connections as close to the noise source as possible Hot Carrier n- well "AC ground" p - epitaxial layer (15 Ω-cm) "AC ground" Reduced back gating due to smaller resistance p+ substrate (0.05 Ω-cm) Heavily Doped p Lightly Doped p Intrinsic Doping Lightly Doped n Heavily Doped n Metal Fig. SI-02

32 Chapter 3 Section 3 (4/15/02) Page Computer Model for Substrate Interference Using SPICE Primitives Noise Injection Model: V DD V DD v in v out L 1 n- well C s1 Digital Ground v in v out V DD (Digital) v in C s3 v out Rs1 C s2 Substrate p+ n+ n+ Hot Carrier Coupling p+ p+ n+ Hot Carrier n- well Coupling Coupling R s2 R s3 C s4 C s5 L 2 L 3 p- substrate C s1 = Capacitance between n-well and substrate C s2, C s3 and C s4 = Capacitances between interconnect lines (including bond pads) and substrate C s5 = All capacitance between the substrate and ac ground R s1, R s2 and R s3 = Bulk resistances in n-well and substrate L 1, L 2 and L 3 = Inductance of the bond wires and package leads Heavily Doped p Lightly Doped p Intrinsic Doping Lightly Doped n Heavily Doped n Metal Fig. SI-06

33 Chapter 3 Section 3 (4/15/02) Page Computer Model for Substrate Interference Using SPICE Primitives Noise Detection Model: V DD (Analog) R L V GS v in v out Substrate Noise V DD (Analog) V DD V GS v in R L v out Analog Ground R L L 4 C L v out n+ n+ p+ L 6 V GS Substrate C s6 R s4 C s7 C s5 L 5 p- substrate C s5, C s6 and C s7 = Capacitances between interconnect lines (including bond pads) and substrate R s4 = Bulk resistance in the substrate L 4, L 5 and L 6 = Inductance of the bond wires and package leads Heavily Doped p Lightly Doped p Intrinsic Doping Lightly Doped n Heavily Doped n Metal Fig. SI-07

34 Chapter 3 Section 3 (4/15/02) Page Other Sources of Substrate Injection (We do it to ourselves and can t blame the digital circuits.) Substrate BJT Inductor Collector Base Emitter Collector n+ p+ n+ n+ p- well Heavily Doped p Lightly Doped p Intrinsic Doping Lightly Doped n Heavily Doped n Metal Fig. SI-04 Also, there is coupling from power supplies and clock lines to other adjacent signal lines.

35 Chapter 3 Section 3 (4/15/02) Page What is a Good Ground? On-chip, it is a region with very low bulk resistance. It is best accomplished by connecting metal to the region at as many points as possible. Off-chip, it is all determined by the connections or bond wires. The inductance of the bond wires is large enough to create significant ground potential changes for fast current transients. v = L di dt Use multiple bonding wires to reduce the ground noise caused by inductance Settling Time to within 0.5mV (ns) Peak-to-Peak Noise (mv) Number of Substrate Contact Package Pins Fig. SI-08 Fast changing signals have part of their path (circuit through ground and power supplies. Therefore bypass the off-chip power supplies to ground as close to the chip as possible. V in t = 0 C1 "! C 2 V out V DD V SS Fig. SI-05

36 Chapter 3 Section 3 (4/15/02) Page Summary of Substrate Interference Methods to reduce substrate noise 1.) Physical separation 2.) Guard rings placed close to the sensitive circuits with dedicated package pins. 3.) Reduce the inductance in power supply and ground leads (best method) 4.) Connect regions of constant potential (wells and substrate) to metal with as many contacts as possible. Noise Insensitive Circuit Design Techniques 1.) Design for a high power supply rejection ratio (PSRR) 2.) Use multiple devices spatially distinct and average the signal and noise. 3.) Use quiet digital logic (power supply current remains constant) 4.) Use differential signal processing techniques. Some references 1.) D.K. Su, M.J. Loinaz, S. Masui and B.A. Wooley, Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal IC s, J. of Solid-State Circuits, vol. 28, No. 4, April 1993, pp ) K.M. Fukuda, T. Anbo, T. Tsukada, T. Matsuura and M. Hotta, Voltage-Comparator-Based Measurement of Equivalently Sampled Substrate Noise Waveforms in Mixed-Signal ICs, J. of Solid-State Circuits, vol. 31, No. 5, May 1996, pp ) X. Aragones, J. Gonzalez and A. Rubio, Analysis and Solutions for Switching Noise Coupling in Mixed- Signal ICs, Kluwer Acadmic Publishers, Boston, MA, 1999.

37 Chapter 3 Section 4 (4/15/02) Page CAPACITANCES OF THE MOSFET Types of Capacitance Physical Picture: SiO 2 Source Gate Drain FOX C 1 C 2 C3 C 4 C BS C BD Bulk FOX Fig MOSFET capacitors consist of: Depletion capacitances Charge storage or parallel plate capacitances

38 Chapter 3 Section 4 (4/15/02) Page Charge Storage (Parallel Plate) MOSFET Capacitances - C 1, C 2, C3 and C 4 LD Mask L Actual L (L eff ) Oxide encroachment Mask W Actual W (W eff ) Overlap capacitances: C1 = C3 = LD W eff Cox = CGSO or CGDO (LD µm for LDD structures) Source-gate overlap capacitance C GS (C 1 ) FOX Source Gate-Channel Capacitance (C 2 ) Gate Gate Bulk Drain-gate overlap capacitance C GD (C 3 ) FOX Drain Channel-Bulk Capacitance (C 4 ) Fig Channel capacitances: C2 = gate-to-channel = C ox W eff (L-2LD) = CoxW eff L eff C 4 = voltage dependent channelbulk/substrate capacitance

39 Chapter 3 Section 4 (4/15/02) Page Charge Storage (Parallel Plate) MOSFET Capacitances - C 5 View looking down the channel from source to drain Overlap Overlap Gate FOXC 5 Source/Drain C 5 FOX Bulk Fig C 5 = CGBO Capacitance values based on an oxide thickness of 140 Å or C ox = F/m 2 : Type P-Channel N-Channel Units CGSO F/m CGDO F/m CGBO F/m CJ F/m 2 CJSW F/m MJ MJSW

40 Chapter 3 Section 4 (4/15/02) Page Illustration of C GD, C GS and C GB Comments on the variation of C BG in the cutoff region: 1 CBG = 1 C C5 Capacitance C 4 1.) For vgs 0, CGB C2 + 2C5 C 2 + 2C 5 (C4 is large because of the thin inversion layer in weak inversion where V GS is slightly less than V T )) 2.) For 0 < v GS V T, C GB 2C 5 (C 4 is small because of the thicker inversion layer in strong inversion) C 4 Large C GS C C 2 C C GS, C GD C 2 v DS = constant C C GS, C GD C v 1, C GD BS = 0 3 2C C C GB 4 Small 5 0 v GS Off Saturation Non- Saturation V T v DS +V T Fig120-12

41 Chapter 3 Section 6 (4/15/02) Page TEMPERATURE AND NOISE MODELS FOR THE MOSFET Large Signal Temperature Model Transconductance parameter: K (T) = K (T 0 ) (T/T 0 ) -1.5 (Exponent becomes +1.5 below 77 K) Threshold Voltage: V T (T) = V T (T 0 ) + α(t-t 0 ) + Typically α NMOS = -2mV/ C to 3mV/ C from 200 K to 400 K (PMOS has a + sign) Example Find the value of I D for a NMOS transistor at 27 C and 100 C if V GS = 2V and W/L = 5µm/1µm if K (T 0 ) = 110µA/V 2 and V T (T 0 ) = 0.7V and T 0 = 27 C and α NMOS = -2mV/ C. Solution At room temperature, the value of drain current is, I D (27 C) = 110µA/V2 5µm 2 1µm (2-0.7) 2 = 465µA At T = 100 C (373 K), K (100 C)=K (27 C) (373/300) -1.5 =110µA/V =79.3µA/V2 and V T (100 C) = 0.7 (.002)(73 C) = 0.554V I D (100 C) = 79.3µA/V2 5µm 2 1µm ( ) 2 = 415µA (Repeat with V GS = 1.5V)

42 Chapter 3 Section 6 (4/15/02) Page Experimental Verification of the MOSFET Temperature Dependence NMOS Threshold: V T (V) Theory matched at 25 C Temperature ( C) Fig Symbol Min. L NA (cm-3) tox (A ) α (mv/ C) O 6µm 2x µm 1x µm 2x µm 3.3x

43 Chapter 3 Section 6 (4/15/02) Page Experimental Verification of the MOSFET Temperature Dependence PMOS Threshold: V T (V) Theory matched at 25 C Temperature ( C) Fig Symbol Min. L NA (cm-3) Tox (A ) α (mv/ C) O 6µm 2x µm 2x µm 2x µm 1.1x

44 Chapter 3 Section 6 (4/15/02) Page Zero Temperature Coefficient (ZTC) Point for MOSFETs For a given value of gate-source voltage, the drain current of the MOSFET will be independent of temperature. Consider the following circuit: Assume that the transistor is saturated and that: I D T µ = µ o -1.5 T o and V T (T) = V T (T o ) + α(t-t o ) where α = V/ C and T o = 27 C I D (T) = µ oc ox W T L T [VGS o V T0 - α(t-t o )]2 di D dt = -1.5µ oc ox T -2.5 T 2T o T [VGS o -V T0 -α(t-t o )]2+αµ o C ox -1.5 T [VGS o -V T0 -α(t-t o )] = 0 V GS V T0 - α(t-t o ) = -4Tα 3 V GS (ZTC) = V T0 - αt o - ατ 3 Let K = 10µA/V2, W/L = 5 and V T0 = 0.71V. At T=27 C (300 K), V GS (ZTC)=0.71-( )(300 K)-(0.333)( )(300 K) = 1.63V At T = 27 C (300 K), I D = (10µA/V2)(5/2)( )2 = 21.2µA At T=200 C (473 K), V GS (ZTC)=0.71-( )(300 K)-(0.333)( )(473 K)=1.76V V GS Fig

45 Chapter 3 Section 6 (4/15/02) Page Experimental Verification of the ZTC Point The data below is for a 5µm n-channel MOSFET with W/L=50µm/10µm, N A =1016 cm-3, t ox = 650Å, u o C ox = 10µA/V2, and V T0 = 0.71V V DS = 6V 25 C 100 C 150 C 200 C 250 C 275 C ID (µa) C 300 C 250 C 150 C 200 C 25 C 100 C Zero TC Point V GS (V) Fig

46 Chapter 3 Section 6 (4/15/02) Page ZTC Point for PMOS The data is for a 5µm p-channel MOSFET with W/L=50µm/10µm, N D =2x10-15cm-3, and t ox = 650Å. 300 C 25 C 100 C 40 V DS = -6V ID (µa) C 250 C 150 C 100 C 25 C V SG (ZTC) -1.95V V GS (V) 150 C Fig Zero temperature coefficient will occur for every MOSFET up to about 200 C.

47 Chapter 3 Section 6 (4/15/02) Page MOSFET NOISE MOS Device Noise at Low Frequencies D D e N 2 D G B G i n 2 G * B where i 2 n = S Noise Free MOSFET 8kTg m (1+η) 3 + KF I D f S C ox L 2 f (amperes 2 ) S B Noise Free MOSFET S f = bandwidth at a frequency, f η = g mbs g m k = Boltzmann s constant KF = Flicker noise coefficient S = Slope factor of the 1/f noise

48 Chapter 3 Section 6 (4/15/02) Page Reflecting the MOSFET Noise to the Gate Dividing i n 2 by g m 2 gives e 2 n = i n 2 g 2 = m 8kT(1+η) 3g m + It will be convenient to use B = i n 2 KF 2fC ox WL K f (volts2 ) KF 2C ox K for model simplification. 1/f noise Thermal noise log 10 (f)

49 Chapter 3 Section 9 (4/15/02) Page SEC. 3.9 MODELS FOR SIMULATION OF MOS CIRCUITS FET Model Generations First Generation Physically based analytical model including all geometry dependence. Second Generation Model equations became subject to mathematical conditioning for circuit simulation. Use of empirical relationships and parameter extraction. Third Generation A return to simpler model structure with reduced number of parameters which are physically based rather than empirical. Uses better methods of mathematical conditioning for simulation including more specialized smoothing functions. Performance Comparison of Models (from Cheng and Hu, MOSFET Modeling & BSIM3 Users Guide) Model Minimum L (µm) Minimum Tox (nm) Model Continuity i D Accuracy in Strong Inversion i D Accuracy in Subthreshold Small signal parameter Scalability MOS Poor Poor Not Modeled Poor Poor MOS Poor Poor Poor Poor Fair MOS Poor Fair Poor Poor Poor BSIM Fair Good Fair Poor Fair BSIM Fair Good Good Fair Fair BSIM3v Fair Good Good Good Good BSIM3v Good Good Good Good Good

50 Chapter 3 Section 9 (4/15/02) Page First Generation Models Level 1 (MOS1) Basic square law model based on the gradual channel approximation and the square law for saturated drain current. Good for hand analysis. Needs improvement for deep-submicron technology (must incorporate the square law to linear shift) Level 2 (MOS2) First attempt to include small geometry effects Inclusion of the channel-bulk depletion charge results in the familiar 3/2 power terms Introduced a simple subthreshold model which was not continuous with the strong inversion model. Model became quite complicated and probably is best known as a developing ground for better modeling techniques. Level 3 (MOS3) Used to overcome the limitations of Level 2. Made use of a semi-empirical approach. Added DIBL and the reduction of mobility by the lateral field. Similar to Level 2 but considerably more efficient. Used binning but was poorly implemented.

51 Chapter 3 Section 9 (4/15/02) Page Second Generation Models BSIM (Berkeley Short-Channel IGFET Model) Emphasis is on mathematical conditioning for circuit simulation Short channel models are mostly empirical and shifts the modeling to the parameter extraction capability Introduced a more detailed subthreshold current model with good continuity Poor modeling of channel conductance HSPICE Level 28 Based on BSIM but has been extensively modified. More suitable for analog circuit design Uses model binning Model parameter set is almost entirely empirical User is locked into HSPICE Model is proprietary BSIM2 Closely based on BSIM Employs several expressions developed from two dimensional analysis Makes extensive modifications to the BSIM model for mobility and the drain current Uses a new subthreshold model Output conductance model makes the model very suitable for analog circuit design The drain current model is more accurate and provides better convergence Becomes more complex with a large number of parameters No provisions for variations in the operating temperature

52 Chapter 3 Section 9 (4/15/02) Page Third Generation Models BSIM3 This model has achieved stability and is being widely used in industry for deep submicron technology. Initial focus of simplicity was not realized. MOS Model 9 Developed at Philips Laboratory Has extensive heritage of industrial use Model equations are clean and simple should be efficient Other Candidates EKV (Enz-Krummenacher-Vittoz) fresh approach well suited to the needs of analog circuit design

53 Chapter 3 Section 9 (4/15/02) Page BSIM2 Model used in Subthreshold BSIM Model Parameters used in Subthreshold VDS 1 0 DC 3.0 M CMOSN W=5UM L=2UM.MODEL CMOSN NMOS LEVEL=4 +VFB= E-01 LVFB= E-02 WVFB= E-01 +PHI= E-01 +K1= E+00 LPHI= E+00 LK1= E-02 WPHI= E+00 WK1= E-01 +K2= E-03 LK2= E-02 WK2= E-02 +ETA= E-03 +MUZ= E+02 LETA= E-03 DL= E-001 WETA= E-03 DW= E-001 +U0= E-02 LU0= E-02 WU0= E-02 +U1= E-03 LU1= E-01 WU1= E-02 +X2MZ= E+01 LX2MZ= E+01 WX2MZ= E+01 +X2E= E-04 +X3E= E-04 LX2E= E-03 LX3E= E-04 WX2E= E-03 WX3E= E-03 +X2U0= E-03 LX2U0= E-02 WX2U0= E-02 +X2U1= E-04 +MUS= E+02 LX2U1= E-03 LMUS= E+02 WX2U1= E-02 WMUS= E+02 +X2MS= E+00 +X3MS= E+00 LX2MS= E+01 LX3MS= E+01 WX2MS= E+01 WX3MS= E-01 +X3U1= E-03 LX3U1= E-02 WX3U1= E-03 +TOX= E-002 TEMP= E+01 VDD= E+00 +CGDO= E-010 CGSO= E-010 CGBO= E-010 +XPART= E+000 +N0= E+000 LN0= E+000 WN0= E+000 +NB= E+000 LNB= E+000 WNB= E+000 +ND= E+000 LND= E+000 +RSH=0 CJ= e-04 CJSW= e-10 WND= E+000 JS=0 PB=0.8 +PBSW=0.8 MJ= MJSW= WDF=0 DELL=0.DC VDS PRINT DC ID(M1).PROBE.END

54 Chapter 3 Section 9 (4/15/02) Page BSIM3 Model The background for the BSIM3 model and the equations are given in detail in the text MOSFET Modeling & BSIM3 User s Guide, by Y. Cheng and C. Hu, Kluwer Academic Publishers, The short channel effects included in the BSIM3 model are: Normal and reverse short-channel and narrow-width effects on the threshold. Channel length modulation (CLM). Drain induced barrier lowering (DIBL). Velocity saturation. Mobility degradation due to the vertical electric field. Impact ionization. Band-to-band tunnelling. Velocity overshoot. Self-heating. 1.) Channel quantiztion. 2.) Polysilicon depletion.

55 Chapter 3 Section 9 (4/15/02) Page µm BSIM3v3.1 NMOS Parameters.MODEL CMOSN NMOS ( LEVEL = 49 +VERSION = 3.1 +XJ = 1E-7 TNOM = 27 NCH = E17 TOX VTH0 = 5.7E-9 = K1 +K3B = = K2 W0 = K3 = 1E-3 = E-7 NLX = E-7 +DVT0W = 0 DVT1W = 0 DVT2W = 0 +DVT0 = E-3 DVT1 = E-3 DVT2 = U0 = UA = E-12 UB = E-18 +UC +AGS = E-11 VSAT = E5 A0 = = B0 = E-8 B1 = -1E-7 +KETA +RDSW = E-3 = A1 = E-4 PRWG = A2 = PRWB = WR = 1 WINT = E-9 LINT = E-9 +XL = 3E-8 XW = 0 +DWB = E-8 VOFF DWG = = E-10 NFACTOR = CIT = 0 +CDSCB = 0 CDSC = 2.4E-4 CDSCD = 0 ETA0 = E-3 ETAB = E-4 +DSUB = PCLM = PDIBLC1 = PDIBLC2 = E-3 PDIBLCB = DROUT = PSCBE1 = E8 PSCBE2 = 5E-10 PVAG = DELTA = 0.01 MOBMOD = 1 PRT = 0 +UTE +KT2 = -1.5 = KT1 UA1 = = 4.31E-9 KT1L UB1 = 0 = -7.61E-18 +UC1 = -5.6E-11 AT = 3.3E4 WL = 0 +WLN +WWL = 1 = 0 WW LL = E-16 WWN = 0 LLN = 1 = LW = 0 LWN = 1 LWL = 0 +CAPMOD = 2 XPART = 0.4 CGDO = 6.33E-10 +CGSO = 6.33E-10 CGBO = 1E-11 CJ = E-3 +PB = MJ = CJSW = E-10 +PBSW = 0.99 MJSW = CF = 0 +PVTH0 = E-3 PRDSW = PK2 +WKETA = E-3 LKETA = E-3 ) = E-4

56 Chapter 3 Section 9 (4/15/02) Page Adjustable Precision Analog Models Table Lookup y High Level Simulators x 1 x 2 Circuit Level Simulators x 3 Process Simulators "Extraction" Methodology I-V characterisitcs Capacitances Transconductances Measurement Methods Objective Develop models having adjustable precision in ac and dc perfomrance using table lookup models. Advantages Usable at any level device, circuit, or behavioral Quickly developed from experiment or process simulators Faster than analytical device models (BSIM) Disadvantages Requires approximately 10kbytes for a typical MOS model Can t be parameterized easily

57 Chapter 3 Section 9 (4/15/02) Page Summary of MOSFET Models for Simulation Models are much improved for efficient computer simulation Output conductance model is greatly improved Poor results for narrow channel transistors Can have discontinuities at bin boundaries Fairly complex model, difficult to understand in detail

58 Chapter 3 Section 10 (4/15/02) Page SEC EXTRACTION OF A LARGE SIGNAL MODEL FOR HAND CALCULATIONS Objective Extract a simple model that is useful for design from the computer models such as BSIM3. Extraction for Short Channel Models Procedure for extracting short channel models: 1.) Extract the square-law model parameters for a transistor with length at least 10 times L min. 2.) Using the values of K, V T, λ, and γ extract the model parameters for the following model: i D = K 2[1 + θ(v GS -V T )] W L [ v GS V T ] 2 (1+λv DS ) Adjust the values of K, V T, and λ as needed.

59 Chapter 3 Section 10 (4/15/02) Page EXTRACTION OF THE SIMPLE, SQUARE-LAW MODEL Characterization of the Simple Square-Law Model Equations for the MOSFET in strong inversion: where W eff i D = K (v 2L GS - V T ) 2(1 + λv DS ) (1) eff i D = K W eff (v GS - V T )v DS - v2 DS 2 (1 + λv DS) (2) L eff V T = V T0 + γ [ 2 φ F + v SB 2 φ F ] (3)

60 Chapter 3 Section 10 (4/15/02) Page Extraction of Model Parameters: First assume that v DS is chosen such that the λv DS term in Eq. (2) is much less than one and v SB is zero, so that V T = V T0. Therefore, Eq. (2) simplifies to W eff i D = K 2L eff (v GS - V T0 ) 2 (6) This equation can be manipulated algebraically to obtain the following i 1/2 K' W eff 1/2 K' W eff 1/2 D = vgs = 2L VT0 eff (7) 2L eff which has the form y = mx + b (8) This equation is easily recognized as the equation for a straight line with m as the slope and b as the y-intercept. Comparing Eq. (7) to Eq. (8) gives y = i 1/2 D (9) x = v GS (10) K' W eff m = (11) and 2L eff 1/2 K' W eff 1/2 b = - 2L VT0 eff (12)

61 Chapter 3 Section 10 (4/15/02) Page Illustration of K and V T Extraction ( i D ) 1/2 Mobility degradation region v DS >V DSAT Weak inversion region m= K W eff 2L eff 1/2 v GS 0 0 b =V T0 AppB-01 Comments: Stay away from the extreme regions of mobility degradation and weak inversion Use channel lengths greater than L min

62 Chapter 3 Section 10 (4/15/02) Page Example Extraction of K and V T Using Linear Regression Given the following transistor data shown in Table and linear regression formulas based on the form, y = mx + b (13) and m = x i yi - ( xi yi)/n x 2 i - ( x i )2/n determine V T0 and K W/2L. The data in Table B-1 also give I 1/2 D as a function of V GS. Table Data for Example V GS (V) I D (µa) I D (µa)1/2 V SB (V) (14)

63 Chapter 3 Section 10 (4/15/02) Page Example Continued Solution The data must be checked for linearity before linear regression is applied. Checking slopes between data points is a simple numerical technique for determining linearity. Using the formula that Gives Slope = m = y x = I D2 - I D1 V GS2 - V GS1 m 1 = m 3 = = m 2 = = m 4 = = = These results indicate that the first (lowest value of V GS ) data point is either bad, or at a point where the transistor is in weak inversion. This data point will not be included in subsequent analysis. Performing the linear regression yields the following results. K'W eff V T0 = V and 2L eff = µa/v 2

64 Chapter 3 Section 10 (4/15/02) Page Extraction of the Bulk-Threshold Parameter γ Using the same techniques as before, the following equation V T = V T0 + γ [ 2 φ F + v SB 2 φ F ] is written in the linear form where y = V T x = 2 φ F + v SB 2 φ F (19) m = γ (20) b = V T0 (21) The term 2 φ F is unknown but is normally in the range of 0.6 to 0.7 volts. Procedure: 1.) Pick a value for 2 φ F. 2.) Extract a value for γ. (18) 3.) Calculate N SUB using the relationship, γ = 2ε si q N SUB C ox N SUB 4.) Calculate φ F using the relationship, φ F = kt q ln n i 5.) Iterative procedures can be used to achieve the desired accuracy of γ and 2 φ F. Generally, an approximate value for 2 φ F gives adequate results.

65 Chapter 3 Section 10 (4/15/02) Page Illustration of the Procedure for Extracting γ A plot of i D versus v GS for different values of v SB used to determine γ is shown below. ( i D ) 1/2 v GS V T0 V T1 V T2 V T3 FigAppB-02 By plotting V T versus x of Eq. (19) one can measure the slope of the best fit line from which the parameter γ can be extracted. In order to do this, V T must be determined at various values of v SB using the technique previously described.

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68 Chapter 3 Section 10 (4/15/02) Page Illustration of the Procedure for Extracting γ - Continued Each V T determined above must be plotted against the v SB term. The result is shown below. The slope m, measured from the best fit line, is the parameter γ. V SB =2V V SB =3V V T V SB =1V m= γ V SB =0V ( v SB +2 φ F ) 0.5 ( 2 φ F ) 0.5 FigAppB-03

69 Chapter 3 Section 10 (4/15/02) Page Example Extraction of the Bulk Threshold Parameter Using the results from Ex. B-1 and the following transistor data, determine the value of γ using linear regression techniques. Assume that 2 φ F is 0.6 volts. Table Data for Example V SB (V) V GS (V) I D (µa) Solution Table B-2 shows data for V SB = 1 volt and V SB = 2 volts. A quick check of the data in this table reveals that I D versus V GS is linear and thus may be used in the linear regression analysis. Using the same procedure as in Ex. B-1, the following thresholds are determined: V T0 = volts (from Ex. B-1), V T = volts (@V SB = 1 V), and V T = V (@V SB = 2 V). Table B-3 gives the value of V T as a function of [(2 φ F + V SB )1/2 (2 φ F )1/2 ] for the three values of V SB.

70 Chapter 3 Section 10 (4/15/02) Page Example Continued Table Data for Example VSB (V) VT (V) [ 2 φf + VSB - 2 φf ] (V1/2) With these data, linear regression must be performed on the data of V T versus [(2 φ F + V SB ) 0.5 (2 φ F ) 0.5 ]. The regression parameters of Eq. (13) are Σx i y i = Σx i y i = Σx 2 i = (Σx i )2 = These values give m = = γ.

71 Chapter 3 Section 10 (4/15/02) Page Extraction of the Channel Length Modulation Parameter, λ The channel length modulation parameter λ should be determined for all device lengths that might be used. For the sake of simplicity, Eq. (2) is rewritten as i D = i D =λ v DS + i D (22) which is in the familiar linear form where y = i D (Eq. (2)) 23) x = v DS (24) m = λi' D b = i' D (Eq. (2) with λ = 0) (26) (25) By plotting i D versus v DS, measuring the slope of the data in the saturation region, and dividing that value by the y-intercept, λ can be determined. The procedure is illustrated in the figure shown. i' D i D Nonsaturation region Saturation region m= λi' D AppB-03 v DS

72 Chapter 3 Section 10 (4/15/02) Page Example Extraction of the Channel Length Modulation Parameter Given the data of I D versus V DS in Table , determine the parameter λ. Table Data for Example I D (µa) V DS (V) Solution We note that the data of Table covers both the saturation and nonsaturation regions of operation. A quick check shows that saturation is reached near V DS = 2.0 V. To calculate λ, we shall use the data for V DS greater than or equal to 2.5 V. The parameters of the linear regression are x i y i = x i y i = x2 i = 43.5 ( x i )2 = 169 These values result in m = λi' D = 3.08 and b = I' D = 88, giving λ = V -1. The slope in the saturation region is typically very small, making it necessary to be careful that two data points taken with low resolution are not subtracted (to obtain the slope) resulting in a number that is of the same order of magnitude as the resolution of the data point measured. If this occurs, then the value obtained will have significant and unacceptable error.

73 Chapter 3 Section 11 (4/15/02) Page SEC SUMMARY Model philosophy for analog IC design Use simple models for design and sophisticated models for verification Models have several parts Large signal static (dc variables) Small signal static (midband gains, resistances) Small signal dynamic (frequency response, noise) Large signal dynamic (slew rate) In addition models may include: Temperature Noise Process variations (Monte Carlo methods) Computer models Must be numerically efficient Quickly derived from new technology Analog Design Tricks Stay away from minimum channel length if possible - Larger r ds larger gains - Better agreement Don t use the computer models for design, rather verification of design