Advantages and Challenges of Advanced MOSFETs for Analog and RF applications

Transcription

1 Advantages and Challenges of Advanced MOSFETs for Analog and RF applications Valeriya Kilchytska, Sergej Makovejev, Jean-Pierre Raskin, Denis Flandre ICTEAM Institute, Université catholique de Louvain Louvain-la-Neuve, Belgium

2 Outline Introduction Analog/RF Figures of Merit Methodology used for device assessment Advantages and challenges Common Features: Si film thinning and high-µ channels UTBB specificities: Back gate biasing Analog FoM variation in a f-range Importance of parasitics Conclusions 2

3 Introduction Device downscaling is accompanied by introduction of new materials and new architectures, affecting Analog/RF FoM Two main contenders: UTBB FDSOI and MuGFET Both technologies are promising for Analog/RF We do not target to answer Which technology is better for Analog/RF? But highlight common features and specificities of both architectures Source: 211 ITRS Executive Summary Fig 5 3

4 Analog/RF Figures of Merit Key-factors: MOSFET-level f T = g m /(2 p C gg ) f max A v = g m /g d = (g m /I d ) V EA const ( f ) depends on Transconductance g m Drive current, I d Output conductance, g d Early voltage, V EA (V EA =I d /g d ) g m /I d ratio IC (amplifier)-level GBW = g m /(2 p C L ) = = (g m /I d ) (I d /(2 p C L )) V in V DD I bias C L f f T max gm 2p C gs gm 4p C gs C 1 C gd gs C 1 C gd gs Gate capacitance, C gg Parasitics (C, R) 1 gd R s Rd gm gd gd Cgs g d C 1 C gd gd R g R 1 s Rs gm 2 Cgs Cgs C 4

5 G m /I d, V -1 Methodology 3 2 g m /I d Technique Baseband applications (High gain, High precision) WI: ~1/S L=3nm V sub = V (2µC ox /ni dnorm ) SI: µ,, n High Frequency applications (High drive current) 1 R sd v sat V. Kilchytska et al. SSE Normalized drain current, I d /(W/L), A independent on V T independent on L (except SCE) independent on V sub g m /W V d =1 V V g =V Th +.6 V g m -A v Analog Metric SCE, R sd Short-L Long-L Intrinsic gain, A v analogue of I on I off digital metric very visual independent on V T Allow fair comparison of different devices & at different conditions 5

6 Common features Si film thinning g m /W (ms/µm) 2 W NW =15 nm (a) W NW =45 nm W=1 µm quasi-planar.5 1 L=17 nm 1µm V g =.2 1.4V V d =1 V V UTBB g =V Th +.6 VV. Kilchytska et al. EuroSOI 214 V. Kilchytska et al. SSE Intrinsic gain, A v (db) Drain Voltage, V d, V quasi volume inversion operation conditions + improved SCE control I d and g m are improved V EA & A v Intrinsic Gain, A v, db 4 L = 3 nm 3 2 A v v = (g ( m /I d ) V EA operation bias point at ~V T on the condition that R sd, interfaces, µ, etc. are well tolerated 6

7 Common features High-µ channels G m /I d, V -1 At present either strain introduction or channel orientation 3 2 FinFETs L=5nm V d =1V g m /W (ms/µm) P-channel g m,max_lin /(W/L) (µs) P-channel (a) 1 V d =2 mv L (nm) 1 w/ strain L=17 nm 1µm w/o strain I dnorm, I d /(W/L), A µ booster G m, I d SCE control S and DIBL V EA Tradeoff for Analog??? Depends on application / bias point of interest V d =1 V V g =V Th +.6 V Intrinsic gain, A v (db) V. Kilchytska et al. EuroSOI 214 7

8 UTBB specificity effect of GP S G D gm/w (µs/µm) M.K.Arshad et al. SSE 213 L= 3 nm 1 µm Intrinsic gain, Av (db) no-gp p-gp n-gp V d = 1. V V g = V Th +.6 V p-substrate GP implementation in UTBB: SUB back-bias schemes V T adjustment Improved SCE control (suppression of SUB depletion) BUT Additional implantation µ degradation? SUB depletion suppression body factor n p n BOX GP Any effect on Analog FoM? G m and I d stay almost unaffected sensitive to GP realization (e.g. if GP implantation is not well adjusted, one might see DIBL V EA A v_dc ) 8

9 Specificity of UTBB V sub : S, DIBL, but V T I on V sub + : µ G m max & I on Effect of V sub Trade-off for analog FoM??? Early Voltage, V EA, V I d /(W/L), µa 15 Vsub=-2V L=1nm V -.5V 1 V.5V 1V 1.5V L=3nm G m /I d = 1V -1 5V -1 L=1nm G m /I d, V Substrate bias, V d =V V g, sub V, V V d =V g, V V. Kilchytska et al. SSE 212 Intrinsic Gain, A v, db Vsub=-2V V -.5V V.5V 1V 1.5V V d =V g, V V sub + I d norm of 5-1% (sign of µ ) V sub V EA (as a result of DIBL improvement) G m /I d (at low V g =V d ) (result of V T shift) one can win ~ 5 db (in max A v range) V sub I d V EA g m /I d A v + - Choice of V sub + or - depends on targeted applications (either I d or A v ) 9

10 Specificity of UTBB ADG regime: V g =V sub (similar to DTMOS in PDSOI) V t s gox V g source channel t box Si substrate V d V GP drain BOX GP QDG regime: V sub (or V GP ) = k V g V t s gox source channel t box Si substrate ADG regime V g with k=1 25 V d V GP drain BOX GP Gm/W, µs/µm 6 4 b V sub V d =1V, V g ~V Th 2 SG ADG k=5 k=1 k=15 k= V. Kilchytska et al., SSE 213 Av, db V sub Beneficial and ± easy thanks to thin BOX and GP simultaneous improvement of electrostatic features and performance enhancement V Th modulation achieved in ADG & QDG mode is accompanied by S and DIBL and I off =const (Contrarily to the constant V sub biasing in SG mode) I d and G m + DIBL + A v can actually be exploited for analog applications impact of parasitic resistance and capacitance??? dynamic performance reduction??? 1

11 g m - A v metric f-range f S. Makovejev et al. ULIS 214 S parameters VNA 4 khz 4 GHz S ij Y ij conversion de-embedding g d = Re(Y dd ) L f Frequency-dependent effects: Floating body, self-heating, substrate coupling, g d (f) & g m (f) Gain (f) Performance prediction from DC data is insufficient Quest for wide-f characterization g m A v analogue metric is strongly f-dependent: g m, g d, A v with f g d (f) = g intr + Dg d_fb (f) + Dg d_sh (f) + Dg d_sub (f) 11

12 g d (f) Reasons Conductance, ms S parameters VNA 4 khz 4 GHz de-embedding S ij Y ij conversion g d = Re(Y dd ) V g =V d =1V L = 1 nm nogp SH SUB Dg d_sub Dg d_sh source BG C R sub GR R Si gate channel C BOX C inv C SC C Si drain BOX substrate Response of minority carriers f 1SUB ~ (C SC R GR ) -1 Response of majority carriers f 2SUB ~ (C Si R Si ) -1 1 V g =.6 V; V d =1V DC S. Makovejev et al. SSE 212 Frequency, Hz Two main reasons of g d (f) variation in UTBB are: SH and SUB-related effects g d (f) = g intr + Dg d_fb (f) + Dg d_sh (f) + Dg d_sub (f) v BGS D g ( n 1) g C d _ SUB BGD C CBGD C SBG GBG m C v v sub BGS DS v DS V. Kilchytska et al. IEEE EDL 23 12

13 g d (f) vs. techno L, T Si, BOX scaling phonon boundary scattering (when smaller than phonon mean free path 1-3 nm) thermal capacitance C th use SOI-like architectures high J ds SH SUB L T Si ± W fin BOX S-to-D proximity Inversion in the substrate (by V d ) over the whole S-to-D distance high J ds interface proximities interface effects thermal conductivity R th coupling through the substrate reduces thinner thermal barrier stronger coupling through the substrate 13

14 g d (f) UTBB GP effect S G D n p n nogp p-substrate BOX GP SUB with GP S. Makovejev et al. ULIS 214 GP allows to suppress SUB-related g d (f) variation SH is the main reason of g d (f) variation g d (f) = g intr + Dg d_fb (f) + Dg d_sh (f) + Dg d_sub (f) 14

15 A v (f) experiments UTBB UTBB vs. FinFET FinFET with GP ~1% SH SUB SH no GP SUB ~35% S. Makovejev et al. SOI Conf. 211 S. Makovejev PhD Thesis 212 SH is the main reason of g d (f) variation both in UTBB FDSOI and SOI-based FinFETs 15

16 f T (GHz) Importance of parasitics C dse C gse C gsi C gde C gdi With devices downscaling importance of extrinsic device parasitics enormously increases. They can even dominate. Particularly important for advanced architectures (multi-fins, 3D, thin-body, ) C dsi C dse Intrinsic Pointed out on example of FinFETs: measured f T values (i.e. including parasitics) are much lower in FinFETs comparing to the planar counterparts, while intrinsically achievable values are the same It is important to separate intrinsic and extrinsic elements C gd = C g de + C g di C g de Including Extrinsic R g G ate C gs = C g s e + C g s i C g di Intrins ic g m.v gs g d R d Drain C ds = C ds e + C ds i J.-P. Raskin J. of Telecom. and Information Technology 29 C g s e C g s i C ds i C ds e R s L g (nm) S ourc e 16

17 RF FoM FinFETs Effect of parasitics f T L=6nm C inner R s +R d C outer f max C inner R s +R d C outer R g J.-P. Raskin J. of Telecom. and Information Technology 29 Wu and Chan (IEEE TED 27) 6% of f T is due to C inner 15% due to C outer + R S,D 4% of f max is due to R g 3% due to C inner C inner is a big bottleneck for FinFET s RF performance Specific for 3D Largest effect is due to coupling between S/D side walls and G wrapping between the fins C inner is predicted to be reduced by S fin or by H fin /W fin C ov C 3 C 1 C 2 C C C 17

18 RF FoM UTBB Effect of parasitics Parasitic R sd no - GP f T ext. g m int. g m (w/o R sd ) L = 3 nm L = 5 nm L = 1 nm UCL Parasitic C gge C gg C g g e C ggi no - GP (IT R S ) L = 27 nm) L = 3 nm L = 5 nm L = 1 nm HP L OP M.K.Arshad et al, SSE 214 Increased impact of R sd and C gge as L particularly C gge : C ggi > C gge in 1 nm-long devices, but C gge > C ggi in 3 nm-long ones Process was not optimized for RF f T as high as requested by ITRS for LP applications is achievable if ITRS requirements for R sd and C gg are respected 18

19 Conclusions #1 Conductance, ms L = 1 nm V g =V d =1V V g =.6 V; V d =1V SH SUB DC Frequency, Hz Performance prediction based exclusively on DC data may be inaccurate (device benchmarking may be misleading) W f = 5 N f = 8 no - GP ext. f T int. f T (w/o R sd ) int. f T (w/o R sd + C gge ) L = 3 nm L = 5 nm L = 1 nm (ITR S ) L = 27 nm) HP L OP Impact of parasitics on device FoM enormously increases with L wide-band analysis is required for the fair FoM assessment separation of intrinsic and extrinsic elements (and related performance) is mandatory adequate structures (with RF access pads) should be included in the layout from the very beginning of the technology development 19

20 Conclusions #2 Transconductance, g m /W, µs/µm Planar [ref.36 in *] FinFETs [ref.36 in *] Optimized FinFETs [ref.36 in *] UTBB W=1µm [*] UTBB W=8nm [*] Intrinsic Gain, A v, db UTB B UTB B UTB B S tres s /s train E ng. F inf E T + P DS OI X B UL K X P DS OI w/ s tres s /s train + B UL K w/ s tres s /s train UT B UT B B UT B B w/o R + sd UT B B w/o R sd and C gge E T S OI IT R S Both technologies are promising for Analog/RF outperforming other technologies Both FinFETs and UTBB exhibits relatively high f T (not as high as HP targeted processes), but combined with LOP and LSTP Potential for improvement through the optimisation of parasitics Good contender for mobile/wireless applications with LOP/LSTP options 2

21 ACKNOWLEDGEMENTS Our Colleagues and PhD students M.K.Md. Arshad, D. Lederer, P. Simon, G. Pailloncy, M. Emam, L. Vancaillie, D. Levaque, T. Rudenko, J. Alvarado, O. Moldavan, T.M. Chung, A. Kranti, J. Tinoco, S. Burignat actively participated in the characterization/simulation work as well as gathering and analyzing the results presented during this short course Leti & ST-M teams and particularly F. Andrieu, O. Faynot, T. Poiroux, M. Haond, N. Planes for providing UTBB FD SOI devices and valuable discussions Imec team and particularly N. Collaert, C. Claeys, M. Dehan, M. Jurczak, A. Mercha, B. Parvais, R. Rooyackers, E. Simoen, V. Subramanian for providing FinFETs and valuable discussions Research projects. Reaching 22 WELCOME Characterization Platform (ELEN/ICTEAM/UCL): 21