Monolithic Microwave Integrated Circuits

Transcription

1 SMA Compound Semiconductors Lecture 10 - MESFET IC Applications - Outline Left over items from Lect. 9 High frequency model and performance Processing technology Monolithic Microwave Integrated Circuits General concept Microstrip layout; Discrete components Specific examples Mesa etched; Ion implanted Digital Logic The difficulty of using depletion-mode transistors General comments Logic families FET logic; Buffered FET logic (BFL); Schottky diode FET logic (SDFL) Direct-coupled FET logic (DCFL) Complementary FET logic Other building blocks Transfer gates Memory cells (none exists, or is likely to anytime soon) C. G. Fonstad, 3/03 Lecture 10 - Slide 1

2 Linear equivalent circuit models - schematics In Lecture 9 we developed a small signal linear equivalent circuit for the MESFET; it can be drawn as: g + d s vgs gmvgs go - To extend this model to high frequencies we introduce small signal linear capacitors representing the charge stored on the gate: g + Cgd s d s vgs - q G Cgs gmvgs go s C Q C gd q G gs v GS v DS Q C. G. Fonstad, 3/03 Lecture 10 - Slide 2

3 MESFET - linear equivalent circuit, cont For a MESFET biased in saturation, we find the following expressions for the conductances in the small signal equivalent circuit model: i G gi = 0 g Q r i G = 0 Q v GS g m i D v GS È o Î Í v DS (f b -V GS ) Q = G Í1- ( f b -V P ) g o i D ª li = I /V Q D D A v DS The intrinsic gate-to-drain capacitance, C gd, is 0 in saturation, but in a real device there is a small, parasitic (extrinsic) C gd ; the value is determined empirically. The intrinsic gate-to-source capacitance, C gs, is dq G /dv GS, where the gate charge, q G, is: L q G = WqN Dn Ú x d ( y)dy Not easy to evaluate! 0 C. G. Fonstad, 3/03 Lecture 10 - Slide 3

4 Impact of velocity saturation - Model A' Consider a MESFET with such a short channel that the carriers reach their saturation velocity at very small v DS. The voltage drop along the channel will be small and the depletion region width under the gate will be uniform: x d ( y) ª x d (0) = 2e s (f b - v GS ) qn Dn In such a device, the current will be that in a uniform resistor when vds is small: i D ª Wq N Dn [a - x d (0)]m e v DS L = Wq N Dn [a - 2e s (f b - v GS ) qn Dn ]m e v DS L for v DS Ls sat /m e In saturation the electrons in the channel will be moving at their satuation velocity, s sat, and the current will be: i D ª Wq N Dn [a - x d (0)] s sat = Wq N Dn [a - 2e s (f b - v GS ) for v DS Ls sat /m e Cont. on next slide qn Dn ]s sat C. G. Fonstad, 3/03 Lecture 10 - Slide 4

5 Impact of velocity saturation - Model A', cont. Continuing with the short, velocity saturated MESFET, we can use our earlier definitions of G o and V P to write the drain current at low v DS as: È ( f 1- b - v GS ) i D = G o Í v ÎÍ ( f b -V P ) DS for v DS Ls sat /m e And, in saturation the current is: È id = G o Í 1- ÎÍ ( f b - v GS ) ( ) f b -V P Ls sat m e for v DS Ls sat /m e The linear equivalent circuit transconductance in this device when it is biased in saturation is: ( V GS ) g m i D v GS = Ws sat e s qn Dn /2 f b - Q = GoLs sat m e 2( f b -V GS (f b ) -V P ) Cont. on next slide C. G. Fonstad, 3/03 Lecture 10 - Slide 5

6 Impact of velocity saturation - Model A', cont. Before continuing we can first compare this result with the earlier result for a MESFET with no velocity saturation: È g m = G Í ( f b -V P ) - (f b -V GS With no velocity saturation : ) o Í Î (f b -V P ) With strong velocity saturation : g m = m G o Ls sat e 2(f b -V GS )(f b -V P ) Finally, turn to the incremental gate-to-source capacitance. It easy to calculate in this model. We begin by finding the charge on the gate, and then differentiate it: L q G = WqN Dn Ú x d (y)dy ª-WL qn Dn 2e s (f b - v GS ) /qn Dn 0 Thus, C gs q G v GS ª W L e s qn Dn /2(f b - v GS ) is We'll use this shortly. C. G. Fonstad, 3/03 Lecture 10 - Slide 6

7 High frequency models - short circuit current gain A measure of the high frequency performance of a transistor is obtained by calculating its short circuit current gain, b sc (jw), and finding the frequency at which its magnitude is 1: i in (jw) g s + vgs - Cgs Cgd gmvgs go d s i out (jw) i out ( jw) jwc g m ) -1 = gd v gs - g m v gs jw(c gd b sc ( jw) = = i in ( jw) jw(c gs + C gd )v gs jw (C gs + C gd ) g m g m b sc ( jw) ª for w << gm C gd w(c gs + C gd ) and thus, b sc ( jw) = 1@ w t = g m (C gs + C gd ) Note : C >> C gd, so the assumption is valid, i.e., w << g m gs t C gd C. G. Fonstad, 3/03 Lecture 10 - Slide 7

8 High frequency models - f t A useful way to visualize this result is make a log-log plot of the magnitude of the short circuit current gain verses frequency, i.e., log b sc (jw), vs. log w. This is called a Bode plot: log b sc w t = g m (C gs + C gd ) ª g m C gs w z = g m C gd w z log w w t Note: Usually C gs >> C gd, so typically w z >> w t. C. G. Fonstad, 3/03 Lecture 10 - Slide 8

9 High frequency models - The meaning of w t We had: C (recall C gs >> C gd ) w t = g m (C gs + C gd ) ª g m gs Our model for a device with extreme velocity saturation gave us: g m = Ws sat e s qn Dn /2(f b - v GS ) Thus: w t ª ssat L C = WL e s qn Dn /2(f b - v GS ) gs This can also be written as the inverse of some time, t tr : w t = 1 t tr, where for this device t tr = L s sat The time, t tr, is seen to be the transit time of the electrons through the channel. This is a very general result for w t, i.e., that it can be written as the inverse of the transit time of the relevant carriers through the device. C. G. Fonstad, 3/03 Lecture 10 - Slide 9

10 High frequency models - More on w t The result, w t = 1 t tr, where t tr = device transit time is very general and very useful for evaluating a device concept. As examples of what might be found, we list below the results for MOSFETs and BJTs, along with the result we just obtained: For an FET without velocity saturation: t tr = L 2 m e (V GS -V T ) For an FET with strong velocity saturation: t tr = L s sat For an BJT without velocity saturation: 2 t tr = w B 2D min. B C. G. Fonstad, 3/03 Lecture 10 - Slide 10

11 One final model observation - Insight on g m We in general want an FET with as large a g m as possible. We can get insight on how to achieve this by looking at our expression for w t, and using what we have learned about it being related to the transit time: w t = 1 t tr and w t = g m C gs Setting these two expressions for w t equal, and solving for g m : Cgs g m = t tr This result teaches us that to get a large g m we must have: 1. The shortest possible transit time 2. The largest possible coupling between the gate electrode and the channel charge (that is, the largest possible C gs ). Pretty neat isn't it?! Useful, too. C. G. Fonstad, 3/03 Lecture 10 - Slide 11

12 MESFET Fabrication: A mushroom- or T-gate MESFET (Image deleted) See Hollis and Murphy in: Sze, S.M., ed. High Speed Semiconductor Devices, New York: Wiley, C. G. Fonstad, 3/03 Lecture 10 - Slide 12

13 MESFET Fabrication - representative processing sequences (Image deleted) See Hollis and Murphy in: Sze, S.M., ed. High Speed Semiconductor Devices, New York: Wiley, Double recess process SAINT process C. G. Fonstad, 3/03 Lecture 10 - Slide 13

14 Microwave Monolithic Integrated Circuits: two views See Thayne, Elgaid, Terenent Devices and Fabrication technology [RFICs and MMICs] in RFIC-amd-MMIC- Perspective view: M-S Diode: 2 ff/cm 2, 1.6 x A/µm 2 (Images deleted) FET: I DSS = 120 ma/mm, V p = -1.5V, f T = 12.3 GHz, g m = 130 ms/mm (all at design-and-technology ed. By I.D. Robertson and S. V DS = 2.5 V, V GS =0 R: 50 W per sq. C: 0.25 ff/cm 2 L: 1nH-20nH Lucyszyn (IEEE,London, UK 2001) pp Top view: C. G. Fonstad, 3/03 Lecture 10 - Slide 14

15 Microwave Monolithic Integrated Circuits: an implanted mesa process (Image deleted) See Bahl, I. and Bhartia, P., Microwave Solid State Circuit Design Hoboken, N.J., Wiley-Interscience, C. G. Fonstad, 3/03 Lecture 10 - Slide 15

16 Microwave Monolithic Integrated Circuits: a planar implanted process (Image deleted) See H. Singh et al, IEEE 1991 Microwave and Millimeter-Wave Monolithic Circuits Symposium C. G. Fonstad, 3/03 Lecture 10 - Slide 16

17 MESFET Logic Families: FET Logic (FL) The challenge of normally-on logic: Multiple inputs: (< 0) C. G. Fonstad, 3/03 Lecture 10 - Slide 17

18 MESFET Logic Families: Buffered FET Logic (BFL) FL is effected by output loading (fanout) High speed requires large static current through diodes Adding a source-follower buffer yields a big improvement C. G. Fonstad, 3/03 Lecture 10 - Slide 18

19 MESFET Logic Families: Schottky Diode FET Logic (SDFL) Input diodes Level shift diodes Diodes can also be used for logic functions, ala DTL, TTL M-S diodes are extremely fast This is very similar to BFL, but the partitioning is different, and now multiple inputs are added by adding more diodes C. G. Fonstad, 3/03 Lecture 10 - Slide 19

20 MESFET Logic Families: Direct coupled FET logic (DCFL) Requires both e-mode and d-mode devices The MESFET equivalent of n-mos The input voltage must be less than the turn-on voltage of the gate This circuit provides good speed, low power, and high density C. G. Fonstad, 3/03 Lecture 10 - Slide 20

21 MESFET Logic Families: Super-buffer for DCFL (SBFL) The switching performance of DCFL can be improved by using a quasi-comlementary push-pull driver Multiple inputs each require a switch and pull-down transistor This circuit introduces some spiking on the lines so the supply and ground must be robust. C. G. Fonstad, 3/03 Lecture 10 - Slide 21

22 MESFET Logic Families: Source-coupled FET logic (SCFL) or Current mode logic (CML) The MESFET equivalent of ECL The output must be level-shifted before going to the next stage C. G. Fonstad, 3/03 Lecture 10 - Slide 22

23 Comparison of three MESFET logic families: layouts and logic swings C. G. Fonstad, 3/03 Lecture 10 - Slide 23

24 Transfer gate A single FET connected in a pseudo-common-gate configuration functions as a transfer gate. A normal logic gate is used to open and close the transfer gate C. G. Fonstad, 3/03 Lecture 10 - Slide 24

25 Memory cells High gate leakage levels have precluded the successful use of dynamic memory cells with MESFETs. All memory is based on static cells (flip-flop stages) C. G. Fonstad, 3/03 Lecture 10 - Slide 25