Modeling Total Ionizing Dose Effects in Deep Submicron Bulk CMOS Technologies. Michael McLain, Hugh Barnaby, Ivan Sanchez

Transcription

1 MURI Modeling Total Ionizing Dose Effects in Deep Submicron Bulk CMOS Technologies Michael McLain, Hugh Barnaby, Ivan Sanchez Department of Electrical Engineering, Ira A. Fulton School of Engineering, Arizona State University, Tempe, AZ May 2008

2 Acknowledgements We would like to thank AFOSR and the MURI program MURI We would also like to acknowledge the additional support of AFRL, DTRA, DARPA, and the Boeing Company. 2

3 Motivation Characterize and model radiation damage effects in modern CMOS device technologies Technologies: - deep submicron bulk CMOS, - silicon on insulator (El-Mamouni) 3

4 Previous Research May Device-level Radiation Effects Modeling Overview of numerical (TCAD) simulation approaches to modeling radiation effects in CMOS devices Sheet Charge Trapped Charge vol. distribution

5 Previous Research June Total Ionizing Dose Effects in Bulk Technologies and Devices Characterize, parameterize TID effects. Formalize closed form analytical expressions for TID effects in devices (130nm CMOS). Normalized Capactiance 1 Pre-rad 0.99 After 1 -week anneal Rad-induced shift Gate Voltage [V] Ionizing radiation - ÄN ÄN ot it + - x d! + - t ox + Dk! Dk g D H volume + - g f f p f y H+ H+ r Si-SiO 2 interface f H H r H H area y ( å) f ot ( å) t ox r ( å) fdhfittox 5

6 Previous Research June Modeling Total Ionizing Dose Effects in Deep Submicron Bulk CMOS technologies Description and initial validation of radiation-enabled compact modeling approach for CMOS technologies ( 90nm CMOS). to phys. mod. Model validation Device comparison Experimental Data Transistors Nit, Not from phys. mod. Compact Model Device I -V sim static, dynamic to circuit sim. Technology Parameters External Conditions - material (! X ) - device (" ms, t ox, N x ) - other structural features ( e.g. trench aspect ratio ) Device Layout - gate geometry (W, L) - RHBD - Bias - Temperature - Time - Packaging 6

7 Recent Work (2008) Full analytical model of TID effects on bulk CMOS isolations oxides Analytical model for TID defect buildup Effects on sidewall surface potential Radiation-induced edge leakage model and validation New data and analysis of effects on 90 nm field oxides and multi-fingered transistors (additional material) 7

8 Ionization Damage in Silicon Dioxide 8

9 Hole trapping process Ionizing radiation Si-SiO 2 interface f p,i + - surviving hole (p) - hole trap (N T ) + area = σ(ε) - trappped hole (N OT ) f p - hole flux t ox 9

10 Oxide trapped charge formation # f p # x =! # p " + # t Dg & f o y Dg & o f y " R (steady state) p f & p, i! Dgofytox (f p > 0 for all x) # N # t ot =! ( N " N (t)) N T T óf p,i ot óf p Not (t) " $ (Assume no saturation or annealing and sheet densities at interface)! N " N ód&! tg ot T f ot D (After Rashkeev et al. TNS 2002) o f y t ox 10

11 Defect buildup: N ot 130 nm data Defect buildup is: 1. Greater for higher oxide fields (consistent w/ f y ) 2. Linear with dose (no saturation yet) Data obtained from measurements on STI field oxide capacitors 11

12 Interface trap formation Two Stage Hydrogen model DH volume Si-SiO 2 interface - hydrogen defect (D H) H+ - protons x d f p H+ H+ H+ f H H H H H - Si-H (N SiH ) - dangling bond (N it ) f H - proton flux + + SiH + H! Si + H 2 t ox! N +! f + H H = NDH DHfp "! t! x # Nit ( t) # t =! N f "! ( t) f # gen SiH + pass it H2 H N (After Rashkeev et al. TNS 2002) 12

13 Defect buildup: N it 130 nm data N it defect buildup is: 1. Greater for higher oxide fields (consistent w/ f y ) 2. Linear with dose (no saturation yet) 3. Less than N ot buildup Data obtained from measurements on STI field oxide capacitors 13

14 Modeling Radiation Effects on Devices 14

15 Pre-irradiation behavior Surface potential based 1.0E-03 analytical model 1.0E Pre-irradiation V 1.0E-05 D = 1 V t 1.0E ox = 2 nm 1.0E E E E E E E E E E Gate Bias (V) L Gate oxide n + Drain Poly Gate n + Source W gate STI cutline STI >> t ox Potential applied to the gate controls the flow of carries (electrons) from source to drain in the channel 15

16 Radiation-induced leakage 1.0E E E E E E E E E E E E E-15 re-rad ost -rad V D = 1 V t ox = 2 nm 1.0E Gate Bias (V) V GS Surface potential based analytical model as-drawn V DS parasitic W eff L t ox,eff Leakage Ionizing radiation Gate oxide n + Drain Poly Gate n + Source gate STI Leakage Charge buildup (N ot ) in the STI inverts the sidewall and induces a parasitic leakage path along the edges of the as-drawn transistor 16

17 Parasitic leakage model I DS Post-rad NMOS prerad Thin t ox Med. t ox Thick t ox prerad Parasitic edge device modeled as several thin, medium, and thick nfets operating in parallel with as drawn FET V G 17

18 Parasitic device description gate STI ε-field line Edge devices represent distinct subdivisions of conducting sidewall gate oxide interface drain-source diffusion depth STI corner p-type Si body W s t ox (i) + + N ot (i), D it (i) STI z recessed isolation The number (n) of edge devices balance need for simulation accuracy with computational efficiency Defect generation and effects of defects on surface potential modeled analytically for each device 18

19 Doping, t ox vs. sidewall depth Sidewall Doping NA (i) V t im plant PT im plant Log Effective t ox(i) 0 W S 2W S 3W S 4W S 5W S 6W S Model requires estimates along sidewall doping concentration (primary fitting parameter) effective oxide thickness! 2 ( i) z( i) t ox! z(1) z(2) z(3) z(4) z(5) z(6) 19

20 Effect of doping on ψ s! V t sidewall implant 90 nm N A = 2#10 17 Doping Concentration NA (cm -3 ) PT implant Surface Potential " s N A = 5#10 17 N A = 1#10 18 N A = 3.3# Depth Along Sidewall w (nm) x #10 12! N ot [cm -2 ] Increased doping near the top edge of the STI sidewall reduces the impact of the sidewall parasitic transistors Lower doping values translate to a higher surface potential for a given N ot buildup and oxide thickness 20

21 Effect of doping on ψ s (cont.) 90 nm RVT transistor 90 nm I/O transistor Surface Potential ψ s w [nm] ΔN ot [cm -2 ] 3 Surface Potential! s w [nm] #N ot [cm -2 ] 3 " As N A is increased, there is a decrease in surface potential (i.e., a valley with respect to w) If N A > cm 3, fluctuations in the doping profile will have a negligible impact on ψ s if N A < cm 3, non-uniformities in the profile will strongly affect ψ s 21

22 TCAD Calculation of N ot distribution 2-D device simulations using radiation enabled module in Silvaco Atlas approximate N ot buildup along sidewall gate gate tox STI tox STI body body 1 krad 10 krad 22

23 Model for defect generation (N ot ) Normalized Not [cm -2 rad -1 ] 2.50E x E x E x x E X E E E E- 06 Not/rad (TCAD) Not/rad Not(i)/rad A (analytical) 0 W S 2W S 3W S 4W S 5W S 6W S 4.0E- 06 W [µm] 6.0E E E E- 05 ÄN f y t ox ( i) " ox! ( i)! å ox ( i) t å V ox gb ( i) ox ( i) ( i) + å0 ( i) N ódg f ( i) t ( i) ot! T o y ox 23

24 Effects on surface potential Calculations of trapped charge and interface traps used in defect potential expression for i th device bulk potential (doping) ö q C ( i) = ( N ( i)! D ( i) "( ø ( i) ö ( i ) nt ot it s! ox Implicit equation for surface potential solved iteratively for i th device 2 2 ( i) + ö ( i) " ø ( i ) = ã ö H (u) (Vgb " ö ms nt s i! t i b surface potential (After C. McAndrew, TED, 2002) Normalized e-field function 24

25 I Model for drain current response Surface potential responses (at both source and drain ends) can be calculated iteratively for each elementary transistor as a function of V gb and inserted into drain current equations 1 2 [" $! 3 / $ " $! 3 / ] 2 2 ( ) ( = ( Vgb $ Vfb )(" sd $ " ss ) $ (" sd $ " ss ) $ 2 sd t ss t ) # 3 I 2 =! t (" $ " + #( " $! $ " $! ) sd ss sd t ss t N Ws Id, i = ì n Cox (I1 + I2 ) Id =! I L i = 1 d,i ψ sd ψ s at drain ψ ss ψ s at source I 1 Drift Component I 2 Diffusion Component 25

26 Comparison of data and model 130 nm data 90 nm data Drain Current (A) E-04 V ds = 50mV 1.E-05 W = 280 nm L = 120 nm 1.E-06 1.E-07 1.E-08 1.E-09 1.E-10 pre-rad 100 krad 500 krad 1 Mrad Drain Current (A) V ds = 1V W = 540 nm L = 120 nm pre-rad 22 Mrad CSM(as_drawn ) CSM(2M) 10 1.E Gate Voltage (V) Gate Voltage (V) Comparison of measured pre- and post-irradiation data (symbols) with modeled radiation response characteristics (solid lines) for single stripe nfets in 130 and 90 nm technologies 26

27 Summary eed for accurate radiation-enabled models (e.g., edge leakage) that can be implemented in circuit simulators is growing odel based on new technique which calculates nonuniform defect distributions and surface potential responses along the STI sidewall to model the parasitics imulated results using the model compare well to experimental data obtained on 130 nm and 90 nm devices odel predicts that in deep-submicron technologies, the doping concentration near the sidewall corner has a significant impact on the MURI radiation 2008 response 27

28 Additional Material 28

29 Single and Multi- Finger Devices 29

30 Experimental results: W < 1 µm Single stripe 90 nm device is fairly radiation tolerant to TID 1.E E E E V g = 1.1 V (rad bias) L = 80 nm W = 0.9 µm V D = 1 V 0k Data suggests that asdrawn device in parallel with parasitic device in strong inversion E E-09 Parasitic 200k 500k 1M S G D E-10 2M 1.E Gate Bias (V) Gate Voltage [V] 30

31 Experimental results: W > 1 µm Radiation response for multi-fingered 90 nm device shows increased susceptibility to ionizing radiation 1.E E E E E E-09 1.E V g = 1.1 V (rad bias) L = 80 nm W = 6 µm V d = 1 V 1.E Gate Bias (V) Gate Voltage [V] 0k 200k 500k 1M 2M 1 µm S D S D S D S G 31

32 Comparison of devices Offstate leakage current (I off ) ratio 1000 Ioff (post)/ioff (pre ) Multi-fingered 1 1.0E+05 prerad 1.0E E+07 Dose (rad) w=0.14 l=0.08 w=0.2 l=0.08 w = 0.24 l=0.08 w=.9 l=0.08 w=3 l=0.08 w=6 l=0.08 w = 0.14 l=0.1 w=0.2 l=0.1 w = 3.75 l=0.1 Single stripe I off defined as current at V g = 0 V Data shows that as gate width increases, offstate leakage ratio significantly increases Multi-fingered devices significantly more susceptible to TID than single stripe devices 32

33 Failure of linear model 1000 Ioff (post)/ioff Ioff,post /Ioff,pre (pre) Data Linear model # Fingers edges Unknown mech Linear model predicts I off (m=n) = n*i off (m=1) n = # fingers Data shows super-linear increase in TID sensitivity Discrepancy suggests secondary cause needed to explain multi-finger response 33

34 Potential Cause Halo Implant Masking G S D S D S D S 1 µm Doping NA (cm -3 ) N A1 N A2 N A3 HALO masking reduces doping of thick parasitic 80 nm Depth Along Sidewall Halo Implant. Gate Gate Gate S D / S S / D S Outer poly gate fingers may block halo implant on inner fingers Halo Implant 34

35 Effect of lower doping N A3 (single stripe) 1.25 N A3 (multi-finger) Normalized Drain Current (A) E E E Post-irradiation Characteristics Decreasing N A3 ID (m=1) ID (m=6) 1E m = # fingers 1E Gate Bias (V) Normalized Drain Current (A) E E E E E E ID (1 finger) ID (6 fingers) Multi-fingered device has reduced threshold voltage ( V T ) due to lower doping in the p - type body 1.00E Experimental data (pre -rad) 1.00E Gate Bias (V) Pre-irradiation experimental data used to approximate doping difference (lower doping explains increased sensitivity to TID) 35

36 Single and multi-finger device summary Multi-fingered devices show a super linear increase in TID sensitivity Potential cause for increased susceptibility is halo implant masking (lower effective p- type body doping) Increased TID susceptibility in multi-fingered devices could have circuit design implications in this technology 36

37 Field Oxide Leakage 37

38 SRAM vs. Device 90nm comparison 4T SRAM > 100X increase in static supply current in SRAM array NMOS XSTOR < 10X increase in off-state leakage in NMOS devices Normalized ISB 0 1 Intra-device leakage I SB V DD = 1.3V RBB V DD = 1V no RBB After Clark TNS 2007 Gamma Dose ( Mrad(Si)) Lack of correlation between circuit and device response suggests inter- device and/or inter-cell leakage due to field oxide leakage 38

39 Leakage paths 1 NMOS Drain-to-Source N+ Source Polysilicongate Leakage N+ drain Leakage 1 39

40 Leakage paths 2 NMOS D/S to NMOS S/D n+ n+ n+ n+ Poly gate Metal/Poly Line Poly gate 2 Poly gate Metal/Poly Line Poly gate n+ n+ n+ n Leakage path 40

41 Leakage paths 3 NMOS D/S to NWELL n+ n+ p+ p+ n+ 3 Poly gate Metal/Poly line Poly gate n-well Poly gate 0V Metal/Poly line Poly gate V DD n+ n+ p p+ n+ n-well Leakage path 41

42 Leakage paths 4 4 NMOS NWELL to NWELL (only if wells at different potential rare in SRAM) n+ p+ p+ p+ p+ n+ n-well Poly gate Metal/Poly line Poly gate n-well V W1 Poly gate 0V Metal/Poly line Poly gate V W2 n+ n-well p+ p+ p p+ n+ n-well Leakage path 42

43 Test structures FOXFET variants 3 n+-to-n+ w/ metal gate w/ GB (L = 0.5 µm) w/o GB (L = 0.5 µm and L = 0.14 µm ) Example: N+ to Nwell w/ poly gate S D S 3 n+-to-nwell w/ metal gate w/ GB (L = 0.55 µm) w/o GB (L = 0.55 µm and L = 0.21 µm ) 1 n+-to-n+ w/ poly gate (L = 0.2 µm) 1 n+-to-nwell w/ poly gate (L = 0.28 µm) 2 nwell-to-nwell w/ poly gate (L = 1.5 µm and L = 0.9 µm) All FOXFETs designed with 200 µ m gate width G 43

44 Legend D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 Gate M1 M1 M1 M1 M1 M1 Poly Poly Poly Poly Drain n + n-well n + n-well n-well n + n-well n-well n-well n + Source n + n + n + n + n + n + n-well n-well n + n + Guardband yes no no yes no no no no no no Length, L (µm)

45 TID Results (LP) During irradiation, V g = 1.2 V for 0 < t < 30 and V g = 8 V for 30 < t < 90 Measurement bias: V g = 1 V, V d = 1 V, V s = V b = 0 V 7-9 magnitude increase in poly-gate devices < 4 magnitude increase in M1-gate devices Slight length effect 1.0E E E E E E E E E E E E E M1-gate Irradiation Rad bias: VG = 8V Time [Hours] Anneal D1 D2 D3 D4 D5 D6 1.0E E E E E E E E E E E E E -16 Poly-gate Irradiation Time [Hours] Anneal 29 days D7 D8 D9 D10 45

46 TID Results (SF_1) Measurement bias: V g = 1 V, V d = 1 V, V s = V b = 0 V 4-8 magnitude increase with poly-gate (much harder than LP) No TID threat in SF field path with metal overlap Slight length effect 1.0E E E E E E E E E E E E-17 Irradiation Anneal D1 D2 D3 D4 D5 D M1-gate Time [Hours] 1.0E E E E E E E E E E E-16 Poly-gate Irradiation Anneal D7 D8 D9 D Time [Hours 46

47 Design implications P+ guard-band and metal route should help N-well to n+ drain leakage under poly could be problem in standard SRAM 47

48 SF vs LP A doping effect Under leakage path Current α 1/N A 48

49 FOXFETs results summary All FOXFET variants in LP and SF technologies were tested up to 2 Mrad Results showed significant degradation in poly-gated n-well to n-well devices (not a large concern for most designs) Measurable degradation in n+ to n-well and n+ to n+ poly gated parts Could be cause of unaccounted for leakage in SRAM and other ICs Reverse body bias will mitigate leakage Annealing looks fairly normal, but biased anneals should be run Metal gated devices were much harder than poly-gate devices (impact of oxide efield on charge yield on defect buildup in FOX) LP was considerably softer than SF (effect of lower doping in body) 49