FinFET Modeling for 10nm and beyond - Si, Ge and III-V channel

Size: px

Start display at page:

Download "FinFET Modeling for 10nm and beyond - Si, Ge and III-V channel"

Dinah Adams
5 years ago
Views:

1 FinFET Modeling for 10nm and beyond - Si, Ge and III-V channel Yogesh S. Chauhan Assistant Professor and Ramanujan Fellow Nanolab, Department of Electrical Engineering IIT Kanpur, India chauhan@iitk.ac.in

2 Acknowledgements BSIM Team Chenming Hu Juan Pablo Duarte Darsen Lu Sourabh Khandelwal My students Chandan Yadav Avirup Dasgupta Tapas Dutta Yogesh S. Chauhan, IIT Kanpur 2

Group: Postdoc 3, Ph.D. 9, MTech 8, R.A.

3 About me Joined IIT Kanpur in 2012 Awarded Ramanujan Fellowship (2012) Received IBM Faculty Award (2013) Funding Device characterization laboratory (1.75crore) Upgraded computational infra. Group: Postdoc 3, Ph.D. 9, MTech 8, R.A. 3 Collaboration: >25 companies/universities Publications in last 3 years: 17 journal papers 18 conference papers Yogesh S. Chauhan, IIT Kanpur 3 Lab website

4 Joint Development & Collaboration Working closely with universities/companies on model development and support 03/12/2012 Yogesh S. Chauhan, IIT Kanpur 4

5 Outline Bulk MOSFET and Scaling FinFET and Compact Modeling Unified Compact Model for arbitrary geometry What next? Yogesh S. Chauhan, IIT Kanpur 5

IC industry for >40 years Closer distance between elements Pitch Faster signal transfer and processing rate For the same Chip size (or cost), more functionality Mass production Wafer size doubled

6 IC industry for >40 years Closer distance between elements Pitch Faster signal transfer and processing rate For the same Chip size (or cost), more functionality Mass production Wafer size doubled every 10years. Use less energy (or power) for same function In the last 45 years since 1965 Price of memory/logic gates has dropped 100 million times. The primary engine that powered the proliferation of electronics is miniaturization. More circuits on each wafer cheaper circuits. Miniaturization is key to the improvements in speed and power consumption of ICs. It s not technology! It s economy. Yogesh S. Chauhan, IIT Kanpur 6

7 Why divorce after 40 years? C g Gate Oxide Short Channel Big Problem Source Drain Body C g Gate Oxide Source Drain Q G = Q i +Q b Charge sharing C d Yogesh S. Chauhan, IIT Kanpur 7 Source: Chenming Hu

8 Making Oxide Thin is Not Enough Gate Source Drain Leakage Path Gate cannot control the leakage current paths that are far from the gate. Yogesh S. Chauhan, IIT Kanpur 8

9 MOSFET in sub-22nm era FinFET FDSOI NY Times Yogesh S. Chauhan, IIT Kanpur 9 SOITEC

10 One Way to Eliminate Si Far from Gate Thin body controlled By multiple gates. Gate Length Gate Length Source Gate Drain Source Gate FinFET body is a thin Fin. Drain Fin Height Fin Width N. Lindert et al., DRC paper II.A.6, 2001 Yogesh S. Chauhan, IIT Kanpur 10

11 Transistor Compact Model Technology Is the vehicle of information transfer EDA / Design Fast ~ 10μs / bias point Accurate Robust Crash free for all circuits. ~ 1% error Yogesh S. Chauhan, IIT Kanpur 11

12 Compact Model is Art Based on Science Output Conductance Current Saturation Quantization Gate Current GIDL Current Impact Ionization Current Noise models Mobility and Transport S/D Resistance Gate Resistance Short Channel Effects Core Overlap Capacitances Fringe Capacitances Inversion Layer Thickness Non-Quasi-Static Effects Substrate RC Network Parasitic Diode, BJT Self Heating Temperature Effects Proximity Effects Random Variations Y. S. Chauhan et.al., BSIM6: Analog and RF Compact Model for Bulk MOSFET, IEEE TED, Yogesh S. Chauhan, IIT Kanpur 12

13 BSIM-CMG: Industry standard FinFET model Selected as Industry standard 2012 FinFETs on Bulk and SOI Substrates Yogesh S. Chauhan, IIT Kanpur 13

triple-gate, quadruple-gate, cylindrical-gate; Bulk and SOI substrates Y. S. Chauhan et.

14 BSIM-CMG Common Multi-gate (BSIM-CMG): All gates tied together Surface-potential-based core I-V and C-V model Supports double-gate, triple-gate, quadruple-gate, cylindrical-gate; Bulk and SOI substrates Y. S. Chauhan et. al., Workshop on Compact Modeling, 2011, Boston. Yogesh S. Chauhan, IIT Kanpur 14

Model Drain Current(mA) 0.20 0.15 0.10 0.

15 Verification: 30nm to 10µm FinFETs 0.25 Each curve is for one Lg Symbols: Data; Lines: BSIM-CMG Model Drain Current(mA) L g Gate Voltage(V) Gm (ma/v) Yogesh S. Chauhan, IIT Kanpur 15 L g Gate Voltage(V)

16 g m` & g m`` of 30nm to 10µm FinFETs Yogesh S. Chauhan, IIT Kanpur 16

17 Temperature Model verified for FinFET Yogesh S. Chauhan, IIT Kanpur 17

18 FinFET s Various Complex Cross-Sections TSMC, IEDM 2010 Leti, VLSI 2012 IBM, VLSI 2012 Toshiba, VLSI 2012 Yogesh S. Chauhan, IIT Kanpur 18

19 Prior Models Available for Two Simple Cross-Sections Only Deductive model 1. Double-Gate FinFET: Charge Equation : 2. Cylindrical FinFET: Charge Equation: Yogesh S. Chauhan, IIT Kanpur 19

20 New Unified Model for Complex FinFET v O v Cross-Sections Inductive model = G v FB Model Parameters: Fin Area: v O q dep v CH A ch Channel Doping:N ch Channel Width: W Insulator Cap: C ins = q 2qn vt C m A + ln t ( q ) m + ln qt e qt 1 2 i ch ch ins ln qt = ( qm + qdep ) 2 insnch ε chw Unified Model for various Fin shapes SEM or imagined Yogesh S. Chauhan, IIT Kanpur 20 q 2 A C

Even FinFET with this fin shape Electron Concentration 10 8 10 6 10 4 10 2 10 0 BSIM-FET MODEL TCAD 0 0.1 0.2 0.

21 Even FinFET with this fin shape Electron Concentration BSIM-FET MODEL TCAD Gate Voltage (V) J. P. Duarte et. al., SRC TECHCON Yogesh S. Chauhan, IIT Kanpur 21

2~1 V g DS V g = 0.2~1 V V ds = 0.05 V V ds = 0.05 V 0 0.

22 Experimental FinFET Example: I-V SOI FinFET SOI FinFET L G = 10 µm SOI FinFET L G = 10 µm SOI FinFET L G = 10 µm SOI FinFET L G = 10 µm Drain Current V ds = 1 V g m V ds = 1 V Drain Current V g = 0.2~1 V g DS V g = 0.2~1 V V ds = 0.05 V V ds = 0.05 V Gate Voltage (V) *FinFET fabricated by SEMATECH Gate Voltage (V) Drain Voltage (V) Drain Voltage (V) Yogesh S. Chauhan, IIT Kanpur 22

23 BSIM-CMG Model Speed Improvement Model Speed Improvement ~ 30% New core model used in BSIM-CMG109 Yogesh S. Chauhan, IIT Kanpur 23

24 3D Model for Short Channel Effects SCEs are 3-D effects Need to solve the 3-D Poisson s equation. DIBL Equations: λλ: characteristic field penetration length Unified λ K. Suzuki, EDL 1996 C. P. Auth, EDL 1997 Yogesh S. Chauhan, IIT Kanpur 24

TCAD FinFET Example: I-V: Scaling Drain Current (A) 10-4 10-6 10-8 10-10 10-12 10-14 3.

25 TCAD FinFET Example: I-V: Scaling Drain Current (A) Bulk FinFET Lines: Model 3 Symbols: TCAD V ds = 0.05 V L = 1000,500, G 100,75,50 nm x Gate Voltage (V) Yogesh S. Chauhan, IIT Kanpur 25

26 Experimental FinFET on Bulk Example: New QM Effects + Body Bias model Lines: Old BSIM-CMG Lines: New BSIM-CMG 8 x QM Improvement 5 Cgg Bulk effect Improvement Vg Yogesh S. Chauhan, IIT Kanpur 26

27 State-of-the-Art 14nm FinFET Taller and Thinner Fins for increased drive current and performance 4/8/2018 Yogesh S. Chauhan, IIT Kanpur 27 Source: Anandtech

28 Future 10nm and beyond Source: Applied Materials Yogesh S. Chauhan, IIT Kanpur 28

29 Key points for 10nm and beyond Reduced leakage Better sub-threshold slope Ultra-thin channel Electrostatic control Nanowire transistor Higher mobility channel Si NMOS and PMOS Ge PMOS SiGe III-V materials NMOS InAs, InGaAs etc. I I off dsat ( na) W = Coxµ 2L W = L eff ( V gs V S V t TH 2 ) Yogesh S. Chauhan, IIT Kanpur 29

InGaAs FinFET Modeling BSIM-CMG with the new Quantum Effects model used to model InGaAs FinFETs L = 20 nm, H = 30 nm, W = 20 nm, Nfin = 4. S. Khandelwal, J. P. Duarte, N. Paydavosi, Y. S. Chauhan, J.

30 InGaAs FinFET Modeling BSIM-CMG with the new Quantum Effects model used to model InGaAs FinFETs L = 20 nm, H = 30 nm, W = 20 nm, Nfin = 4. S. Khandelwal, J. P. Duarte, N. Paydavosi, Y. S. Chauhan, J. J. Gu, M. Si, P. D. Ye, and C. Hu, "InGaAs FinFET Modeling Using Industry Standard Compact Model BSIM-CMG", Workshop on Compact Modeling, Yogesh S. Chauhan, IIT Kanpur 30

31 InGaAs FinFET Modeling L = 20 nm, H = 30 nm, W = 20 nm, Nfin = 4. Data from: J. J. Gu et al. IEDM 2012 Yogesh S. Chauhan, IIT Kanpur 31

32 InGaAs FinFETs with Triangular Cross-section T. Irisawa et al. IEDM 2013 Importance of accurate modeling of Quantum Effects Yogesh S. Chauhan, IIT Kanpur 32

33 Modeling of Germanium Ge FinFET may be used in 10nm node for better P-FinFET. Industry standard BSIM FinFET model can now model Ge FinFET. Early availability of a unified Si/Ge FinFET model facilitates technology-circuits codevelopment. Yogesh S. Chauhan, IIT Kanpur 33

34 Modeling Germanium FinFETs User selectable MOD to model Ge FinFETs Material Mode MTRLMOD = Si (Default) or Ge MTRLMOD =Ge invokes new mobility model for Ge MTRLMOD = Ge sets key parameters for Ge Band-Gap, Mobility MTRLMOD=Ge model verified with experimental data Excellent Model Calibration Results Scalable Ge FinFET Model Yogesh S. Chauhan, IIT Kanpur 34

35 Germanium Mobility Model Due to the lower m* of holes in Ge the charge-centroid is farther away from the oxide interface resulting in a weaker SR scattering. Ge mobility has a weaker dependence on E eff up-to 0.5 MV/cm as the impact of SR scattering is only seen at much higher E eff in Ge as compared to Si. Yogesh S. Chauhan, IIT Kanpur 35

36 BSIM-CMG Model Results for Ge pfinfets L = 130 nm S. Khandelwal et. al., "Modeling 20nm Germanium FinFET with the Industry Standard FinFET Model", IEEE Electron Device Letters, Vol. 35, Issue 7, July Yogesh S. Chauhan, IIT Kanpur 36

37 BSIM-CMG Model Scalability for Ge pfinfets L increasing L varying from 20 nm to 90 nm Scalable Model Yogesh S. Chauhan, IIT Kanpur 37

38 Forward Looking Modeling of Pillar/Nanowire FET Vertical Pillar FET Yogesh S. Chauhan, IIT Kanpur 38

39 Validation on Asymmetric Nanowire FET Symbols experimental data Ids-Vgs for N-type Nanowire for different temperatures S. Venugopalan et. al., "Modeling Intrinsic and Extrinsic Asymmetry of 3D Cylindrical Gate/ Gate-All-Around FETs for Circuit Simulations", IEEE Non-Volatile Memory Technology Symposium, Shanghai, China, Nov Yogesh S. Chauhan, IIT Kanpur 39

40 Modeling of III-V FinFET Chandan Yadav et. al., Modeling of GaN-Based Normally-Off FinFET, IEEE Electron Device Letters, June Yogesh S. Chauhan, IIT Kanpur 40

41 7nm & beyond Would it be a smooth ride? Effects in ultra-thin Si/Ge/III-V Transistors Quantum Capacitance Charge centroid Source to Drain Tunneling Bandgap variation with thickness Effective mass variation with thickness Yogesh S. Chauhan, IIT Kanpur 41

Quantum Capacitance Concept of the quantum capacitance was given by S. Luryi, which originates when vertical electric field partially penetrates the inversion charge in channel.

42 Quantum Capacitance Concept of the quantum capacitance was given by S. Luryi, which originates when vertical electric field partially penetrates the inversion charge in channel. The quantum capacitance depends on 2-D density of states ρρ 2DD = mm ππħ and valley degeneracy factor (g 2 v. ) Quantum Capacitance CC QQ = qq2 gg vv mm ππħ 2 Yogesh S. Chauhan, IIT Kanpur 42

43 Quantum Capacitance Thin body device is a 2D system. E 3 E 2 E 1 C. Yadav et. al., submitted in Solid State Electronics. Yogesh S. Chauhan, IIT Kanpur 43

44 Quantum Capacitance & III-V Very strong impact on gate capacitance with low effective mass channel Yogesh S. Chauhan, IIT Kanpur 44

45 Charge centroid Charge centroid in conjunction with Quantum capacitance can deteriorate C-V further. Yogesh S. Chauhan, IIT Kanpur 45

46 Modeling of Quantum Capacitance in III-V FinFET Avirup Dasgupta et. al., Modeling of Quantum Capacitance in III-V Transistors, being submitted in IEEE EDL. Yogesh S. Chauhan, IIT Kanpur 46

47 Source to Drain Tunneling in III-V FETs Under the barrier transport T. Dutta et. al., Source to Drain Tunneling in III-V MOSFETs, submitted in IEEE Electron Device Letters. Yogesh S. Chauhan, IIT Kanpur 47

48 Modeling SiGe FinFETs with Thin Fin Current Dependent Source/Drain Resistance S. Khandelwal et. al., submitted in IEEE Electron Device Letters. Yogesh S. Chauhan, IIT Kanpur 48

49 High Mobility channel Different materials for NMOS and PMOS Complex integration NMOS III-V materials NMOS InAs, InGaAs etc. PMOS Ge PMOS SiGe Bulk mobility of Ge = 4000 > Si 1450 cm^2/v-s How about using Ge based CMOS? Yogesh S. Chauhan, IIT Kanpur 49

First Experimental Demonstration of Ge CMOS

Standard Model and Experimental CMOS Circuit

50 First Experimental Demonstration of Ge CMOS Circuits from Purdue (IEDM 2014) NMOS PMOS H. Agarwal et. al., Modeling of Ge MOSFETs Using Industry Standard Model and Experimental CMOS Circuit Validation, submitted in IEEE Electron Yogesh Device S. Chauhan, Letters. IIT Kanpur 50

51 BSIM-IMG vs. Experimental Ge circuit Ge CMOS Inverter VTC H. Agarwal et. al., Modeling of Ge MOSFETs Using Industry Standard Model and Experimental CMOS Circuit Validation, submitted in IEEE Electron Yogesh Device S. Chauhan, Letters. IIT Kanpur 51

FinFET Modeling for IC Simulation and Design: Using the BSIM-CMG Standard Authors Yogesh Singh Chauhan, IITK Darsen D Lu, IBM Navid Payvadosi, Intel Juan Pablo Duarte, UCB Sriramkumar Vanugopalan,

52 FinFET Modeling for IC Simulation and Design: Using the BSIM-CMG Standard Authors Yogesh Singh Chauhan, IITK Darsen D Lu, IBM Navid Payvadosi, Intel Juan Pablo Duarte, UCB Sriramkumar Vanugopalan, Samsung Sourabh Khandelwal, UCB Ai Niknejad, UCB Chenming Hu, UCB Chapters 1. FinFET- from Device Concept to Standard Compact Model 2. Analog/RF behavior of FinFET 3. Core Model for FinFETs 4. Channel Current and Real Device Effects 5. Leakage Currents 6. Charge, Capacitance and Non-Quasi-Static Effect 7. Parasitic Resistances and Capacitances 8. Noise 9. Junction Diode Current and Capacitance 10. Benchmark tests for Compact Models 11. BSIM-CMG Model Parameter Extraction 12. Temperature Effects Available online on Elsevier. 4/8/2018 Yogesh S. Chauhan, IIT Kanpur 52

53 Relevant Publications H. Agarwal, P. Kushwaha, S. Khandelwal, J. P. Duarte, Y.-K. Lin, H.-L. Chang, C. Hu, H. Wu, P. D. Ye and Y. S. Chauhan, "Modeling of GeOI and Validation with Ge-CMOS Inverter Circuit using BSIM-IMG Industry Standard Model", IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, Aug C. Yadav, A. Agarwal, and Y. S. Chauhan, "Analysis of Quantum Capacitance Effect in Ultra-Thin-Body III-V Transistor", IEEE International Conference on VLSI Design, Kolkata, India, Jan C. Yadav, J. P. Duarte, S. Khandelwal, A. Agarwal, C. Hu, and Y. S. Chauhan, "Capacitance Modeling in III-V FinFETs", IEEE Transactions on Electron Devices, Vol. 62, Issue 11, Nov S. Khandelwal, J. P. Duarte, A. Medury, Y. S. Chauhan, S. Salahuddin, and C. Hu, "Modeling SiGe FinFETs with Thin Fin and Current Dependent Source/Drain Resistance", IEEE Electron Device Letters, Vol. 36, Issue 7, July C. Yadav, A. Agarwal, and Y. S. Chauhan, "Compact Modeling of Charge Density and Capacitance in III-V channel Double Gate FETs", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec A. Dasgupta, A. Agarwal, and Y. S. Chauhan, "Compact Model for charge centroid in III-V FETs", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec A. Dasgupta, A. Agarwal, and Y. S. Chauhan, "Compact Modeling of Quasi-Ballistic transport in FETs", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec T. Dutta, M. Agrawal, A. Agarwal and Y. S. Chauhan, "Wavefunction Penetration Effects in Extremely Scaled III-V MOSFETs", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec J. P. Duarte, S. Khandelwal, A. Medury, C. Hu, P. Kushwaha, H. Agarwal, A. Dasgupta, and Y. S. Chauhan "BSIM-CMG: Standard FinFET Compact Model for Advanced Circuit Design", IEEE European Solid-State Circuit Conference (ESSCIRC), Graz, Austria, Sept (Invited) C. Yadav, A. Agarwal, Y. S. Chauhan, "Simulation study of gate capacitance with back bias effects in III-V UTB devices", SRC TECHCON, Austin, USA, September S. Khandelwal, J. P. Duarte, A. Medury, Y. S. Chauhan, and C. Hu, "New Industry Standard FinFET Compact Model for Future Technology Nodes", IEEE VLSI Technology symposium, Kyoto, June C. Yadav, P. Kushwaha, S. Khandelwal, J. P. Duarte, Y. S. Chauhan, and C. Hu, "Modeling of GaN based Normally-off FinFET", IEEE Electron Device Letters, Vol. 35, Issue 6, June S. Khandelwal, J. P. Duarte, Y. S. Chauhan, and C. Hu, "Modeling 20nm Germanium FinFET with the Industry Standard FinFET Model", IEEE Electron Device Letters, Vol. 35, Issue 7, July C. Yadav, P. Kushwaha, H. Agarwal, and Y. S. Chauhan, "Threshold Voltage Modeling of GaN Based Normally-Off Tri-gate Transistor", IEEE India Conference (INDICON), Pune, India, Dec A. Dasgupta, C. Yadav, P. Rastogi, A. Agarwal, and Y. S. Chauhan, "Analysis and Modeling of Quantum Capacitance in III-V Transistors", IEEE International Conference on Emerging Electronics (ICEE), Bangalore, India, Dec (Best Poster Award) S. Khandelwal, J. P. Duarte, N. Paydavosi, Y. S. Chauhan, J. J. Gu, M. Si, P. D. Ye, and C. Hu, "InGaAs FinFET Modeling Using Industry Standard Compact Model BSIM-CMG", Workshop on Compact Modeling (WCM), Washington D.C., USA, June N. Paydavosi, S. Venugopalan, Y. S. Chauhan, J. P. Duarte, S. Jandhyala, A. M. Niknejad, and C. Hu, "BSIM - SPICE Models Enable FinFET and UTB IC Designs", IEEE Access, May Y. S. Chauhan, S. Venugopalan, N. Paydavosi, P. Kushwaha, S. Jandhyala, J. P. Duarte, S. Agnihotri, C. Yadav, H. Agarwal, A. Niknejad, and C. Hu, "BSIM Compact MOSFET Models for SPICE Simulation", IEEE International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), Gdynia, Poland, June (Invited) Y. S. Chauhan, S. Venugopalan, M. A. Karim, S. Khandelwal, N. Paydavosi, P. Thakur, A. M. Niknejad, and C. C. Hu, "BSIM - Industry Standard Compact MOSFET Models", IEEE European Solid-State Device Research Conference (ESSDERC), Bordeaux, France, Sept (Invited) Yogesh S. Chauhan, IIT Kanpur 53

A Multi-Gate CMOS Compact Model BSIMMG

A Multi-Gate CMOS Compact Model BSIMMG Darsen Lu, Sriramkumar Venugopalan, Tanvir Morshed, Yogesh Singh Chauhan, Chung-Hsun Lin, Mohan Dunga, Ali Niknejad and Chenming Hu University of California, Berkeley