Negative Capacitance MOSFETs for Future Technology Nodes

Transcription

1 Negative Capacitance MOSFETs for Future Technology Nodes Yogesh Singh Chauhan Nanolab, Department of Electrical Engineering IIT Kanpur, India Homepage

2 My Group and Nanolab Current members 30 Postdoc 5 Ph.D. 17 Three PhD graduated Postdocs in UC Berkeley and U. Bordeaux France Books 1 1 Journal Conference Device Characterization Lab - Pulsed IV/RF - PNA-X 43.5GHz - High Power IV 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 2

3 Joint Development & Collaboration 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 3

4 Outline MOSFET and Scaling Negative Capacitance and Transistor Modeling of NC-FinFET Impact of Material Parameters Switching Delay and Energy Conclusion 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 4

5 Outline MOSFET and Scaling Negative Capacitance and Transistor Modeling of NC-FinFET Impact of Material Parameters Switching Delay and Energy Conclusion 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 5

6 Transistor The Driving Force MOSFET is a transistor used for switching electronic signals. Gate V I OFF Switch vs. MOSFET I Switch ON V GS OFF Drain Source 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 6 I DS I DS MOSFET ON V GS Desired - High I ON - Low I OFF

7 Bulk MOSFET Drain current in MOSFET (ON operation) II OOOO = μμ WW LL CC oooo VV DDDD VV TTTT 2 Drain current in MOSFET (OFF operation) II OOOOOO 10 VV GGGG VV TTTT SS C ox =ε ox /t ox =oxide cap. S Subthreshold slope High I ON ( L, Cox, V DD -V TH ) Low I OFF ( V TH, S) 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 7

8 Technology Scaling Each time the minimum line width is reduced, we say that a new technology node is introduced. Example: 90 nm, 65 nm, 45 nm Numbers refer to the minimum metal line width. Poly-Si gate length may be even smaller. 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 8

9 Technology Scaling Scaling At each new node, all geometrical features are reduced in size to 70% of the previous node. Reward Reduction of circuit size by half. (~50% reduction in area, i.e., = 0.49.) Twice number of circuits on each wafer Cost per circuit is reduced significantly. Ultimately Scaling drives down the cost of ICs. 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 9

10 Scaling and Moore s Law Number of components per IC function will double every two years April 19, 1965 (Electronics Magazine) Shorthand for rapid technological change! Still working! 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 10 Source:

11 Moore s Law It s not technology! It s economy. Ways to Huge Profits High performance and Low Cost Achieved by making everything SMALLER 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 11

12 Scaling Overview B. Tox :Scale oxide thickness C. Wdep: Increase doping 1.High scattering Scale l d with L for better SCE A. Xj :Shallow junctions 2.Poor Subthreshold Slope Channel encroachment proportional to X j Ohguro, 11/09/2017 et al., ULSI Science and Technology 1997 Gate current increases as T ox is reduced Yeo et.al, IEEE TED, Vol.50, 2003 High I OFF 3.Large junction capacitance Limit circuit speed Other Issues 1- Random Dopant Fluctuation 2- Increased Effective T ox (Quantum Mechanical Effect) 3- Polysilicon Gate Depletion Tsividis, 3 rd Edition, 2011 Yogesh S. Chauhan, IIT Kanpur 12

13 Scaling and Innovations Scaling For : Cost, Speed and Power New technology node every two year Channel length reduction ~30% Area reduction ~50% 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 13 C. Hu, Modern Semiconductor Devices for ICs

14 Technology Trend Technology Product Performance Source : 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 14

15 Scaling Issues/Challenges V TH not following scaling Current Scaling Mobility is not constant Velocity Saturation Higher I off Parasitic resistance and capacitance don t scale linearly Process variations Affordable Litography Heat dissipation and Cooling 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 15

16 IC industry for >40 years Closer distance between elements Pitch Faster signal transfer and processing rate For the same Chip size (or cost), more functionality Use less energy (or power) for same function In the last 45 years since 1965 Price of memory/logic gates has dropped 100 million times. Miniaturization is key to the improvements in speed and power consumption of ICs. 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 16

17 Why divorce after 40 years? C g Gate Oxide Source Drain Q G = Q i +Q b Charge sharing Body 11/09/2017 Courtesy: Chenming Hu Yogesh S. Chauhan, IIT Kanpur 17

18 Threshold Voltage Roll-Off Energy band diagram from source to drain when Vgs=0V and Vgs=Vt. A-b long channel; c-d short channel. Vt decreases at very small Lg. It determines the minimum acceptable Lg because Ioff is too large when Vt becomes too low or too sensitive to Lg. 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 18 Ref. Modern Semiconductor Devices for Integrated Circuits by Chenming C. Hu

19 Short Channel Effects Gate C g Oxide Source Drain C d 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 19

20 Making Oxide Thin is Not Enough Gate Source Drain Leakage Path Gate cannot control the leakage current paths that are far from the gate. 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 20

21 Leakage current in MOSFET Ref. Y.-K. Lin et. al., Modeling of Subsurface Leakage Current in Low VTH Short Channel MOSFET at Accumulation Bias, IEEE TED /09/2017 Yogesh S. Chauhan, IIT Kanpur 21

22 MOSFET in sub-22nm era FinFET FDSOI 11/09/2017 NY Times Yogesh S. Chauhan, IIT Kanpur 22 SOITEC

23 Eliminate Si Far from Gate Thin body controlled By multiple gates. Gate Length Gate Length Source Gate Drain Source Gate FinFET body is a thin Fin. Drain Fin Height Fin Width N. Lindert et al., DRC paper II.A.6, /09/2017 Yogesh S. Chauhan, IIT Kanpur 23

24 Challenges & Solutions Power challenge II OOOO = μμ WW LL CC oooo VV DDDD VV TTTT 2 II OOOOOO 10 VV GGGG VV TTTT SS Scaling both the V DD and V T maintains same performance (I ON ) by keeping the overdrive (V DD - V T ) constant. 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 24 Adrian Ionescu et al., Nature 2011

25 Spectrum of Approaches to Analyzing Electronic System 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 25

26 Compact Modeling or SPICE Modeling Medium of information exchange Good model should be Accurate: Trustworthy simulations. Simple: Easy Parameter extraction. Balance between accuracy and simplicity depends on end application Excellent Convergence Simulation Time ~µsec Accuracy requirements ~ 1% RMS error after fitting Example: BSIM6, BSIM- CMG 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 26

27 Compact Model is Art Based on Science Output Conductance Current Saturation Quantization Gate Current GIDL Current Impact Ionization Current Noise models Mobility and Transport S/D Resistance Gate Resistance Short Channel Effects Core Overlap Capacitances Fringe Capacitances Inversion Layer Thickness Non-Quasi-Static Effects Substrate RC Network Parasitic Diode, BJT Self Heating Temperature Effects Proximity Effects Random Variations Y. S. Chauhan et.al., BSIM6: Analog and RF Compact Model for Bulk MOSFET, IEEE TED, /09/2017 Yogesh S. Chauhan, IIT Kanpur 27

28 BSIM Family of Compact Device Models BSIM1,2 BSIM3 BSIM4 Conventional MOSFET BSIM5 New BSIM6 BSIMSOI Silicon on Insulator MOSFET 11/09/2017 BSIM-CMG BSIM-IMG Multi-Gate MOSFET BSIM: Berkeley Short-channel IGFET Model Yogesh S. Chauhan, IIT Kanpur 28

29 Outline MOSFET and Scaling Negative Capacitance and Transistor Modeling of NC-FinFET Impact of Material Parameters Switching Delay and Energy Conclusion 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 29

30 Subthreshold Swing Amount of gate voltage required to change the current by 1-decade. C ins S = d dv GS ( log I ) ds SS = VV GG log 10 II DD = VV GG ψψ SS = 1 + CC SS CC iiiiii ψψ SS log 10 II DD. 60mV/decade As 11 + CC SS CC iiiiii 11, SS /dddddddddddd 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 30

31 Capacitance Definition In general, insulator can be a non-linear dielectric whose capacitance density (per unit volume) can be defined as Definition 1: CC iiiiii = 2 1 GG = inverse curvature of free energy density PP 2 Definition 2: CC iiiiii = = slope of the polarization vs electric field curve where PP = Polarization in dielectric, GG = Free energy density and EE = Externally applied electric field Two types of non-linear dielectrics: Paraelectric : No polarization when electric field is removed. Ferroelectric : Two possible states of polarization when electric field is removed. 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 31

32 Negative Capacitance Transistor What if insulator has a Negative Capacitance! CC iiiiii < 0 and CC SS CC iiiiii < 0, then 1 + CC SS CC iiiiii For a linear capacitor Energy GG = QQ2 < 1 SS < 60mV/decade Capacitance CC = 1 2CC dd 2 GG = 1/CCCCCCCCCCCCCCCCCC ddqq The same holds also for a non-linear capacitor. 2 G Energy landscape of ferroelectric materials. 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 32 Ref. S. Salahuddin et. al., Nano Letters, QQ = εεεε + PP PP

33 Landau-Khalatnikov Theory of Non- Linear Dielectrics Free energy of a non-linear dielectric is given as GG = αpp 2 + ββpp 4 + γγpp 6 EEEE In general, αα and ββ can be +ve or ve but γγ is always +ve for stability reasons. δ = Polarization damping factor Dynamics of G is given by δδ dddd dddd = In the steady state, dddd dddd = 0 EE = 2αPP + 4ββPP3 + 6γγPP 5 For α > 0 and at EE = 0, there exit only one real root PP = 0 A Paraelectric Material For α < 0 and at EE = 0, there exit three real roots PP = 0, ± PP rr where PP rr = ββ 2 3αααα ββ A Ferroelectric Material has a non-zero P at zero E. 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 33 3γγ

34 Positive and Negative Capacitances Three possible solutions at EE = 0 Only one solution at EE = 0 PP = 0 is not possible in a isolated Ferroelectric due to maxima of energy or a negative capacitance CC iiiiii = 2 GG PP 2 1 = < 0 Paraelectric A Positive Capacitor Ferroelectric A Conditionally Negative Capacitor 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 34

35 Negative Capacitance in Ferroelectric P r CC iiiiii = CC ffff -ve slope region can be stabilized if -E c E c CC GGGG = 1 CC ffff + 1 CC SS 1 > 0 or, CC ffff > CC SS -P r S. Salahuddin and S. Datta, Use of negative capacitance to provide voltage amplification for low power nanoscale devices, Nano Letters, vol. 8, no. 2, pp , /09/2017 Yogesh S. Chauhan, IIT Kanpur 35

36 How to stabilize a Negative Capacitance? Add a positive dielectric capacitance in series such that total free energy of system has a minima in the negative capacitance regime of ferroelectric. 1 = > 0 CC tttttt CC FFFF CC DDDD CC DDDD < CC FFFF and CC FFFF < 0 CC tttttt = CC DDDD. CC FFEE CC FFEE CC DDDD > 0 A. I. Khan et al., APL, vol. 99, no. 11, p , /09/2017 Yogesh S. Chauhan, IIT Kanpur 36

37 Ferroelectric-Dielectric Systems A. I. Khan et al., APL, vol. 99, no. 11, p , D. J. Appleby et al., Nano Letters, vol. 14, no.7, pp , Total Capacitance of Ferroelectric-dielectric hetro-structure becomes greater than the dielectric capacitance. CC tttttt = CC DDDD. CC FFFF CC FFFF CC DDDD > 0 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 37

38 Negative Capacitance FETs PbZr 0.52 Ti 0.48 O3 FE with HfO 2 buffer interlayer P(VDF TrFE 0.25 ) Organic Polymer FE HfZrO FE CMOS compatible FE S. Dasgupta et al., IEEE JESCDC, J. Jo et al., Nano Letters, 2015 K.-S. Li et al., in IEEE IEDM, /09/2017 Yogesh S. Chauhan, IIT Kanpur 38

39 Outline MOSFET and Scaling Negative Capacitance and Transistor Modeling of NC-FinFET Impact of Material Parameters Switching Delay and Energy Conclusion 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 39

40 Device Structure Metal-ferroelectric-Metal-Insulator-Semiconductor (MFMIS) Metal internal gate provides an equipotential surface with a spatially constant V int. Simplifies modeling as ferroelectric and baseline MOSFET can be considered as two separate circuit entities connected by a wire. 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 40

41 Experimental Calibration of L-K Model Calibration of L-K with P-V fe curve for Y- HfO2 with 3.6 mol% content of YO 1.5 [3] α = m/f ββ = m/f γγ = 0 (2 nd order phase transition) [3] J. M uller et al., JAP, vol. 110, no. 11, pp , Gibb s Energy, GG = αpp 2 + ββpp 4 + γγpp 6 EEEE Dynamics of G is given by δδ ddpp ddtt = In the steady state, dddd dddd = 0 EE = VV ffff = 2αPP + 4ββPP 3 + 6γγPP 5 tt ffff PP = QQ εεee QQ (Gate Charge) [1] Devonshire et al., The London, Edinburgh, and Dublin Philosophical Magazine and Journal of Science, vol. 40, no. 309, pp , [2] Landau, L. D. & Khalatnikov, I. M. On the anomalous absorption of sound near a second order phase transition point. Dokl. Akad. Nauk 96, (1954). 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 41

42 Calibration of Baseline FinFET Calibration of baseline FinFET with 22 nm node FinFET. BSIM-CMG model is used to model baseline FinFET. Gate length (L) = 30nm, Fin height (Hfin) = 34nm Fin thickness (Tfin) = 8nm C. Auth et al., in VLSIT, 2012, pp /09/2017 Yogesh S. Chauhan, IIT Kanpur 42

43 Complete Modeling Flowchart VV GG EE = VV ffff tt ffff = 2αPP + 4ββPP 3 + 6γγPP 5 PP = QQ εεee QQ (Gate Charge) Landau-Khalatnikov Model of ferroelectric Verilog-A Code VV iiiiii = VV GG VV ffff QQ GG BSIM-CMG Model of FinFET Verilog-A Code 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 43 II DD

44 Outline MOSFET and Scaling Negative Capacitance and Transistor Modeling of NC-FinFET Impact of Material Parameters Impact of ferroelectric thickness Ferroelectric Parameters Variation Switching Delay and Energy Conclusion 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 44

45 Capacitances and Voltage Amplification EE = VV ffff tt ffff = 2αPP + 4ββPP 3 + 6γγPP 5 VV ffff = tt ffff 2αPP + 4ββPP 3 + 6γγPP 5 CC ffff = VV ffff = 1 = 1 + CC iiiiii CC oooo 1 tt ffff 2αα + 12ββQQ γγQQ 4 1 CC SS + CC DDDDDDDDDD + CC SSoooooooooo Internal Voltage Gain, Capacitance matching between C fe and C int increases the gain. AA VV = VV iiiiii VV GG = CC ffff CC ffff CC iiiiii 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 45

46 Capacitance Matching Capacitance matching increases with t fe which increases the gain. Hysteresis appears for C fe < Cint which is region of instability. Increase in V D reduces the capacitance matching Reduces gain. Reduces width of hysteresis window. 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 46

47 I D -V G Characteristics SS region As t fe increases Capacitance matching is better C S and C ins are better matched SS = 1 CC SS CC iiiiii. 60mV/dec As t fe SS 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 47

48 I D -V G Characteristics ON region As t fe increases Capacitance matching is better AA VV = VV iiiiii VV GG = CC ffff CC ffff CC iiiiii As gain increases, I ON increases. Note the significant improvement in I ON compared to SS. 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 48

49 I D -V D Characteristics FE material is different. NCFET is biased in negative capacitance region. Q G or P is positive V fe is negative. V DS Q G or P V fe V int =V G + V fe A V Current reduces G. Pahwa,, Y. S. Chauhan, Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance, IEEE TED, Dec /09/2017 Yogesh S. Chauhan, IIT Kanpur 49

50 I D -V G Characteristics High V DS Hysteresis appears for C fe < C int which is the region of instability. As t fe increases SS reduces, I ON increases. I OFF reduces for high V D. Width of hysteresis at larger thicknesses can be controlled with V D. 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 50

51 Negative DIBL V D reduces Q G which, in turn reduces VV iiiiii = VV GG VV ffff in the negative capacitance region. Negative DIBL increases with t fe due to increased V fe drop. V th increases with V D instead of decreasing. Higher I ON still lower I OFF! 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 51

52 Optimum NC-FinFET Same I ON as 22 nm node FinFET. Steeper SS of 58.2 mv/decade. V DD reduction by 0.4 V. I OFF reduction by 83 %. 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 52

53 Ferroelectric Parameters Variation If γγ = 0, α = 3 3EE cc ββ = 3 3EE Low P r and high E c cc reduce C fe which leads to PP 3 rr PP rr improved capacitance matching PP rr = Remnant Polarization and hence, a high gain. EE cc = Coercive Field Low SS 1 increase I CC ffff = ON but reduce I OFF due to a tt ffff 2αα + 12ββQQ 2 more negative DIBL high I ON /I OFF. 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 53 D. Ricinschi et al., JPCM, vol. 10, no. 2, p. 477, 1998.

54 Outline MOSFET and Scaling Negative Capacitance and Transistor Modeling of NC-FinFET Impact of Material Parameters Switching Delay and Energy Conclusion 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 54

55 Intrinsic Delay Delay, τ = ΔQQ GG II OOOO ΔQQ GG = QQ GG VV GG = VV DD = VV DDDD QQ GG VV GG = 0, VV DD = VV DDDD NC-FinFET driving NC-FinFET For high V DD, high I ON advantage is limited by large amount of ΔQQ GG to be driven. Outperforms FinFET at low V DD. Minimum at VV DDDD 0.28 V corresponds to a sharp transition in Q G. NC-FinFET driving FinFET load provides full advantage of NC-FinFET. 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 55

56 Power and Energy Delay Products PPPPPP = ΔQQ GG. VV DDDD EEDDDD = ΔQQ GG 2 VV DDDD II OOOO NC-FinFET driving NC-FinFET shows advantage only for low V DD. NC-FinFET driving FinFET load is the optimum choice. 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 56

57 Modeling of MFIS NCFET Contrast with MFIMS structure: P and V int vary spatially in longitudinal direction Better stability w.r.t. Leaky ferroelectric and domain formation Issues with Existing Models [1,2] : Implicit equations tedious iterative numerical solutions [1] H.-P. Chen, V. C. Lee, A. Ohoka, J. Xiang, and Y. Taur, Modeling and design of ferroelectric MOSFETs, IEEE Trans. Electron Devices, vol. 58, no. 8, pp , Aug [2] D. Jiménez, E. Miranda, and A. Godoy, Analytic model for the surface potential and drain current in negative capacitance field-effect transistors, IEEE Trans. Electron Devices, vol. 57, no. 10, pp , Oct /09/2017 Yogesh S. Chauhan, IIT Kanpur 58 58

58 Explicit Modeling of Charge Voltage Balance: Implicit equation in Goal: Explicit Model with good initial guesses for each region of NCFET operation Both the Q G and its derivatives match well with implicit model G. Pahwa, T. Dutta, A. Agarwal and Y. S. Chauhan, "Compact Model for Ferroelectric Negative Capacitance Transistor With MFIS Structure," in IEEE Transactions on Electron Devices, March /09/2017 Yogesh S. Chauhan, IIT Kanpur 59

59 Drain Current Model Validation Against Full Implicit Calculations Against Experimental Data G. Pahwa, T. Dutta, A. Agarwal and Y. S. Chauhan, "Compact Model for Ferroelectric Negative Capacitance Transistor With MFIS Structure," IEEE Transactions on Electron Devices, March [1] M. H. Lee et al., in IEDM Tech. Dig., Dec. 2016, pp [2] M. H. Lee et al., in IEDM Tech. Dig., Dec. 2015, pp /09/2017 Yogesh S. Chauhan, IIT Kanpur 60 60

60 MFIS Vs MFMIS MFIS excels MFMIS for low P r ferroelectrics only. A smooth hysteresis behavior in MFIS compared to MFMIS. MFIS is more prone to hysteresis exhibits hysteresis at lower thicknesses compared to MFMIS. G. Pahwa, T. Dutta, A. Agarwal, and Y. S. Chauhan, "Physical Insights on Negative Capacitance Transistors in Non-Hysteresis and Hysteresis Regimes: MFMIS vs MFIS Structures", accepted in IEEE Transactions on Electron Devices, /09/2017 Yogesh S. Chauhan, IIT Kanpur 61

61 NC-FinFET based inverters Although the transistor characteristics show no Hysteresis, the VTCs of NC-FinFET inverters can still exhibit it due to the NDR region in the output characteristics. T. Dutta, G. Pahwa, A. R. Trivedi, S. Sinha, A. Agarwal, and Y. S. Chauhan, "Performance Evaluation of 7 nm Node Negative Capacitance FinFET based SRAM", IEEE Electron Device Letters, Aug /09/2017 Yogesh S. Chauhan, IIT Kanpur 62

62 NC-FinFET based SRAM Read time: reduced due to the increased drive current Write time: slower due to the gate capacitance enhancement P avg : NC-SRAM performs better with lower standby leakage only at small t fe, taking advantage of the lower subthreshold currents T. Dutta, G. Pahwa, A. R. Trivedi, S. Sinha, A. Agarwal, and Y. S. Chauhan, "Performance Evaluation of 7 nm Node Negative Capacitance FinFET based SRAM", IEEE Electron Device Letters, Aug /09/2017 Yogesh S. Chauhan, IIT Kanpur 63

63 Impact of Process Variations Variability in I ON, I OFF, and V t due to combined impact of variability in L g, T fin, H fin, EOT, t fe, E c, and P r I ON : Improvement is non-monotonic with t fe I OFF : Decreases monotonically with t fe V t : Decreases monotonically with t fe T. Dutta, G. Pahwa, A. Agarwal, and Y. S. Chauhan, "Impact of Process Variations on Negative Capacitance FinFET Devices and Circuits", accepted in IEEE Electron Device Letters, /09/2017 Yogesh S. Chauhan, IIT Kanpur 64

64 Process Variation in Ring Oscillator The overall average delay variability in NC-FinFET based RO is lesser compared to the reference RO. The improvement is non-monotonic with nominal FE thickness scaling. 11-stage Ring-Oscillator: Variation in τ due to combined variation T. Dutta, G. Pahwa, A. Agarwal, and Y. S. Chauhan, "Impact of Process Variations on Negative Capacitance FinFET Devices and Circuits", accepted in IEEE Electron Device Letters, /09/2017 Yogesh S. Chauhan, IIT Kanpur 65

65 Conclusion Maintaining I ON /I OFF is the biggest challenge in new technology nodes Negative capacitance FET is one of the best choice Need to find sweet material (HfZrO 2 ) Integration in conventional CMOS process remains a challenge (lot of progress) Speed/Switching need more research 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 66

66 Relevant Publications G. Pahwa, T. Dutta, A. Agarwal, and Y. S. Chauhan, "Physical Insights on Negative Capacitance Transistors in Non-Hysteresis and Hysteresis Regimes: MFMIS vs MFIS Structures", accepted in IEEE Transactions on Electron Devices, T. Dutta, G. Pahwa, A. Agarwal, and Y. S. Chauhan, "Impact of Process Variations on Negative Capacitance FinFET Devices and Circuits", accepted in IEEE Electron Device Letters, T. Dutta, G. Pahwa, A. R. Trivedi, S. Sinha, A. Agarwal, and Y. S. Chauhan, "Performance Evaluation of 7 nm Node Negative Capacitance FinFET based SRAM", IEEE Electron Device Letters, Aug G. Pahwa, T. Dutta, A. Agarwal, and Y. S. Chauhan, "Compact Model for Ferroelectric Negative Capacitance Transistor with MFIS Structure", IEEE Transactions on Electron Devices, Mar G. Pahwa,, and Y. S. Chauhan, "Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance - Part I, Model description", IEEE Transactions on Electron Devices, Dec G. Pahwa,, and Y. S. Chauhan, "Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance - Part II, Model validation", IEEE Transactions on Electron Devices, Dec G. Pahwa, T. Dutta, A. Agarwal, and Y. S. Chauhan, "Energy-Delay Tradeoffs in Negative Capacitance FinFET based CMOS Circuits", IEEE ICEE, Dec (Best Paper Award) G. Pahwa, T. Dutta, A. Agarwal, and Y. S. Chauhan, "Designing Energy Efficient and Hysteresis Free Negative Capacitance FinFET with Negative DIBL and 3.5X ION using Compact Modeling Approach", IEEE ESSDERC, Switzerland, Sept (Invited) 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 67

67 Thank You 11/09/2017 Yogesh S. Chauhan, IIT Kanpur 68