CORE COMPACT MODELS FOR SYMMETRIC MULTI-GATE FERROELECTRIC FIELD EFFECT TRANSISTORS

Transcription

1 CORE COMPACT MODELS FOR SYMMETRIC MULTI-GATE FERROELECTRIC FIELD EFFECT TRANSISTORS Thesis submitted in partial fulfillment of the requirements for the degree of Masters of Science in Electronics and Communication Engineering by Research by MULAKA HARANADHA REDDY CENTER FOR VLSI AND EMBEDDED SYSTEMS TECHNOLOGY International Institute of Information Technology Hyderabad , INDIA JULY 2018

2 Copyright MULAKA HARANADHA REDDY, 2018 All Rights Reserved

3 International Institute of Information Technology Hyderabad, India CERTIFICATE It is certified that the work contained in this thesis, titled CORE COMPACT MODELS FOR SYM- METRIC MULTI-GATE FERROELECTRIC FIELD EFFECT TRANSISTORS by MULAKA HARANADHA REDDY, has been carried out under my supervision and is not submitted elsewhere for a degree. Date Adviser: Prof. Srivatsava Jandhyala.

4 To my family and friends

5 Acknowledgments This thesis would not have been possible without the support of many individuals. I would like to extend my gratitude to all of them. Foremost, I express my thanks and gratitude to my thesis advisor Dr. Srivatsava Jandhyala for his continuous advice he provided me throughout the course of my work. Without his motivation and support, it would have not been possible for me to continue my work till the final stages. I would not have submitted this thesis if not for his immense patience with me. I am thankful to everyone in CVEST for providing such a positive work environment. Many thanks to Anand, Soumya, Sunil, Prateek, Gopi, Bhuvanan for all the help, discussions, study group sessions and support. I cannot forget to mention my friends Viswanadh, Surendra Reddy, Nageswara Rao, Koteswara Rao, Vinay for remaining by my side rock steady throughout this journey and for being my friends through my ups and downs. I could not have accomplished it without the support and understanding of my parents. I wish to thank my Mom, Dad and my brother Naveen for being my constant support and motivation. Last, but not the least, thanks to IIIT community for giving me such a beautiful campus and environment to grow. v

6 Abstract The integration density achievable in Complementary Metal-Oxide-Semiconductor (CMOS) technology is limited by the leakage power seen in nanoscale transistors. Efforts to overcome the bottlenecks of power dissipation set by classical Boltzmann physics, resulted in exploration of new transistor architectures having novel transport mechanisms in channel. Ferroelectric FETs use the negative capacitance phenomenon to achieve low subthreshold slopes and have good potential to replace the classical Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). The transport mechanism of the channel remains unmodified and these novel transistors are fabricated by depositing a ferroelectric material on top of the gate oxide of a conventional transistors. The subthreshold slope (SS) in a ferroelectric device can go below the Boltzmann limit of 60 mv/dec, resulting in low leakage power in FeFET devices. Further, the current boosting observed in these transistors around the threshold region, aids in improving the speed of operation of these devices. In this thesis, we present hysteresis free operation conditions for Ferroelectric FETs, and derive the core compact models of Symmetric Double-Gate Ferroelectric Field Effect Transistors (SDG-FeFET) and Pillar Gate ferroelectric Field Effect Transistors (Pillar-FeFET). The quasi-static terminal-charge models proposed are shown to match very well with exact numerical terminal charge integrals, for all bias conditions and across various device parmeters. The proposed models are integrated into a professional SPICE simulators using the Verilog-A interface. Different combinational, sequential and SRAM circuits are built using SDG-FeFET and Pillar-FeFET transistors and improvement in their switching behavior is demonstrated through SPICE simulations.. vi

7 Abbreviations ɛ ox ɛ si ψ s ψ s C dep C fe C g C Mos C ox E ext I ds I off I on n i Q D Q G Q id Q is Q S T c oxide Permittivity silicon Permittivity electrostatic surface potential at drain end electrostatic surface potential at source end depletion capacitance Ferroelectric capacitance per unit area Gate capacitance per unit area MOSFET capacitance oxide capacitance External electric field drain current OFF current ON current intrinsic carrier density Drain terminal charge Gate terminal charge inversion charge at drain end inversion charge at source end Source terminal charge Curie temperature vii

8 viii t ox t si V d V fb V F E V g V ox 6T-SRAM BL BLB C CMOS CPU CR DG-MOSFET DIBL EOT FA FDSOI GIDL IMOS IOT IVE k L thickness of oxide layer thickness of silicon drain voltage flat band voltage voltage across ferroelectric layer gate voltage voltage across oxide layer 6 Transistor-Static Random Access Memory Bit Line Bit Line Bar Capacitance Complementary Metal-Oxide-Semiconductor Central Processing Unit Cell Ratio Double Gate-MOSFET Drain Induced Barrier Lowering equivalent oxide thickness Full Adder Fully Depleted Silicon On Insulator Gate Induced Drain Lowering Impact Ionization Metal Oxide Semiconductor transistors Internet Of Things Input Voltage equation Boltzmann s constant channel length

9 ix LK NC-FET NLF nmosfet P Pillar-FeFET Pillar-FET PZT q R SBT SCE SDG-FeFETs SDG-FET SNM SS T TFET U VTC W WL Landau-Khalatnikow Negative Capacitance-FET Nonlinearity factor n-channel MOSFET Polarization Pillar Gate ferroelectric Field Effect Transistors Pillar Gate Field Effect Transistor Lead Zirconate Titanate electron charge radius Strontium Bismuth Titanate Short Channel Effects Symmetric Double-Gate Ferroelectric Field Effect Transistors Symmetric Double-Gate Field Effect Transistors Static Noise Margins Subthreshold Swing Temperature Tunneling Field Effect Transistors Gibb s free energy Voltage Transfer Curves width Word Line

10 Contents Chapter Page 1 Introduction Introduction to VLSI and the key challenge Problems of Scaling in Conventional MOSFETs Advantages Multi-Gate MOSFETs and their Structures The Power Dissipation Bottleneck for CMOS Technology nodes Alternatives to get both scaling and power benefits Negative Capacitance Ferroelectric Conventional MOSFET with Ferroelectric Compact Modeling Scope and organization of the thesis Modeling of long channel Symmetric Double Gate Ferroelectric Field Effect Transistor (SDG- FeFET) Introduction Surface potential for SDG-FeFET Drain current equation for Symmetric Double-Gate Ferroelectric Field Effect Transistors Quasi-static Terminal Charge Model for Symmetric Double-Gate Ferroelectric Field Effect Transistors Summary Circuit applications using Symmetric Double Gate Ferroelectric Field Effect Transistor (SDG- FeFET) Introduction Digital Circuits Inverter Stage Ring oscillator All basic gates Full Adder bit Ripple Carry Adder Sequential Circuits T-SRAM CELL Read SNM variation with supply voltage: Write SNM variation with supply voltage: Read SNM variation with cell ratio (CR): x

11 CONTENTS xi Read SNM variation with Word line voltage variation: Write time with supply voltage variation: Read access time with supply voltage variation: Summary Modeling of long channel Pillar Gate Ferroelectric Field Effect Transistor (Pillar-FeFET) Introduction Surface potential for Pillar-FeFET Drain current equation for Pillar Gate Ferroelectric Field Effect Transistors Quasi-static Terminal Charge Model for Pillar Gate Ferroelectric Field Effect Transistors Circuit simulation for Pillar-Ferroelectric Field Effect Transistors Inverter DC and Transient simulations stage ring Oscillator Summary Conclusion Conclusion Future work Bibliography

12 List of Figures Figure Page 1.1 Different types of Multi-gate MOSFETs [1] The projected energy consumption of data centers [2]. Carbon emissions of data centers [3] (a)the evolution of CMOS power supply and half-pitch over the 20 years [4] (b) the evolution of CPU Power Density (c) and microprocessor clock frequency. [5][5] Comparison of Novel FET and conventional MOSFET (a) Energy landscape and charge versus voltage for positive capacitor (b) Energy landscape and charge versus voltage for Negative capacitor Energy well diagram of ferroelectric material. The region under dashed lines indicates the negative capacitance region Charge or polarization vs voltage characteristics of a ferroelectric material. Here negative capacitance is represented by dotted line. [1] Ferroelectric Hysteresis plotted as polarization vs. electric field Polarization-voltage hysteresis characteristics of a ferroelectric capacitor. The energy landscapes at different points on the hysteresis curves [1] Stabilization of ferroelectric negative capacitance using positive capacitance [1] (a) Negative capacitance MOSFET and (b) its equivalent capacitors A compact model is formed from a core model (long-channel) and different real-device models Structure of SDG-FeFET Variation of f (β) with β for SBT at different and t ox = 1nm, t si = 10nm Variation of f (β) with β for PZT at different and t ox = 1nm,t si = 10nm (a) Voltage across Ferroelectric (V fe ), voltage across oxide layer (V ox ), surface potential (ψ s ) variation with gate voltage for two different materials (solid lines indicates for PZT and dashed lines indicate SBT material). (b) Inversion charge variation with gate voltage for two different materials. (c) C fe variation with gate bias for two different materials. (d) C g variation with gate bias for two different materials Variation of C Mos, C ox, and C fe with gate voltage and comparison Variation of surface potential with gate voltage. Plots are made using t si =10 nm, =150 nm and t ox =1 nm Variation of surface potential with gate voltage for SDG-FeFET at differenrroelectric layer thickness. Plots are made using t si =10 nm, =150 nm and t ox =1 nm Variation of surface potential with gate voltage for SDG-FeFET at different oxide layer thickness. Plots are made using t si =10 nm, =150 nm and t ox =1 nm xii

13 LIST OF FIGURES xiii 2.9 Gate voltage versus Drain current of SDG-FeFET and SDG-FET at different drain voltages. Plots are made using t si =10 nm, W=1 µm, L=1 µm and t ox =1 nm Subthreshold Swing (SS) for SDG-FeFET and SDG-FET. Plots are made using t si =10 nm, =150 nm and t ox =1 nm Drain voltage versus drain current at different gate voltages for SDG-FeFET and SDG- FET. Plots are made using t si =10 nm, =150 nm and t ox =1 nm (a) Shows the non-linearity factor as a function of gate voltage at V ds =0.1 V and V ds =0.5 V (b) Shows the I ratio, which is magnitude of I d2 /I d1, where I d2 =4µC si (W/L)(2kT/q) 2 (G s G d ), and I d1 = I ds I d2 for different drain biases. For any V ds, the value of I ratio remains high only at low gate-bias implying that the contribution of G in I ds is significant only at low-gate bias. Plots are made using t si =10 nm, W=1 µm, L=1 µm for various devices (dev1: t ox =1 nm, =150 nm), (dev2: t ox =2 nm, =150 nm), (dev3: t ox =2 nm, =200 nm) (a), (b) are gate and drain terminal charges with change in gate voltage and (c), (d) are gate and drain terminal charges with change in drain voltage of the device calculated by exact numerical integrals (symbols) and by proposed model (lines). The device parameters are t ox =1nm, =150 nm, t si =10 nm Transcapacitances (a) C gg, (b) C dg with change in gate voltage and (c) C gd, (d) C dd with change in drain voltage of the device calculated by exact numerical integrals( symbols) and by proposed model (lines). The device parameters are =150 nm, t ox =1nm, t si =10 nm (a) circuit symbol for PMOS SDG-FET, SDG-FeFET (b) circuit symbol for NMOS SDG-FET, SDG-FeFET (a) Inverter circuit (b) circuit symbol Dc analysis of inverter using SDG-FET (solid lines) and SDG-FeFET (dotted lines) transistors with device parameters t ox = 1nm, = 150nm, t si = 10nm and considered mobility of both NMOS and PMOS transistors are same and is 300cm 2 /V-sec Transient analysis of inverter using SDG-FET (solid lines) and SDG-FeFET (dotted lines)transistors with device parameters t ox = 1nm, = 150nm, t si = 10nm and considered mobility of both NMOS and PMOS transistors are same and is 300cm 2 /Vsec Schematic view of Ring Oscillator (a) Simulated transient response of 15-stage ring-oscillator built using N &P- SDG- FeFETs has frequency of MHz and the same built with equivalent N &P - SDG- FETs has MHz. (b) Demonstration of match in frequency of ring-oscillator built with SDG-FeFETs operating at rail-to-rail voltage of 1 V with the one SDG-FETs having higher rail-to-rail voltage of 1.6 V. The W/L ratio of P-FET to N-FET is 3:1 in both SDG-FeFETs and equivalent SDG-FETs. Mobility of electrons and holes assumed in current calculation are 300 cm 2 /V-sec and 100 cm 2 /V-sec respectively. The device parameters used for SDG-FeFET are =150 nm, t ox =1nm, t si =10 nm Schematic view of all logic gates Transient analysis of all gates using SDG-FET (solid lines) and SDG-FeFET (dotted lines) transistors with device parameters t ox = 1nm, = 150nm, t si = 10nm and considered mobility of both NMOS and PMOS transistors are same and is 300cm 2 /Vsec

14 xiv LIST OF FIGURES 3.9 Schematic view of Full Adder Transient analysis of Full Adder using SDG-FET (solid lines) and SDG-FeFET (dotted lines) transistors with device parameters t ox = 1nm, = 150nm, t si = 10nm and considered mobility of both NMOS and PMOS transistors are same and is 300cm 2 /Vsec Schematic view of ripple carry adder Transient analysis of ripple carry adder using SDG-FET and SDG-FeFET transistors with device parameters t ox = 1nm, = 150nm, t si = 10nm and considered mobility of both NMOS and PMOS transistors are same and is 300cm 2 /V-sec Transient analysis of D flip flop using SDG-FET (solid lines) and SDG-FeFET (solid lines) transistors with device parameters t ox = 1nm, = 150nm, t si = 10nm and considered mobility of both NMOS and PMOS transistors are same and is 300cm 2 /Vsec Schematic view of Johnson s ring counter Transient analysis of 8-bit Johnson s ring counter using SDG-FET and SDG-FeFET transistors with device parameters t ox = 1nm, = 150nm, t si = 10nm and considered mobility of both NMOS and PMOS transistors are same and is 300cm 2 /V-sec T-SRAM cell The schematic of SRAM in read access mode for butterfly curve measurement The schematic of SRAM in write mode for butterfly curve measurement T-SRAM cell SNM Simulated results of 6T-SRAM cell designed with SDG-FETs and SDG-FeFETs Read SNM variation with power supply Write SNM variation with power supply SNM variation with Cell Ratio SNM variation with Word line Voltage Write time with power supply Read access time with power supply D view and cross sectional view of Pillar-FeFET (a) Variation of f(β) with β for SBT at different, t ox = 1nm, ɛ ox = 3.9 and R = 20nm (b) for SBT at different, t ox = 1nm, ɛ ox = 25 and R = 20nm (c) for PZT at different, t ox = 1nm, ɛ ox = 3.9 and R = 20nm (d) for PZT at different, t ox = 1nm, ɛ ox = 25 and R = 20nm (a) Comparison of inversion charge variation with gate voltage for Pillar-FeFET (solid line) and Pillar-FET (dashed line) with SBT material at = 135nm, t ox = 1nm, ɛ ox = 3.9, R = 20nm (b) Variation of inversion charge with gate voltage of Pillar- FeFET (SBT at = 135nm, t ox = 1nm, ɛ ox = 3.9, R = 20nm and PZT at = 350nm, t ox = 1nm, ɛ ox = 3.9, R = 20nm) (c) Variation of inversion charge with gate voltage of Pillar-FeFET (SBT at = 35nm, t ox = 1nm, ɛ ox = 25, R = 20nm and PZT at = 70nm, t ox = 1nm, ɛ ox = 25, R = 20nm)

15 LIST OF FIGURES xv 4.4 (a) Variation of C fe with gate voltage of Pillar-FeFET (SBT at = 135nm, t ox = 1nm, ɛ ox = 3.9, R = 20nm and PZT at = 350nm, t ox = 1nm, ɛ ox = 3.9, R = 20nm) (b) Variation of C g with gate voltage of Pillar-FeFET (SBT at = 135nm, t ox = 1nm, ɛ ox = 3.9, R = 20nm and PZT at = 350nm, t ox = 1nm, ɛ ox = 3.9, R = 20nm) (c) With SBT at = 35nm, t ox = 1nm, ɛ ox = 25, R = 20nm and PZT at = 70nm, t ox = 1nm, ɛ ox = 25, R = 20nm) Variation of C Mos, C ox, and C fe with gate voltage for Pillar-FeFET with SBT at R = 20nm (a) Voltage across Ferroelectric (V fe ), voltage across oxide layer (V ox ), surface potential (ψ s ) variation with gate voltage for two different materials (solid lines indicates for SBT at = 135nm, t ox = 1nm, ɛ ox = 3.9, R = 20nm and dashed lines indicate PZT material at = 350nm, t ox = 1nm, ɛ ox = 3.9, R = 20nm). (b) Voltage across Ferroelectric (V fe ), voltage across oxide layer (V ox ), surface potential (ψ s ) variation with gate voltage for two different materials (solid lines indicates for SBT at = 35nm, t ox = 1nm, ɛ ox = 25, R = 20nm and dashed lines indicate PZT material at = 70nm, t ox = 1nm, ɛ ox = 25, R = 20nm) Variation of surface potential with gate voltage with differenrroelectric materials, differenrroelectric layer thickness, different ε ox at t ox = 1nm and R = 20nm Variation of surface potential with gate voltage with differenrroelectric materials, different oxide layer thickness, different ε ox and R = 20nm Variation of gain with gate voltage with differenrroelectric materials, differenrroelectric layer thickness, different ε ox at t ox = 1nm and R = 20nm Variation of gain with gate voltage with differenrroelectric materials, different oxide layer thickness, different ε ox and R = 20nm (a) Variation of drain current with gate voltages for SBT material at different (b) at different t ox (a) Variation of drain current with gate voltage for Pillar-FeFET and Pillar-FET at different drain voltages (b) Variation of drain current with drain voltage for Pillar-FeFET and Pillar-FET at different gate voltages (a) Shows the NLF as a function of V g at V ds =0.1 V and V ds =0.5 V (b) Shows the I ratio, which is magnitude of I d2 /I d1, where I d2 =(µ2πr/l)(g s G d ), and I d1 = I ds I d2 for different drain voltages. For any drain bias, I ratio remains high only at low V g implying that the contribution of G in I ds is significant only at low-gate bias. Plots are made using R=20nm, L=1 µm for various devices (dev1: t ox =1nm, =135nm), (dev2: t ox =2 nm, =135nm), (dev3: t ox =2 nm, =150nm) (a), (b) are gate and drain terminal charges for Pillar-FeFET and for Pillar-FET with change in gate voltage and (c), (d) are gate and drain terminal charges with change in drain voltage calculated by exact numerical integrals (symbols) and proposed model (lines). The device parameters are t ox =1nm, =135 nm, R=20 nm and ɛ ox = Transcapacitances (a) C gg, (b) C dg for Pillar-FeFET and for Pillar-FET with change in gate voltage and (c) C gd, (d) C dd with change in drain voltage calculated by exact numerical integrals( symbols) and proposed model (lines). The device parameters are t ox =1nm, =135 nm, R=20 nm and ɛ ox =

16 xvi LIST OF FIGURES 4.16 DC analysis of inverter using Pillar-FET (solid lines) and Pillar-FeFET (dotted lines) transistors with device parameters t ox = 1nm, = 135nm, R = 20nm, ɛ ox = 3.9 and considered mobility of both NMOS and PMOS transistors are same and is 300cm 2 /V-sec Transient analysis of inverter using Pillar-FET (solid lines) and Pillar-FeFET (dotted lines) transistors with device parameters t ox = 1nm, = 135nm, R = 20nm and considered mobility of both NMOS and PMOS transistors are same and is 300cm 2 /Vsec Simulated transient response of 15-stage ring-oscillator built using N &P Pillar-FeFETs (dotted lines) has frequency of MHz and the same built with equivalent N &P Pillar-FETs (solid lines) has MHz. ( The W/L ratio of P-FET to N-FET is 3:1 in both Pillar-FeFETs and equivalent Pillar-FETs. In current calculations assumed electron and hole densities are 300 cm 2 /V-sec and 100 cm 2 /V-sec respectively. The device parameters used are =135 nm, t ox =1nm, R=20 nm, ɛ ox =

17 List of Tables Table Page 1.1 Landau parameters for differenrroelectric materials Subthreshold slope for two different materials having different Landau coefficients Read and write modes in 6T-SRAM cell Simulated results of 6T-SRAM cell SS for Pillar-FeFET using different materials at t ox = 1nm, R = 20nm xvii

18 Chapter 1 Introduction 1.1 Introduction to VLSI and the key challenge Very large scale integration of transistors is an important field of electronics, related to design and manufacture of high performing robust Integrated Circuits (IC) which consume very less power. Many fields like communications, signal processing, computational systems owe their progress to the field of VLSI. Fields like Artificial Intelligence (AI) [6] having applications in autonomous vehicles, robotics etc. need high performance computational hardware, which state-of-art VLSI technology offers, were hitherto impossible to be practically realized. Complementary Metal Oxide semiconductor process is the key technology in VLSI used to build Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) in ICs. VLSI field started with ICs having 100 s of transistors and currently billions of transistors are integrated into a single chip. To increase the device density in an IC, the physical dimensions of transistors need to be scaled down. Moore [7] in 1965, observed that transistor count integrated onto an IC doubles every two years. This remained true for many decades and is popularly termed as Moore s Law. However as the device dimensions got eventually scaled to sub-100nm, Moore s law began to saturate. Further scaling of transistor dimensions, resulted in high-leakage currents making transistor integration limited by the allowed power budget. Exploration of new transistor topologies and investigation of alternative materials to keep Moore s law alive, remains to be the key challenge in VLSI. 1.2 Problems of Scaling in Conventional MOSFETs Moore s law [7] predicted that continuous improvement can be achieved in transistor performance and its integration density using device scaling supplemented with innovations on transistor materials. Scaling the gate channel length results in higher drain currents and hence faster switching speed can be achieved. Device scaling is done using certain rules called scaling rules to attain optimal device performance [8]. The requirements of MOSFET to be an ideal switch is to have a high on-state current, zero off-state current and a sharp transition from off-state to on-state. Scaling rules reduce device dimen- 1

19 sions (such as channel length, gate oxide thickness, junction depth) and increase doping concentration which helps in boosting on-current and keeps off-current under control. Reducing device dimensions by scaling not only results in higher packing density (i.e. more circuits functionality on given die area) but also higher speed, lower power, reduced manufacturing cost, and other performance improvements. But as the feature size approached sub-100 nm range, in addition to the technological challenges the scaling of classical planar MOSFETs resulted in many problems related to device characteristics. At shortchannels, classical planar MOSFETs showed increased short channel effects (SCEs) like threshold voltage (V th ) roll off, drain induced barrier lowering (DIBL), and incremental in subthreshold swing (SS) [9]. This is because as the channel length is reduced the field lines originating from the drain region strong influence the channel potential and reduce the barrier seen by the electrons at the source which enhances the drain current [10]. In an ideal MOSFET, the barrier needs to be controlled only by the applied gate field. However in short-channels this assumption breaks. To increase the gate control of the channel, as suggested by the classical scaling rules, the gate oxide needs to be made thinner and the channel doping need to be increased. Thinner gate oxide results in more gate-leakage currents and larger doping results in increased reverse-biased junction leakage and random dopant fluctuations in short channels. To overcome these issues in scaled MOSFETs, new device topologies like Multi-Gate MOSFETs are explored. 1.3 Advantages Multi-Gate MOSFETs and their Structures Having more number of gates around the channel improves the electrostatic control of gate over the channel region. Improvement in gate control results in better short channel effects (SCEs). Various types of Multiple gate MOSFET structures are proposed in literature to replace the classical planar MOSFETs and extended the channel length scalability into the sub-20 nm regime. Different types of Multi-gate MOSFETs shown in Figure 1.1 Multi-Gate MOSFETs offer increased immunity to small-geometry effects, a near-ideal subthreshold slope, and other advantages like the increased mobility associated with low or no doping. Lower channel doping results in less effective electric field which reduces surface carrier scattering and gate tunneling [11, 12, 13]. The use of an undoped or lightly doped body provides immunity to threshold voltage and drive current variation due to statistical dopant fluctuations in Multi-Gate MOSFETs. For classical planar MOSFETs the substrate doping not only gives the control of the SCEs but also enables threshold voltage adjustment. In undoped Multi-Gate MOSFETs, the freedom for threshold voltage adjustment is lost. The required threshold voltage adjustment in Multi- Gate MOSFETs is usually achieved by gate work-function adjustment [14]. Moreover, the absence of doping in channel increases the carrier mobility due to lack of Coulomb scattering. 2

20 Figure 1.1 Different types of Multi-gate MOSFETs [1] 1.4 The Power Dissipation Bottleneck for CMOS Technology nodes Present world is defined by Internet, social media, Internet Of Things (IOT), smart phones. Around 70% of people using Internet daily and the number of people using the technology increasing day by day. In current world most of the things are digital. For every one minute almost 205 million s are transferred and about 350k tweets on Twitter [2]. The online activities are increasing day by day. Power forms an important metric in design of hardware systems. From Figure 1.2(a)) [2] the total energy consumption was very huge [15] and if it continues, in future the power consumption will reach an unmanageable level [16, 17]. The carbon emissions from all the data centers worldwide is too huge (Figure 1.2(c)) [3] and is comparable to the carbon emission of Malaysia and Netherlands. Figure 1.3(a) shows the evolution of CMOS power supply voltage and half-pitch over last 20 years [4]. Even though the dimensions of devices scale down the supply voltage has been remain at around 1 V for long time. In CMOS circuits the power density is proportional to the square of the supply voltage, frequency of operation and density. From Figure 1.3 (b,c) The increase in Central Processing Unit (CPU) frequency results in increase the power density to reach around 100 W/cm 2 level, which is really very high. Increase in power density beyond that level is not recommended, so for that clock frequency stopped increasing beyond 3 GHz from 2005 [5]. This is the reason why the supply voltage in CPU has not scaled at par with the dimensions of transistor originates from the physics of transistor operation. The Boltzmann distribution express that, to increase the drain current I d by an order magnitude at room temperature, the gate voltage V g needs to be increased by at least (kt/q) log 10=60mV, where q is charge of electron, k and T are Boltzmann 3

21 Figure 1.2 The projected energy consumption of data centers [2]. Carbon emissions of data centers [3]. 4

22 Figure 1.3 (a)the evolution of CMOS power supply and half-pitch over the 20 years [4] (b) the evolution of CPU Power Density (c) and microprocessor clock frequency. [5][5] 5

23 Figure 1.4 Comparison of Novel FET and conventional MOSFET constant and the temperature, respectively. So the the sub-threshold swing (SS) in an ideal classical MOSFET, defined as V g / log 10 I d, is 60 mv/decade. This limits scaling of supply voltage since a difference of at least 3-4 orders of current, is essential for a MOSFET to function as an efficient switch. This limitation is called as the Boltzmann Tyranny and is the bottleneck of a fundamental physics of MOSFET. Even if much engineering is put into a transistor device design, the SS cannot be lowered below this Boltzmann limit. The limitation of SS cannot be overcome without introducing new physics into MOSFET physics. Active research is in progress to reinvent the classical MOSFET [18, 19, 20, 21] which can have better subthreshold slope and has much lower power dissipation at advanced technology nodes. 1.5 Alternatives to get both scaling and power benefits For an ideal MOSFET, the expected current characteristics are shown in Figure 1.4. To overcome the problem of Boltzmann limit in conventional classical transistors, researchers proposed a number of alternative approaches. Examples are Tunneling Field Effect Transistors (TFET) [22, 23], Impact Ionization Metal Oxide Semiconductor transistors (IMOS) [24] and also suspended gate switches [25, 26]. In the mentioned approaches the transport mechanism, i.e., the way of electrons flow in a transistor, is changed such that the minimum limit Boltzmann can be avoided. In contrast, it was theoretically shown [27] that it may be possible to keep the mechanism of transport intact, but change the electrostatic gating 6

24 in such a way that it steps up the surface potential of the transistor beyond what is possible conventionally. Researchers recently proposed Negative Capacitance concept, in which the basic principle active relies on the ability to drive the Negative capacitance material away from its local energy minimum to a non-equilibrium state where its capacitance (dq/dv ) is negative and stabilizing it by adding a series positive capacitance called Negative Capacitance FET without changing the transport mechanism. With the help of Multi-Gate transistors we can get better gate control at short-channels. We can achieve higher density however the subthreshold leakage is unavoidable to Boltzmanns limit resulting in higher leakage power consumption. The increased power consumption limits the maximum active silicon on a chip. Any circuits exceeding the power envelope virtually remain useless, since they cannot be powered on often termed as dark silicon. Reduction of SS below 60 mv/dec will reduce the sub-threshold power dissipation, heating issues in the transistor. With Multi-Gate Negative capacitance approach, We use the advantages of Multi-Gate transistors in short-channels and steep SS will be achieved using Negative Capacitance phenomenon. Hence the Multi-Gate Negative capacitance FETS offer great potential for future scaling nodes and make the Moore s Law alive. 1.6 Negative Capacitance A capacitor is an element that stores charge. Capacitance of any device C can be defined as the rate of increase of charge Q with rate of rate of increase in voltage applied across its terminals i.e. (C = dq/dv ). Hence, from the definition, for a negative capacitor, charge Q decreases as voltage V is increased. In another way, capacitance can also be defined in terms of the free energy U. For a given negative capacitor, the energy landscape is an inverted parabola (see Figure 1.5). For a linear capacitor, energy U = Q2 2C. The capacitance can be defined as follows in terms of free energy is C = [ d 2 ] 1 U dq 2 (1.1) The above same relation holds for a non-linear capacitor also. In other way, in the energy landscape, the curvature is negative for negative capacitor Ferroelectric Ferroelectrics are materials which have electric polarization (Polarization (P ) is the electric dipole moment per unit volume) even in the absence of an external electric field, the direction of the polarization may be reversed by an electric field in ferroelectric materials. The properties of ferroelectric materials are a. It is capable of getting polarized when electric field is zero named as spontaneous polarization. b. Ferroelectric materials have pre-existing or permanent dipoles or natural dipoles. c. The individual dipoles are not randomly oriented but the regions or domains consisting of dipoles are randomly oriented which causes zero net polarization at zero electric field. 7

25 d. When external electric field is applied the dipoles are oriented in parallel in the domains and they are aligned with the direction of electric field. From Landau theory, for a non-linear ferroelectric capacitor the relationship between energy or Gibb s free energy (U) and polarization (P ) per unit area can be expressed as where P dp dt + P U = 0 (1.2) U = ap 2 + bp 4 + cp 6 E ext P (1.3) is the Gibb s free energy given by the sum of the anisotropy energy and the energy due to the external electric field (E ext ), a < 0, b > 0, c > 0 are ferroelectric material coefficients, the value of a is negative till the Curie temperature (T c ) for ferroelectric capacitor [28, 29]. For simplicity, consider the steady-state polarization and set dp dt we can obtain external electric field = 0. From equations (1.2) and (1.3) E ext = 2aP + 4bP 3 + 6cP 5 (1.4) From equation (1.4) we can obtain voltage across ferroelectric capacitor (V fe ) is V F E = 2a P + 4b P 3 + 6c P 5 (1.5) where is the thickness of ferroelectric material. The total charge density for a given material can be written as Q = ε fe E + P, where ε fe is the Permittivity of the ferroelectric material, E is the external applied electric field and P is the polarization. In general ferroelectric materials, P >> ε fe E. So this leads to Q = P. The electric charge per unit area can be expressed as Q P. So the charge voltage relation for ferroelectric capacitor can be written as V F E = 2a Q + 4b Q 3 + 6c Q 5 The capacitance offered by ferroelectric is given by = a 0 Q + b 0 Q 3 + c 0 Q 5 (1.6) C fe = Q/V F E (1.7) There are different types of ferroelectric materials available. Table 1.1 shows different materials and their corresponding Landau coefficients. The Landau parameters or coefficients (a, b, c) are different for differenrroelectric materials. Here a is temperature dependent and it has linear relationship with temperature as a = a x (T T C ), where a x is temperature independent and it is positive quantity, T 8

26 Figure 1.5 (a) Energy landscape and charge versus voltage for positive capacitor (b) Energy landscape and charge versus voltage for Negative capacitor 9

27 S.NO ferroelectric material a(m/f ) b ( m 5 /F/C 2) c ( m 9 /F/C 4) 1 BTO[27] PZT[28] SBT[30] Table 1.1 Landau parameters for differenrroelectric materials Figure 1.6 Energy well diagram of ferroelectric material. The region under dashed lines indicates the negative capacitance region. and T C are temperature and Curie temperature respectively. So a will be negative for the temperature below Curie temperature, which results negative curvature around P = 0 in the energy landscape of ferroelectric material. Ferroelectric materials have a negative curvature in their energy landscape as shown in Figure 1.6. Energy well has two energy minima s. From this the ferroelectric material could provide a non-zero polarization even without an applied electric field. If do we comparing the characteristic ferroelectric energy landscape (Figure1.6) with that of positive capacitor shown in Figure 1.5(a), we could see that the curvature around the point Q = 0 of a ferroelectric material is just the opposite to that of an ordinary capacitor. The dotted region in Figure 1.6 will provide negative capacitance. Figure 1.7 shows the polarization vs voltage characteristics of a ferroelectric capacitor in from the Landau theory of ferroelectric materials, ferroelectric capacitor has a non linear charge vs voltage characteristics in which the negative capacitance of material can be obtained in a certain range of charge and voltage as represented by the dashed curve. Due to the two well energy landscape, the ferroelectric material suffer from hysteresis problem. The energy required to move from one well to another is not same when do reverse. From the Figure 1.9 [1] the polarization-voltage hysteresis characteristics of a ferroelectric capacitor and shows the energy landscapes at different points on the hysteresis curve. From the Figure, 1.8 the curve ABC represents 10

28 Figure 1.7 Charge or polarization vs voltage characteristics of a ferroelectric material. Here negative capacitance is represented by dotted line. [1] Figure 1.8 Ferroelectric Hysteresis plotted as polarization vs. electric field 11

29 Figure 1.9 Polarization-voltage hysteresis characteristics of a ferroelectric capacitor. The energy landscapes at different points on the hysteresis curves [1] the increase in polarization of ferroelctric material from zero to saturation value. AE represents the saturation polarization, P s. If we try to lower down the applied electric field, after saturation the polarization curve follows the path CBD instead of CBA. It happens because the polarization ferroelectric materials follow is orientation polarization, so the atoms have to move from one place to another. It is a sluggish process, therefore, even if the electric field is reduced, the atoms cannot come to its original position and results in a phase lag between the change in orientation of domains and the electric field. That is the reason, even in zero electric field there remains a positive polarization and this phenomena is called as remnant polarization, P r. The distance AD represented in the Figure 1.8 shows the remnant polarization. To make the polarization in ferroelectric material zero again, a negative electric field needs to be applied and is known as coercive field, E c. From the Figure 1.8 AF shows the coercive field. If we go further in the negative direction, the curve will saturate again and the domains will be aligned in parallel with the negative electric field and here F G represents the path of change. then if we go to zero electric field again, then we will get negative polarization. If we increase the electric field further, the polarization will again reach the saturation point C. This continuous process with the change of electric field is called as the hysteresis or hysteresis loop of ferroelectric material.the problem of hysteresis in ferroelectric material can be avoided by adding a proper positive capacitance in series with ferroelectric material. Figure 1.10(a) and (b) show the structure of ferroelectric and dielectric combination and its equivalent capacitor circuit. Figure 1.10(c,d,e) show the energy landscapes for the ferroelectric-dielectric series combination for different cases. For the case in Figures 1.10(c,d), the ferroelectric negative capacitance is stabilized, for the case in Figure 1.10(e) it is not stabilized. For the case in Figure 1.10(c) the energy landscape has still two minima s, but almost flat, which means that it is still behaves like ferroelectric with small spontaneous polarization and small hysteresis. For Figure 1.10(d) the energy landscape is less flat and it has single minima and it behaves as dielectric. 12

30 Figure 1.10 Stabilization of ferroelectric negative capacitance using positive capacitance [1] Conventional MOSFET with Ferroelectric Figure 1.11 (a) shows a conventional MOSFET modified to have a negative capacitance layer on top of insulator. The performance of the classical MOSFET can be improved by minimizing SS below the Boltzmann limit. The equivalent capacitor diagram of Negative capacitance MOSFET in Figure 1.11 (b). Here the ferroelectric capacitor is added in series with positive capacitor in conventional MOSFET. The idea for negative capacitance to reduce the sub threshold slope below 60 mv/decade. Here the idea is to place a negative capacitance (ferroelectric) material on top of gate oxide layer. To get better understand how negative capacitance will help in reducing the power supply voltage and hence energy dissipation in conventional transistors, we can note that a field effect transistor could be thought of a series combination of two capacitors i.e the gate oxide capacitor C fe and the semiconductor capacitor C dep as shown in Figure 1.11 (b). In a conventional transistor, where is a positive capacitor, the equivalent capacitance of these two series capacitors would be smaller than that of two positive capacitors. On the other hand, when a negative capacitor C fe connected in series with C ox, C dep, the equivalent capacitor would be larger than C Mos. Now we can understand that reduction in supply voltage in the following way: since the total capacitance is enhanced by having a negative capacitance, it needs less voltage to generate the same amount of charge Q across all the series capacitors, all of which have the same Q due to being in series. The current in the channel is proportional to the charge across C dep. This means that the same amount of drain current can be produced with less voltage. 13

31 Figure 1.11 (a) Negative capacitance MOSFET and (b) its equivalent capacitors From the definition of SS, the SS is mathematically given by, SS = V g (1.8) log 10 I d V in = V g V in log 10 I ( d = 1 + C ) dep 60mv/dec C ins = m 60mv/dec (1.9) Here V g is the gate voltage applied to MOSFET, I d is the drain current, V in is the intermediate voltage shown in Figure 1.11 (b), C ox = ɛ ox /t ox is oxide capacitance, C fe is the ferroelectric capacitance, C dep is the depletion capacitance of MOSFET and C ins is the series combination of C fe and C dep. m = ( 1 + C ) dep C ins (1.10) = 1 + C dep 1 1 Cox 1 C fe (1.11) To get the SS value below Boltzmann limit the value of m should be less than one. So from equation (1.10) and (1.11) 1 + C dep 1 1 Cox 1 C fe < 1 (1.12) 14

32 C fe < C ox (1.13) To get hysteresis free operation the the value of m should be positive. So, C dep 1 1 Cox 1 C fe > 1 (1.14) where the MOSFET capacitance (C Mos ) is, C fe > C Mos (1.15) 1 C Mos = (1.16) C ox C dep Hence from equation (1.13) and (1.15) the constraints for hysteresis and lower SS [31] are, C Mos < C fe < C ox (1.17) In further sections we developed core compact model for multi-gate negative capacitance FETs which can enable their circuit simulation. The detailed description of model development and circuit simulation is discussed in next coming chapters. 1.7 Compact Modeling Compact models are required for simulation of circuits or in circuit design with new devices. Compact model contains the physics of transistor and mathematical information of the transistor characteristics in closed form. Compact models provide a bridge between circuit designers and chip manufacturers. Usually, compact models of MOSFETs were threshold voltage based model and they switched between different regions by using smoothing functions. There are inversion charge base models, in these models, a single equation is enough for all modes of operation and no need of smoothing functions and it is more accurate than threshold voltage based models. We use Inversion charge based compact modeling approach in our derivations. The long-channel core model forms the main component of any device compact model. On top of core model other real device effects will be applied to get good accuracy for the compact model. For the long channel devices we can use the core model directly without using real device effects. The core model consists of I-V equation using surface potential or inversion charge and quasi-static terminal 15

33 Figure 1.12 A compact model is formed from a core model (long-channel) and different real-device models 16

34 charges. The short-channel device effects become significant when the device is scaled aggressively. Figure 1.12 shows the structure of a compact model. The real device effects consists of short-channel effects, Non quasi-static terminal charges, different noise models, reliability effects, temperature effects, GIDL (Gate Induced Drain Lowering) current, Source/Drain resistances, fringe capacitances, quantum effects etc. 1.8 Scope and organization of the thesis This thesis is organized as follows. In chapter 1 introduces the problems with planar conventional classical transistors, the Multi-gate transistors and the concept of Negative capacitance for the future technology node for better performance and low power. In chapter 2 we present surface potential, current voltage characteristics of SDG-FeFET and conditions for hysteresis free operation, deriving of quasi-static terminal charges, different transcapacitances, verifies the correctness with exact numerical integrals, and compares the performance of SDG-FeFET with SDG-FET. In chapter 3 we simulate inverter, all the basic gates, ring oscillator, Half-Adder, full-adder, D- flip flop, 8 bit Ring counter and 8 bit ripple carry adder, 6T-SRAM cell with SDG-FeFET model and comparative study with circuits designed using SDG-FETs. In chapter 4 we present inversion charges, surface potential, different capacitances, different voltages at different oxide materials, differenrroelectric materials at different thickness, current voltage characteristics of Pillar-FeFET, conditions for hysteresis free operation, deriving of quasi-static terminal charges, different transcapacitances, verifies the correctness with exact numerical integrals, and compares the performance of Pillar-FeFET with Pillar-FET. In chapter 5 concluded the thesis and proposed future research plans to extend the thesis. 17

35 Chapter 2 Modeling of long channel Symmetric Double Gate Ferroelectric Field Effect Transistor (SDG-FeFET) 2.1 Introduction Double Gate-MOSFETs (DG-MOSFETs) or Multi-Gate transistors offer better electrical behavior in short geometries and reduced static leakage power [12, 11]. Switching power in a transistor can be reduced by minimizing its Subthreshold Swing (SS) [9]. However SS cannot be lowered below the Boltzmann s limit (< 60mv/decade ) without changing the nature of carrier transport [24, 23, 22]. The reduction in SS can be achieved exploiting the negative capacitance behavior of Ferroelectric material, as in Ferroelectric Field Effect Transistors (FeFETs) [27]. Hysteresis in ferroelectric material can pose a problem in switching behavior of the transistor since the threshold voltage changes with the forward and reverse sweep of gate voltage. To avoid hysteresis in the ferroelectric material, the thickness of ferroelectric layer has to properly tuned [31]. In a SDG-FeFET, the combination of DG-MOSFET structure along with ferroelectric material, offer considerable advantage in its electrical behavior at short-geometries and total power consumed, making it a promising device for advanced technology nodes [32]. Figure 2.1 shows the structure of SDG-FeFET. When the SDG-FeFET device is biased in the negative capacitance (NC) regime, the surface potential at the silicon-oxide interface can exceed the gate voltage, making its capacitance go negative. 2.2 Surface potential for SDG-FeFET Consider an undoped or lightly doped, negative capacitance FET with a Symmetric Double Gate geometry (see Figure 2.1). From Taur s study [33, 34] assuming the gradual channel approximation [35], Poisson s equation takes the following form along a vertical cut perpendicular to the semiconductor with only the mobile charge (electrons) term: 18

36 Figure 2.1 Structure of SDG-FeFET d 2 ψ dx 2 = q n i e q(ψ V ) kt (2.1) ɛ si where q is the electron charge, n i is the intrinsic carrier density ɛ si is silicon Permittivity, ψ (x) is the electrostatic surface potential, and V is the electron quasi-fermi potential, which is constant in the x-direction. Here, we consider an n-channel MOSFET (nmosfet) with qψ kt >> 1, so that the hole density is negligible. and The solution for the equation (2.1 ) from [36] is ψ(x) = V 2kT q Where β is the solution from the boundary following conditions ln t si q 2 ( ) n i 2βx 2β 2ɛ si kt cos (2.2) ( ɛ ox Vg V fb V F E ψ ( x = ± t )) si 2 dψ = ±ɛ si t ox dx x= t si 2 t si (2.3) V g V fb V F E ψ s V ox = 0 (2.4) Where V g is the gate voltage applied, V fb is the flat band voltage, V F E is voltage across ferroelectric layer, V ox is the voltage across oxide layer, ɛ ox is oxide Permittivity and ψ s is the electrostatic surface potential at x = ± t si 2, t si, t ox are thickness of silicon and oxide layer respectively. 19

37 From Landau-Khalatnikow (LK) theory, the voltage across ferroelectric layer (V F E ) can be derived as follows For a non-linear ferroelectric capacitor the relationship between energy or Gibb s free energy (U) and polarization (P ) per unit area can be expressed as where P dp dt + P U = 0 (2.5) U = ap + bp 4 + cp 6 E ext P (2.6) is the Gibb s free energy given by the sum of the anisotropy energy and the energy due to the external electric field (E ext ), a < 0, b > 0, c > 0 are ferroelectric material coefficients, the value of a is negative till the Curie temperature (T c ) for ferroelectric capacitor [28, 29]. For simplicity, consider the steady-state polarization and set dp dt we can obtain external electric field = 0. From equations (2.5) and (2.6) E ext = 2aP + 4bP 3 + 6cP 5 (2.7) From equation (2.7) we obtain voltage across ferroelectric capacitor as V F E = 2a P + 4b P 3 + 6c P 5 (2.8) where is the thickness of ferroelectric material. The electric charge per unit area can be expressed as Q P. So the charge voltage relation for ferroelectric capacitor can be written as V F E = 2a Q + 4b Q 3 + 6c Q 5 = a 0 Q + b 0 Q 3 + c 0 Q 5 (2.9) The coefficients are depends on different specific ferroelectric materials. Examples of few ferroelectric materials are Strontium Bismuth Titanate (SBT ) with coefficients a = m/f, b = m 5 F/coul 2, c = 0 and lead zirconate titanate (P ZT ) with coefficients a = m/f, b = m 5 F/coul 2, c = mf/coul 4 (in SI units). From Gauss s law, the total mobile charge or inversion charge per unit gate area can be determined by Q = ɛ si dψ s dx = ɛ si ( 2kT q ) ( 2β t si ) tan (β) (2.10) By substituting the mobile charge (Q), equation (2.9) into the equation (2.4) we get 20

38 ( ) (V g V fb V )q 2 2ɛ si kt ln 2kT t si q 2 n i ( = ln (β) ln [cos (β)] + a 0 + t ) ox (2C si ) β tan (β) ɛ ox From the equation (2.11) we can write f (β) as +b 0 (2C si ) 3 ( 4kT q +c 0 (2C si ) 5 ( 4kT q ) 2 β 3 tan 3 (β) ( f (β) = ln (β) ln [cos (β)] + a 0 + t ) ox (2C si ) β tan (β) +b 0 (2C si ) 3 ( 4kT q +c 0 (2C si ) 5 ( 4kT q ɛ ox ) 2 β 3 tan 3 (β) ) 4 β 5 tan 5 (β) (2.11) ) 4 β 5 tan 5 (β) (2.12) where β is the solution from the Input Voltage equation (IV E) (2.11), the range of β is in the range between 0 to π 2. The root β at source end is β sis obtained by replacing V as zero in IVE and the root at the drain end is β d is obtained by replacing V by V ds. From the equations (2.12)and IVE we can write replace IVE at source end f (β s ) and drain end f (β d ) can be written as f (β s ) = (q/2kt ) (V g V 0 ) (2.13) f (β d ) = (q/2kt ) (V g V 0 V ds ) (2.14) where V 0 = V fb + 2kT q ( 2 ln t si ) 2ɛ si kt q 2 n i (2.15) Figure 2.2 & 2.3 show the f (β) for two materials (SBT, P ZT ) at differenrroelectric thickness ( ). In general as increases, the negative capacitance behavior gets more pronounced. However, as shown in Figure 2.2 & 2.3, as the thickness of ferroelectric material increases, the device can have hysteresis. In this regime, for a given bias, multiple values of β are possible. From Figure 2.2 & 2.3 the variation of β with f (β) at different bias conditions show that the roots may get multiple values if the thickness of ferroelectric layer exceeds the maximum value. To avoid the hysteresis, the thickness of the ferroelectric material should be limited to a maximum value for a given material and oxide thickness. It was seen empirically that for a 1 nm gate oxide thickness, to avoid hysteresis in SBT material, the is limited to 150 nm. For a differenrroelectric material (PZT), the gets limited to 385 nm. 21

39 15 10 SBT =0 nm =100 nm =150 nm =250 nm f(β) 5 0 q(v g V 0 )/(2kT) 5 β d β s q(v g V 0 V ds )/(2kT) β Figure 2.2 Variation of f (β) with β for SBT at different and t ox = 1nm, t si = 10nm PZT t =0 nm fe t =100 nm fe t =385 nm fe =500 nm f(β) 5 0 q(v g V 0 )/(2kT) β d β s q(v g V 0 V ds )/(2kT) β Figure 2.3 Variation of f (β) with β for PZT at different and t ox = 1nm,t si = 10nm 22

40 Figure 2.4.a shows the variation of surface potential, voltage across oxide and voltage across ferroelectric layer for the SDG-FeFET device with applied gate bias for both materials. Figure 2.4.b shows the corresponding variation of inversion charge seen in the device. Figure 2.4.c shows the C fe (per unit area Ferroelectric capacitance) and Figure 2.4.d shows the C g (per unit area Gate capacitance) with applied gate bias V g for the SDG-FeFET device made with SBT and PZT materials respectively for t ox = 1nm and for the maximum hysteresis free, (150 nm for SBT and 385 nm for PZT) allowed. The boosting of C g happens around threshold voltage due to sharp increase in inversion charge in this region. From PZT and SBT materials the hysteresis free negative capacitance is obtained at 150 nm and 385 nm ferroelectric thickness respectively at oxide thickness of 1nm. So in our study, we continued the device with SBT material because of lower ferroelectric thickness required for the hysteresis operation at same oxide thickness. Figure 2.5 shows the variation of C Mos, C ox, and C fe with gate voltage for SBT at =150 nm and t ox =1 nm. From the equation (1.17) in chapter.1 the absolute value of C fe should be bounded between C Mos and C ox. The maximum boosting happens when the absolute value of C fe reaches to the C Mos but from Figure 2.5 the absolute value of C fe is matching only to a limited gate voltage, in the remaining bias range the difference between the absolute value of C fe and the C Mos is more. So the amount of boosting is also limited to small bias region in weak inversion. After the inversion the the C fe is going to positive and it behaves as normal positive capacitor. From the Figure 2.6 we can see that the surface potential plot for SDG-FeFET case, that is at = 150nm, the improvement of ψ s is more compared to the case with no ferroelectric, that is SDG- FET at the bias range of 0.5V, this is because of the limited matching of capacitances in Figure 2.5. The boosting of surface potential in the lower gate voltage is not much because the difference between C fe and the C Mos is more, the boosting is more in the weak inversion region. This boosting of surface potential leads indicates that the ψ s is more than gate voltage in weak inversion region. This is also one of the indication that the ferroelectric material offers negative capacitance. We simulated the surface potential of SDG-FeFET at differenrroelectric thickness (see from Figure 2.2). In the Figure 2.2 shows that as the thickness of ferroelectric layer increases the boosting in the surface potential also increasing in weak inversion region. If the thickness goes beyond the maximum value it shows hysteresis from Figure 2.2 & 2.3. From Figure 2.8, it shows that as the thickness of oxide layer increases for the given ferroelectric layer thickness (150nm), the boosting in the surface potential decreases in weak inversion region. This indicates that as t ox increases the should also increase to get negative capacitance effect, boosting of ψ s in weak inversion region, but it should not cross the maximum thickness to avoid hysteresis. If the oxide thickness increases, the thickness of ferroelectric layer should increase to get negative capacitance but it should be limited to maximum without hysteresis. So from this as as t ox increases the should also be more to make device more novel but it should be below the maximum limit. 23

41 Voltages (a) ψ s V ox V fe inversion charge(c/m 2 ) (b) PZT SBT V g V g 4 3 (c) PZT SBT (d) SBT PZT C fe (F/m 2 ) 2 1 C g (F/m 2 ) V g V g Figure 2.4 (a) Voltage across Ferroelectric (V fe ), voltage across oxide layer (V ox ), surface potential (ψ s ) variation with gate voltage for two different materials (solid lines indicates for PZT and dashed lines indicate SBT material). (b) Inversion charge variation with gate voltage for two different materials. (c) C fe variation with gate bias for two different materials. (d) C g variation with gate bias for two different materials. 24

42 C ox C fe Capacitance(F/m 2 ) C mos V g Figure 2.5 Variation of C Mos, C ox, and C fe with gate voltage and comparison ψ s = 150 nm with no ferroelectric V g Figure 2.6 Variation of surface potential with gate voltage. Plots are made using t si =10 nm, =150 nm and t ox =1 nm 25

43 ψ s =150 nm =100 nm =50 nm with no ferroelectric V g Figure 2.7 Variation of surface potential with gate voltage for SDG-FeFET at differenrroelectric layer thickness. Plots are made using t si =10 nm, =150 nm and t ox =1 nm ψ s At = 150 nm t ox = 1 nm t ox = 2 nm t ox = 3 nm t ox = 4 nm V g Figure 2.8 Variation of surface potential with gate voltage for SDG-FeFET at different oxide layer thickness. Plots are made using t si =10 nm, =150 nm and t ox =1 nm 26

44 2.3 Drain current equation for Symmetric Double-Gate Ferroelectric Field by Effect Transistors The drain current for the SDG-FeFET [30] including both drift and diffusion component is calculated I ds (y) = µw dv Q(y) (2.16) dy where Q(y) is the inversion charge or displacement charge per unit area, µ is the mobility, W is the width of transistor. Multiply the equation (2.16) with dy and integrate from source end to drain end: ˆ L 0 I ds (y) dy = µw ˆ Vd V s Q(y)dV (2.17) I ds = µ W L ˆ Vd V s Q(y)dV (2.18) I ds = µ W L ˆ βd β s Q(β) dv dβ (2.19) dβ here dv/dβ can be represented in the form of β by differentiating the IVE with respect to β and substituting this into (2.19) then I ds = µ 4C siw L ( 2kT q ) 2 [( a 0 + t ) ox C si β 2 tan 2 (β) ɛ ox ) 2 β 4 tan 4 (β) ( +β tan (β) + 3b 0 (2C si ) 3 2kT q β ( ) 6 c 0 (2C si ) 5 4kT 4 β 6 tan 6 (β) q ] β s (2.20) β d Figure 2.9 shows the input characteristics (gate voltage versus drain current) at different drain to source bias (V ds ) for both SDG-FeFET (with FE) and SDG-FET (without FE), where the equivalent oxide capacitance of SDG-FET is defined as C ox = ɛ ox /(t ox + a 0 ɛ ox ). From the characteristics it is seen that for SDG-FeFET with properly tuned ferroelectric layer thickness for the given oxide layer has boosting in the current in the weak inversion region. If the thickness of ferroelectric layer is going down for the given oxide thickness the amount of negative capacitance reduces, from that surface potential reduces which leads to decreasing the amount of boosting in weak inversion region. The input characteristics of SDG-FeFET and SDG-FET are observed at different V ds, in all the cases in Figure 2.9 it is shown that the boosting occurs in subthreshold region in SDG-FeFET. In all the cases, at different 27

45 I ds (A/µm) with FE at V ds =0.1V with FE at V ds =0.2V with FE at V ds =1V without FE at V ds =1V without FE at V ds =0.2V without FE at V ds =0.1V V g Figure 2.9 Gate voltage versus Drain current of SDG-FeFET and SDG-FET at different drain voltages. Plots are made using t si =10 nm, W=1 µm, L=1 µm and t ox =1 nm. I ds (A/µm) V ds =0.1 V SS=70 mv/dec SS=40 mv/dec SDG FeFET SDG V g Figure 2.10 Subthreshold Swing (SS) for SDG-FeFET and SDG-FET. Plots are made using t si =10 nm, =150 nm and t ox =1 nm. 28

46 x with FE at V g =0.6V 5 with FE at V g =0.8V with FE at V g =1V I ds (A/µm) without FE at V g =1V without FE at V g =0.8V without FE at V g =0.6V V ds Figure 2.11 Drain voltage versus drain current at different gate voltages for SDG-FeFET and SDG-FET. Plots are made using t si =10 nm, =150 nm and t ox =1 nm drain to source bias the ON current is more in SDG-FeFET compared to the ON current (I on ) of SDG- FET. But there is no change in OFF current (I off ). So the I on /I off ratio is more in SDG-FeFET compared to SDG-FET in all drain to source bias conditions. From the Figure 2.5 the boosting region is limited for ferroelectric material. So at the lower voltage range the drain current of SDG-FeFET is almost same as SDG-FET but in weak inversion region boosting is more because of good match of C fe and the C Mos. From Figure 2.10 the input voltage characteristics of SDG-FeFET at t si =10 nm, =150 nm and t ox =1 nm and SDG-FET with equivalent oxide capacitance at V ds = 0.1V for SBT material, the SS is 40mv/dec and is limited to only to limited region because the ferroelectric material has limitation of matching with the C Mos. But the I on /I off is improved for a given bias conditions which leads to better performance of device means the speed of operation is more and have better switching characteristics due to improvement in SS. From Figure 2.11 shows the output characteristics of SDG-FeFET and SDG-FET at different gate bias conditions. From the characteristics it is seen that in all the cases the SDG-FeFET has better characteristics than SDG-FET which always leads to better performance in speed and less switching power due to better switching characteristics. The Table 2.1 which shows the Subthreshold slope for two differenrroelectric materials (SBT and PZT) having two different Landau coefficients at hysteresis free condition. It is seen that for SDG- FeFET with PZT material, the SS is better compared to SS with SBT material, but at the cost of higher 29

47 S.NO Material Subthreshold Swing (SS) 1 SBT 150 nm (without hysteresis) 40 mv/dec 2 PZT 385 nm (without hysteresis) 35 mv/dec Table 2.1 Subthreshold slope for two different materials having different Landau coefficients ferroelectric thickness. Higher thickness of ferroelectric material increases the strain on the channel and increases the fringe capacitance component at gate electrode. 2.4 Quasi-static Terminal Charge Model for Symmetric Double-Gate Ferroelectric Field Effect Transistors A modified form for the drain current equation can be obtained in terms of Q is and Q id (the inversion charges at source end and drain end respectively), as in [37], Where I ds = 4µC si W L ( ) 2kT 2 (F (Q is, G s ) F (Q id, G d )) (2.21) q F ( Q is(d), G s(d) ) = AQis(d) + A 3 Q 2 is(d) + A 5Q 4 is(d) + A 7Q 6 is(d) + G s(d) (2.22) A = q 4kT C si (2.23) ( A 3 = A 2 a 0 + t ) ox C si (2.24) ɛ ox A 5 = 3b 0 (2C si ) 3 A 4 ( 2kT q A 7 = 5 6 c 0 (2C si ) 5 A 6 ( 4kT q ) 2 (2.25) ) 4 (2.26) G s(d) = β2 s(d) 2 (2.27) Q is(d) = 4kT q C siβ s(d) tan ( β s(d) ) (2.28) Using Ward Dutton charge partition theory [38] the integrals for the terminal charges are given by: 30

48 ˆL Q G = W Q i (y) dy (2.29) Q D = W 0 ˆL 0 y L Q i (y) dy (2.30) Q S = (Q D + Q G ) (2.31) Where y varies from y=0 (source end) to y=l (drain end) and represents the position along the channel where the inversion charge is computed. The expression for y is given by [39] y L = F s F F s F d (2.32) Where F s, F d are F (Q is, G s ), F (Q id, G d ) respectively. The closed form expressions for Q G and Q D integrals cannot be obtained directly from equations (2.29) and (2.30), since y involves higher order terms with βtan(β). So the charge linearization technique discussed in [37] is adapted to simplify the terminal charge integrals. Figure 2.12 (a), shows the variation of non-linearity factor of G for varying gate bias. The nonlinearity factor NLF (2.33) is calculated as in [40]. Where G lin is given by (16) NLF = Qid Q is [G (Q) G lin (Q)] 2 dq Q id Q is (2.33) ( ) Gs G d G lin = (Q i Q is ) + G s (2.34) Q is Q id It could be seen that, for low gate-bias, the non-linearity factor of G is small and becomes significant at higher gate-bias. The contribution of factor G to the total drain current however decreases with increasing gate bias. Hence in evaluating I ds or a quantity like y derived from I ds, G can be approximated to be G lin, without making a significant error. This observation is shown to be true for all bias conditions, by the good match obtained in terminal charge models, when compared with the exact numerical integration results. Expression for y/l is thus simplified using equations (2.34) in (2.32) resulting in (2.35) below. Where y L = A 6Q 6 i + A 4 Q 4 i + A 2 Q 2 i + A 1 Q i + F s + sq is G s F s F d (2.35) [A + s] A 1 = (2.36) F s F d 31

49 2.5 (a) NLF dev1 dev2 dev3 dev1 dev2 dev3 V ds =0.1V V ds =0.5 V V g I ratio (b) dev1 (V =0.1V) ds dev2 (V ds =0.1V) dev3 (V =0.1V) ds dev1 (V =0.5V) ds dev2 (V ds =0.5V) dev3 (V =0.5V) ds V g Figure 2.12 (a) Shows the non-linearity factor as a function of gate voltage at V ds =0.1 V and V ds =0.5 V (b) Shows the I ratio, which is magnitude of I d2 /I d1, where I d2 =4µC si (W/L)(2kT/q) 2 (G s G d ), and I d1 = I ds I d2 for different drain biases. For any V ds, the value of I ratio remains high only at low gate-bias implying that the contribution of G in I ds is significant only at low-gate bias. Plots are made using t si =10 nm, W=1 µm, L=1 µm for various devices (dev1: t ox =1 nm, =150 nm), (dev2: t ox =2 nm, =150 nm), (dev3: t ox =2 nm, =200 nm). 32

50 ( ) ] [A 2 a 0 + tox ɛ ox C si A 2 = (2.37) F s F d [ ( ) ] 2 3b 0 (2C si ) 3 A 4 2kT q A 4 = F s F d (2.38) A 6 = [ ( ) ] c 0 (2C si ) 5 A 6 4kT q F s F d (2.39) s = G d G s Q id Q is (2.40) dy = L ( 6A 6 Q 5 i + 4A 4 Q 3 i + 2A 2 Q i + A 1 ) dqi (2.41) Terminal charge integrals ( ) can then be evaluated as shown below Q G = W ˆ Q id Q is Q i dy dq i (2.42) dq i [ 6A6 ( = W L Q 7 7 id Q 7 4A 4 ( is) + Q 5 5 id Q 5 is) + 2A 2 ( Q 3 3 id Q 3 A 1 ( is) + Q 2 2 id Q 2 ) ] is (2.43) 33

51 Q D = W L ˆ Q id Q is dy yq i dq i (2.44) dq i [ A 2 = W L 1 ( Q 3 3 id Q 3 ) 2A 2 ( is + 2 Q 5 5 id Q 5 is) + 4A2 ( 4 Q 9 9 id Q 9 ) 6A 2 ( is + 6 Q 13 id 13 ) Q13 is + 3A 1A 2 ( Q 4 4 id Q 4 5A 1 A 4 ( is) + Q 6 6 id Q 6 is) + 6A 2A 4 ( Q 7 7 id Q 7 7A 1 A 6 ( is) + Q 8 8 id Q 8 is) + 8A 2A 6 ( Q 9 9 id Q 9 10A 4 A 6 ( is) + Q 11 id 11 ) Q11 is + A ( 1G s Q 2 id Q 2 ) is + 2A ( 2G s Q 3 id Q 3 ) is 2 (F d F s ) 3 (F d F s ) + 4A ( 4G s Q 5 id Q 5 ) is + 6A ( 6G s Q 7 id Q 7 ) is 5 (F d F s 7 (F d F s A ( 1 Q 2 id Q 2 ) is Fs 2A ( 2 Q 3 id Q 3 ) is Fs 2 (F d F s ) 3 (F d F s ) 4A ( 4 Q 5 id Q 5 ) is Fs 6A ( 6 Q 7 id Q 7 ) is Fs 5 (F d F s ) 7 (F d F s ) sa ( 1 Q 2 id Q 2 ) is Qis 2sA ( 2 Q 3 id Q 3 is 2 (F d F s ) 3 (F d F s ) 4sA ( 4 Q 5 id Q 5 ) is Qis 5 (F d F s ) 6sA ( 6 Q 7 id Q 7 ) ] is Qis 7 (F d F s ) ) Qis (2.45) Q S = (Q D + Q G ) (2.46) In the following simulations, we use a long-channel SDG-FeFET device (W= 1µm, L=1 µm) with parameters =150 nm, t ox =1 nm and t si =10 nm. The ferroelectric layer thickness,, is tuned to avoid hysteresis without losing the negative capacitance behavior [36]. The negative capacitance depends on the ferroelectric material thickness and Landau parameters [28]. To avoid hysteresis, it was seen that for a 1nm gate oxide, in Strontium Bismuth Tantalite (SBT) material the is limited to 150 nm. For a differenrroelectric material Lead Zirconate Titanate (PZT), the gets limited to 385 nm. In case of short channels, (L < 2λ ), where λ is the characteristic length of double gate MOSFET given by λ = (t si + 2(ɛ si /ɛ ox )EOT )/π, where EOT is the equivalent oxide thickness [41, 30], the thickness of ferroelectric layer needs to be tuned including the increased drain to channel coupling short-channel 34

52 2.5 x (a) Q G (C) SDG FeFET V ds =1 V V ds =0.1 V 0.5 SDG FET x V g 2 (b) SDG FET 4 V ds =1 V Q D (C) 6 8 SDG FeFET V ds =0.1 V V g 35

53 x (c) 2 V gs =1 V SDG FeFET Q G (C) V gs =0.6 V SDG FET V d x V gs =0.6 V SDG FET Q D (C) 6 8 V gs =1 V SDG FeFET (d) V d Figure 2.13 (a), (b) are gate and drain terminal charges with change in gate voltage and (c), (d) are gate and drain terminal charges with change in drain voltage of the device calculated by exact numerical integrals (symbols) and by proposed model (lines). The device parameters are t ox =1nm, =150 nm, t si =10 nm. 36

54 x (a) 2 c gg (F/µm) V ds =0.1 V SDG FeFET V ds =1 V 0.5 SDG FET x (b) V g c dg (F/µm) V ds =0.1 V SDG FeFET SDG FET 0.2 V ds =1 V V g 37

55 3.5 x (c) c gd (F/µm) SDG FeFET V d SDG FET V gs =1 V V gs =0.6 V x (d) 2.5 c dd (F/µm) SDG FeFET SDG FET V gs =1 V 0.5 V gs =0.6 V V d Figure 2.14 Transcapacitances (a) C gg, (b) C dg with change in gate voltage and (c) C gd, (d) C dd with change in drain voltage of the device calculated by exact numerical integrals( symbols) and by proposed model (lines). The device parameters are =150 nm, t ox =1nm, t si =10 nm. 38

56 capacitance. The appropriate thickness of the ferroelectric material for short-channels, is thus arrived at, for a given ferroelectric material, oxide thickness and a given channel length. Figure 2.13 & 2.14 show the variation of gate, drain terminal charges and the four independent capacitances [33] namely C gg, C dg, C dd, C gd capacitances of the SDG-FeFET obtained using the closed form expressions ( ), with high and low, gate and drain biases. As seen from the plots, a good match in terminal charge models and transcapacitances is obtained for the expressions derived in ( ), when compared to the values obtained by numerical integration of exact integrals ( ) for all bias conditions. We use the math tool, Matlab [42], to perform the numerical integrals and evaluate the derivatives for transcapacitances. For comparison purpose, the corresponding terminal charge and transcapacitance values obtained for equivalent SDG-FET are as well included. Values obtained by numerical integration of exact integrals are seen to match pretty well even in the case of SDG-FETs for high and low, gate and drain biases. In the plots, it could be seen that, a boosting in charge happens in the negative capacitance regime for a SDG-FeFET, resulting in a steep slope in capacitance curves in moderate inversion. The capacitance is seen to decrease once it is out of the negative capacitance regime. Using the SDG-FeFET surface-potential equation, drain current model [36] and the closed form quasi-static terminal charge expressions derived ( ), we build the core compact model for SDG-FeFET using the Verilog-A interface. We use the SmartSpice R simulator [43] to simulate a all the basic gates, 15-stage ring-oscillator, 8-bit Johnson ring counter, 8- bit ripple carry adder, 6T-SRAM cell, built with long channel (L=1um) SDG-FeFET transistors and compare their transient response with corresponding circuits built with equivalent oxide capacitance, SDG transistors. The simulations of the circuits using SDG-FeFETs are explained in next chapter. 2.5 Summary We have studied the terminal charges and capacitances for different voltages and device parameters for SDG-FeFET using two ferroelectric materials, SBT and PZT.. The Hysteresis free condition for the SDG-FeFET is obtained varying thickness of the ferroelectric layer. The surface potential of SDG-FeFET at differenrroelectric layer thickness and different oxide thickness is simulated and corresponding drain current is plotted. It is shown that the boosting of ON current and SS minimization occurs in SDG-FeFET which makes it superior compared to SDG-FET. Further a Closed form Quasistatic Terminal Charge Model for SDG-FeFET is derived. It is shown that all the terminal charges and transcapacitances with SDG-FeFET and SDG-FET for any given device parameters math well with the exact numerical integrals. 39

57 Chapter 3 Circuit applications using Symmetric Double Gate Ferroelectric Field Effect Transistor (SDG-FeFET) 3.1 Introduction IOT, Mobile and wearable electronic products demand energy efficient design to avoid repeated battery charging cycles. Device scaling reduces the device area and associated dynamic power. However Short channel effects increase as channel length is scaled down. The subthreshold slope degrades with scaling resulting in worser I on /I off ratio. This results in increased power consumption. To reduce the dynamic power at a given technology node, power-supply voltage scaling is exploited aggressively since voltage has quadratic effect on dynamic power consumed. However when the supply voltage scales down, the speed of operation and the static noise margin (SNM) [44] in a device decreases. Hence scaling of power supply needs to be performed taking into account noise-margin and performance requirements. In digital CMOS designs, memory consumes significant portion of the total power budget. In most of the ASIC products today, SRAMs are used as local memories in the designs because of their superior memory access latencies. Low power consumption, high stability to noise and high speed of operation are important requirements for an SRAM cell to be efficient in such designs. As discussed in chapter1, multi-gate devices offer better control of channel, resulting in reduced leakage currents [11, 12]. However even in these multi-gate devices, the subthreshold swing is limited by the Boltzmann s limit, which determines the maximum reduction that can be achieved.[36]. SDG-FeFETs offer a promising solution in reducing the leakage currents since the subthreshold swing in these devices is not limited by the Boltzmann s limit. In this chapter, we present basic logic gates, data path circuits like adders, sequential circuits like D Flip-Flop, Ring Counter, SRAM circuit like a 6T-SRAM cell and benchmark circuits like ring oscillator designed using SDG-FeFETs. The performance of these circuits is compared with equivalent SDG-FETs. Parameters affecting the performance and stability in circuits built with SDG-FeFETs is discussed. 40

58 Figure 3.1 (a) circuit symbol for PMOS SDG-FET, SDG-FeFET (b) circuit symbol for NMOS SDG- FET, SDG-FeFET Figure 3.1 shows the symbols for PMOS and NMOS transistors. The device has symmetrical double gates means both gates are identical, same work function (V fb ), same oxide thickness (t ox ) applied with same gate voltages and are shorted. Hence the symbol is shown to have both gates shorted in both NMOS and PMOS versions. Here both gates are represented by G, source is represented by S and drain is represented by D as in conventional CMOS. 3.2 Digital Circuits In this section, we present different logic circuits built using SDG-FeFETs, their simulated wave forms and comparison with equivalent SDG-FETs implementations. For all the circuits, the device parameters chosen for SDG-FET and SDG-FeFET transistors are t ox = 1nm, = 150nm, t si = 10nm, L = 1µm, W = 1µm and ferroelectric coefficients for SBT are (a = 1.3e8 m/f, b = 1.3e10 m 5 F/coul 2, c = 0) [36]. Using the Verilog-A device model developed in chapter 2, the behavior of equivalent SDG-FET can be obtained by making b and c Landau coefficients zero. The equivalent oxide thickness for the SDG-FET is taken to be t ox + a 0 ε ox where a 0 = 2.a. [36] Inverter Figure 3.2 shows the inverter circuit and its circuit symbol using Figure 3.1. Figure 3.3 shows the DC analysis of inverter by sweeping the Vin form 0V to 1V and plotted the transfer characteristics of an inverter. From the Figure 3.3 we see that the transfer characteristics of inverter using SDG-FeFETs is slightly better than the inverter built using SDG-FETs. The noise margin for the SDG-FeFETs hence remain better than SDG-FETs and tunable using the Landau parameters. Figure 3.4 shows the transient analysis of inverter by applying square wave as input to the inverter at room temperature. Plots for the transient analysis show sharper transitions for SDG-FeFETs compared to the SDG-FETs case. From the plot, the propagation delay of the inverter using SDG-FeFETs is 11ps 41

59 Figure 3.2 (a) Inverter circuit (b) circuit symbol Figure 3.3 Dc analysis of inverter using SDG-FET (solid lines) and SDG-FeFET (dotted lines) transistors with device parameters t ox = 1nm, = 150nm, t si = 10nm and considered mobility of both NMOS and PMOS transistors are same and is 300cm 2 /V-sec. 42

60 Figure 3.4 Transient analysis of inverter using SDG-FET (solid lines) and SDG-FeFET (dotted lines)transistors with device parameters t ox = 1nm, = 150nm, t si = 10nm and considered mobility of both NMOS and PMOS transistors are same and is 300cm 2 /V-sec. while the same in the case of SDG-FETs is 55ps. Hence it can be seen that the SDG-FeFETs offer better performance compared to SDG-FETs Stage Ring oscillator Figure 3.5 shows the schematic view of ring oscillator for n stage, here the n must be odd number to get oscillations. Here in this we constructed 15 stage ring oscillator simulated with SDG-FeFETs and SDG-FETs. Figure 3.6 shows that, the ring-oscillator built with complementary SDG-FeFETs has higher frequency than the one built with the equivalent SDG-FETs. Simulated transient response of 15-stage ring-oscillator built using N &P- SDG-FeFETs has frequency of MHz and the same built with equivalent N &P - SDG-FETs has MHz. From Figure3.6(b), it can be seen that, in order to match the frequency of ring-oscillator built with SDG-FeFET having 1 V rail-to-rail voltage, a higher rail-torail voltage of 1.6 V is needed for the circuit built with complementary SDG-FETs. Thus to achieve the same performance SDG-FeFETs need a much lesser voltage supply resulting in significant improvement in dynamic power All basic gates Figure 3.7 shows all basic gates circuit symbols and their truth tables, Figure 3.8 shows the transient simulation of all gates with SDG-FeFETs and SDG-FETs. The propagation delays seen in AND, OR, 43

61 Figure 3.5 Schematic view of Ring Oscillator Figure 3.6 (a) Simulated transient response of 15-stage ring-oscillator built using N &P- SDG-FeFETs has frequency of MHz and the same built with equivalent N &P - SDG-FETs has MHz. (b) Demonstration of match in frequency of ring-oscillator built with SDG-FeFETs operating at rail-torail voltage of 1 V with the one SDG-FETs having higher rail-to-rail voltage of 1.6 V. The W/L ratio of P-FET to N-FET is 3:1 in both SDG-FeFETs and equivalent SDG-FETs. Mobility of electrons and holes assumed in current calculation are 300 cm 2 /V-sec and 100 cm 2 /V-sec respectively. The device parameters used for SDG-FeFET are =150 nm, t ox =1nm, t si =10 nm. 44

62 Figure 3.7 Schematic view of all logic gates. NAND, NOR, EX-OR using SDG-FeFETs are 0.056ns, 0.046ns, 0.044ns, 0.074ns, 0.089ns respectively and SDG-FETs are 0.669ns, 0.769ns, 0.25ns, 0.376ns, 1.328ns respectively. From this we can say that the gates build with SDG-FeFETs have better speed than with the SDG- FETs Full Adder Figure 3.9 shows the schematic view and truth table of Full Adder (FA). The circuits used for each of the logic gates is same as discussed in previous section. The transient simulation of Full Adder simulated using SDG-FETs and SDG-FeFETs are shown in Figure Here in the plots the dotted lines show the SDG-FeFET case and solid lines show SDG-FET case. From the plots we can see that the propagation delay of FA with SDG-FeFETs is 0.09ns and using SDG-FETs is ns. Further the transition from rise to fall and fall to rise is more sharp in case in SDG-FeFETs than SDG-FET. 45

63 Figure 3.8 Transient analysis of all gates using SDG-FET (solid lines) and SDG-FeFET (dotted lines) transistors with device parameters t ox = 1nm, = 150nm, t si = 10nm and considered mobility of both NMOS and PMOS transistors are same and is 300cm 2 /V-sec. 46

64 Figure 3.9 Schematic view of Full Adder Figure 3.10 Transient analysis of Full Adder using SDG-FET (solid lines) and SDG-FeFET (dotted lines) transistors with device parameters t ox = 1nm, = 150nm, t si = 10nm and considered mobility of both NMOS and PMOS transistors are same and is 300cm 2 /V-sec. 47

65 Figure 3.11 Schematic view of ripple carry adder Figure 3.12 Transient analysis of ripple carry adder using SDG-FET and SDG-FeFET transistors with device parameters t ox = 1nm, = 150nm, t si = 10nm and considered mobility of both NMOS and PMOS transistors are same and is 300cm 2 /V-sec bit Ripple Carry Adder Figure 3.11 shows the schematic view of 8-bit ripple carry adder. Here for the 8-bit case the propagation delay of adder is sum of propagation delay of 8 FA. Here the inputs we consider for the simulation purpose are A7 to A0 are , B7 to B0 are and Cin as 0. The transient simulation of ripple carry adder simulated using SDG-FETs and SDG-FeFETs are shown in Figure Here in the plots the dotted lines show the SDG-FeFET case and solid lines show SDG-FET case. From the plots we can see that the propagation delay of ripple carry adder with SDG-FeFETs is ns and using SDG-FETs is ns and the transition from rise to fall and fall to rise is more sharp in case in SDG- FeFETs than SDG-FET. Drain current boosting that occurs at threshold due to Negative capacitance effect, we can get better speed of operation for the same bias. 48

66 Figure 3.13 Transient analysis of D flip flop using SDG-FET (solid lines) and SDG-FeFET (solid lines) transistors with device parameters t ox = 1nm, = 150nm, t si = 10nm and considered mobility of both NMOS and PMOS transistors are same and is 300cm 2 /V-sec. Figure 3.14 Schematic view of Johnson s ring counter 3.3 Sequential Circuits We simulated few sequential circuits like D flip flop and 8-bit Johnson s ring counter. Figure 3.13 shows the simulated wave forms of D flip flop. The propagation delay offered by SDG-FET case is more than the SDG-FeFET case are 3.805ns and ns respectively. Figure 3.14, 3.15 show the circuit and simulated wave forms of 8-bit Johnson s ring counter. For N bit Johnson s ring counter the number of states are 2N. Here the propagation delays offered by Johnson s ring counter using SDG-FET and SDG-FeFET are 4.866ns and 0.983ns, which shows the SDG-FeFETs show better performance than SDG-FETs. 49

67 Figure 3.15 Transient analysis of 8-bit Johnson s ring counter using SDG-FET and SDG-FeFET transistors with device parameters t ox = 1nm, = 150nm, t si = 10nm and considered mobility of both NMOS and PMOS transistors are same and is 300cm 2 /V-sec. 50

68 Read operation WL=1, BL=1, BLB=1 Write operation WL=1, BL=1, BLB=0 Table 3.1 Read and write modes in 6T-SRAM cell 3.4 6T-SRAM CELL Figure 3.16 shows the schematic diagram of 6T-SRAM cell. A 6T-SRAM cell is composed of six transistors, in which four transistors(n 1, n 2, p 1, p 2 ) form the two cross coupled CMOS inverters and two NMOS transistors (n 3,n 4 ) are used for access. The transistors n 1 and n 2 are called driver or pulldown transistors, p 1 and p 2 are called pull-up or load transistors. The BL (bit line) and BLB (bit line complement) are two bit lines, W L is the word line and q and qb are the two storage nodes of SRAM cell respectively. This configuration has 6 transistors so it is called a 6T-SRAM cell and the two cross coupled inverters make the memory element. The 6T-SRAM cell has two stable states which are used to represent states either 0 or 1. The two access transistors (n 3,n 4 ) in SRAM cell used for control to access during read and write operations of cell. The word line is used to enable the access transistors, which, in turn, controls whether the cell should be connected to the bit lines BL and BLB. These are used for data transfer in both read and write operations. During reading operation of SRAM cell the signal W L is raised and the SRAM cell discharges either BL or BLB depending on stored data at nodes q and qb. During write operation, the W L is raised and the BL and BLB are forced to either V DD or GND depending on data to be written. Table 3.1 describes the bit lines and word line in both Read and Write modes of operations. Here 0 represents zero volts or GND, 1 represents VDD. If we want read data from SRAM cell pre-charge the both the bit lines to VDD before read, apply W L to VDD and assume that the data points q = 0 and qb = 1. The qb and BLB both points are same state, so there is no change in those but at node q and bit line BL, the bit line BL tried to discharge through n 4 and n 1 but a minimum value of drain to source voltage is required to for the n 1 to discharge, this cause voltage bump at the node q, if that voltage reaches the threshold voltage it will trip the left side inverter that leads to wrong operation or wrong read or unstable read operation. So the drive strength of driver or pull-down transistor should be much high so that this will make the node q to nearly zero. So the SRAM cell will be in stable read operation. If we want to write 1 to this SRAM cell, we need to apply a 1 to the BL, 0 to the BLB and connect the W L to VDD. for good stability in both read and write operations of SRAM, the NMOS transistors of latching inverters (n 1, n 2 )are sized to be strong, PMOS (p 1, p 2 ) are made weak and NMOS (n 3, n 4 ) access transistors are sized to be of moderate strength. The Cell Ratio (CR), defined as (W/L)n 2 (W/L) n3, needs to be large to maintain read stability, while the Pull-up Ratio (P R), defined as (W/L)p 1 (W/L) n4, needs to be low for good write stability. There is a trade off with area while arriving at CR size and in our following analysis, CR is taken to be 2 and PR to be 1. The transistor sizing used in simulations in both SDG-FET based and SDG-FeFET based SRAM cell are given below ( W ) L p 1 = ( ) W L p 2 = ( W L ) n 3 = ( W L ) n 4 = 3.6um 1um and( ) W L n 1 = ( ) W L n 2 = 7.2um 1um 51

69 Figure T-SRAM cell Here the device and technology parameters used for SDG-FeFETs are channel length (L = 1µm), oxide thickness (t ox = 1nm), silicon thickness (t si = 10nm), thickness of ferroelectric layer ( = 150nm) and ferroelectric coefficients for SBT are (a = 1.3e8 m/f, b = 1.3e10 m 5 F/coul 2, c = 0) [36]. Using the same Verilog-A model, the behavior of equivalent SDG-FET can be obtained by making b and c Landau coefficients zero. The equivalent oxide thickness for the SDG-FET is taken to be t ox + a 0 ε ox where a 0 = 2.a. [36]. To get the butterfly curves or butterfly curve measurement the schematic for the read access mode is shown in Figure For the butterfly curves or butterfly curve measurement the schematic for the write mode is shown in Figure The voltage source sweeps from 0 to 1V. With the above mentioned CR, PR values the 6T-SRAM cell is simulated using smart spice simulator [43], separately with SDG-FETs and SDG-FeFETs with corresponding devices in both the SRAM cell having same W/L ratios. Table.3.2 show the results obtained from simulations, for the supply voltage of 1V. Here the static noise margin (SNM) [44] of SRAM is defined as amount of minimum noise voltage required to change the state of SRAM cell. The SNM of SRAM cell can be obtained by finding the maximum square that can be fit into the Voltage Transfer Curves (VTC) of the two cascaded inverters. Magnitude of the side of this square gives the SNM. Figure 3.19 shows the comparison of read SNM of SRAM cells designed with SDG-FeFETs and SDG-FETs respectively. From Figure 3.20 it can be seen that the stability of SRAM cell designed with SDG-FeFETs has improved by 20%, write stability by 5%, read access speed has become 6.5 times faster and the writing speed has become 1.15 times faster 52

70 Figure 3.17 The schematic of SRAM in read access mode for butterfly curve measurement 53

71 Figure 3.18 The schematic of SRAM in write mode for butterfly curve measurement 54

72 6T-SRAM Read SNM Write SNM Read access time Writing time With SDG-FETs 230 mv 425 mv 400 ps 548 ps With SDG-FeFETs 280 mv 450 mv 61.5 ps 476 ps Table 3.2 Simulated results of 6T-SRAM cell With SDG FeFET With SDG Vqb,Vq Vq,Vqb Figure T-SRAM cell SNM compared to SRAM cell with SDG-FET. Hence the SRAM cell designed with SDG-FeFETs offers high speed of operation and improved SNM compared to SRAM with SDG-FETs. Multiple publications have explored the impact of supply voltage variation and transistor sizing, on speed of operation and the SNM, for an SRAM cell designed using SDG, Fully Depleted Silicon On Insulator (FDSOI) & Bulk MOSFETs respectively [45, 46, 47, 48, 49] Below we repeat a similar analysis and compare the impact of design parameters on operation of an SRAM cell designed with SDG-FeFETs and that designed with SDG-FETs Read SNM variation with supply voltage: If the supply voltage increases the noise margins will increase. Figure 3.21 shows the variation of Read SNMs with supply voltage, extracted from simulations of the SRAM cells using both the SDG- FET and SDG-FeFET. For both the SRAMs, SNM increases with supply voltage. The SNM of SRAM with SDG-FeFETs, exceeds that of SRAM with SDG-FETs, for all supply voltages above 0.74 V. Below 0.74 V, there is a slight degradation, of about 3%, in SNM of SRAM with SDG-FeFETs compared to the SRAM with SDG-FETs. 55

73 Figure 3.20 Simulated results of 6T-SRAM cell designed with SDG-FETs and SDG-FeFETs 0.28 Read SNM with SDG FeFET with SDG Figure 3.21 Read SNM variation with power supply 56

74 0.45 write SNM with SDG FeFET with SDG Vdd Figure 3.22 Write SNM variation with power supply with SDG FeFET with SDG SNM Cell Ratio Figure 3.23 SNM variation with Cell Ratio 57

75 with SDG FeFET with SDG 0.34 SNM Vdd Vwl Figure 3.24 SNM variation with Word line Voltage with SDG FeFET with SDG Write time (ns) Vdd Figure 3.25 Write time with power supply 58

76 Read Access time (ns) with SDG FeFET with SDG Vdd Figure 3.26 Read access time with power supply Write SNM variation with supply voltage: From Figure 3.22 for both the SRAMs, the write SNM shows similar behavior as the read SNM, for variation in supply voltage. Till 0.8V of supply voltage, the write SNMs of both the SRAMs remain same and beyond it the SNM of SRAM with SDG-FeFETs, improved marginally the SRAM with SDG- FET Read SNM variation with cell ratio (CR): Increase in CR increases the strength of pull down transistor n 2. This leads to an improvement in read SNM, but area of the cell increases and speed of operation decreases. Figure 3.23 shows the variation of read SNM for increasing CR for the SRAM cell designed with SDG-FeFETs and that designed with SDG-FETs. The improvement of SNM with CR is more for the SRAM with SDG-FeFETs compared to SRAM with SDG-FETs. The difference in SNMs for the SRAMs, keeps increasing with increase in CR and it amounts to 7%, 12.5%, 12% 18.5% and 27% for CRs of 1, 1.5, 2, 2.5 and 3 respectively, computed with respect to SRAM with SDG-FETs Read SNM variation with Word line voltage variation: One of the alternatives to improve the read stability at low voltages, is reducing the word line voltage below the supply voltage without changing the SRAM design. From Figure 3.24 it is clearly shown that for both the SRAM cells, as the word line voltage decreases the read SNM increases. The SNM of 59

77 SRAM cell designed with SDG-FeFETs always exceeds the SDG-FETs and difference in SNM for the SRAM keeps decreasing Write time with supply voltage variation: Figure 3.25 shows the write time of SRAMs built with SDG-FeFETs and SDG-FETs for an increase in supply voltage. The writing speed decreases as the supply voltage scales down in both cases. However the SRAM with SDG-FeFETs takes lower time to write and it is 1.3 to 1.16 times faster than the SRAM built with SDG-FETs. The increase in speed is due to boosting of on-current that happens in SDG- FeFETs due to negative capacitance behavior [36] Read access time with supply voltage variation: Figure 3.26 shows the read access time of SRAM built with SDG-FeFETs and SDG-FETs for an increase in supply voltage. As supply voltage increases, the access time decreases in both the cases. At any given voltage, the speed of access of SRAM with SDG-FeFETs, is faster compared to the one built with SDG-FETs. The difference in speeds for the SRAM keeps decreasing with increase in voltage and SRAM with SDG-FeFETs is 11 times faster at 0.6 V and 3.8 times faster at 1.5V, compared to SRAM with SDG-FETs. As mentioned before from Figure 3.21, it could be seen that at low supply voltages, the read SNM of SDG-FeFET based SRAM is 3% less compared to SRAM with SDG-FETs. However at these voltages, the speed of operation of SDG-FeFET based SRAM is about 11 times faster, making SDG-FeFET based SRAM more suitable for advanced technology nodes. 3.5 Summary Using the long-channel surface potential, drain current and terminal charge equations derived from [36], the core compact model for SDG-FeFETs is ported on to a standard circuit simulator using the Verilog-A interface. All the basic gates, few combinational circuits, few sequential circuits and a 6T- SRAM cell built using SDG-FeFETs is simulated using this model and a comparative study of its performance, with an SRAM built with equivalent SDG-FETs, is performed as a function of supply voltage and for 6T-SRAM cell with cell ratios. It was observed that the all basic gates, combinational circuits, sequential circuits built with SDG-FeFETs have better propagation delay compared to SDG-FeFETs and cell stability of SRAM built with SDG-FeFET is better than SRAM built with SDG-FETs for all higher voltages and at lower voltages there is a marginal degradation. The read access speed and writing speeds looks significantly better in SDG-FeFET based SRAM even at low voltages, making it an attractive option for future technology nodes. 60

78 Chapter 4 Modeling of long channel Pillar Gate Ferroelectric Field Effect Transistor (Pillar-FeFET) 4.1 Introduction Internet Of Things (IOT) devices typically operate at low frequencies (MHz). The leakage power in the devices form a significant part of the total power dissipation and in certain scenarios can exceed even the switching component of the total power [50][51]. We propose Pillar FeFETs for IOT applications, since they have better subthreshold slopes and better Ion/Ioff ratio in short channels due to increased gate control given by the gate wrap-around structure. The frequency of operation in FeFETS however is limited by the switching polarization times, which is in the range of MHZ [52] and suits well for the IOT applications. To predict the performance of the circuits using the Pillar FeFETs, physics based device models are required. For this we need to solve 1-D Poisson s equation to get the surface potential in long-channel devices, and model the the drain current and quasi-static terminal charges. These are used to derive terminal charges and transcapacitances for various device terminals of Pillar FeFET. Figure 4.1 shows the 3D structure and cross sectional view of Pillar Gate Ferroelectric Field Effect Transistor (Pillar-FeFET). From the figure 4.1 the oxide layer formed on top of Si, the ferroelectric layer is formed on top of the oxide layer. Here the gates of Pillar-FeFET are symmetrical. The n+ regions show the source and drains of Pillar-FeFET. 4.2 Surface potential for Pillar-FeFET Here the conventions used in this chapter are same as in previous chapter like gate-oxide capacitance per unit area C ox is defined as ɛ ox / (R.ln (1 + t ox /R)), the structural capacitance C si is defined as ɛ si /t si. Where t si, t ox are the thicknesses and ɛ si, ɛ ox, are permittivities of Si and oxide layer respectively, T is the temperature, is the thickness of ferroelectric material, q is the electron charge, k is the Boltzmann s constant, n i is the intrinsic carrier density, V fb is the the work function difference 61

79 Figure 4.1 3D view and cross sectional view of Pillar-FeFET between semiconductor and gate, V g is the gate voltage, Q i is the inversion charge per unit gate area, V is the electron quasi-fermi potential (channel potential), L is the channel length, R is the radius of Pillar-FeFET, 2R is the diameter and ψ s, ψ d are surface potential at source, drain end respectively. From [53, 54] using Poisson s equation and the surface potential for the undoped Pillar-FeFET is expressed as d 2 ψ dr dψ r dr = q n i e q(ψ V ) kt (4.1) ɛ si ψ(r) = V + kt [ ] q ln 8B δ (1 + Br 2 ) 2 (4.2) Where δ = q 2 n i /(kt ε si ), B = (β 1) /R 2 and β is the solution using boundary condition as and ɛ ox (V g V fb V F E ψ (r = R)) t ox = ɛ si dψ dr r=r (4.3) V g V fb V F E ψ s V ox = 0 (4.4) The voltage across Ferroelectric layer is given by 62