Layout-Optimization of Power-Devices. Frederik Vanaverbeke, J. Das, H. Oprins, J. Derluyn, M. Germain, W. De Raedt
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1 Layout-Optimization of Power-Devices Frederik Vanaverbeke, J. Das, H. Oprins, J. Derluyn, M. Germain, W. De Raedt
2 Outline 1. Problem + Nomenclature 2. Unit gatewidth 3. Thermal 4. Number of unit cells 5. EM-simulations imec restricted
3 Outline 1. Problem + Nomenclature 2. Unit gatewidth 3. Thermal 4. Number of unit cells 5. EM-simulations imec restricted
4 Problem Description + Nomenclature A device = N unit cells, each having n gate-fingers of length w gu Total gatewidth is w=n x n x w gu. And w~pout Lgg=finger spacing?: How to choose N,n,w gu, L gg, -> EM effects -> Thermal effects imec restricted
5 Outline 1. Problem + Nomenclature 2. Unit gatewidth w gu 3. Thermal 4. Number of unit cells 5. EM-simulations imec restricted
6 Unit gatewidth w gu IDS modulation: UNIFORM over the gate finger => Phase rotation & hence length must be limited. Finger ~ transmission line voltage: Z ( s) E ( s) γ ( s) x γ ( s)(2 L x) 0 G L v( x, s) =. γ ( s) 2 L Z 0 ( s) + Z G ( s) 1 ΓL ( s) ΓG ( s) e e + Γ ( s) e difference in phase between v( 0, s) and v( w, s) < π / 16 gu imposes a limit to w gu γ (complex number): Through simulation By modeling an infinitesimal section of the line imec restricted
7 Unit gatewidth w gu γ (complex number): Through simulation in Ansoft s HFSS Infinitesimal section of the line; values from transistor extractions ~ g R ~ s L g R + γ = α + jβ = ( R + R + jωl ) jωc g s g gs ~ C gs Resulting maximum values for w gu in μm: imec restricted
8 Outline 1. Problem + Nomenclature 2. Unit gatewidth w gu 3. Thermal Lgg 4. Number of unit cells 5. EM-simulations imec restricted
9 Thermal Lgg From a previous Imec study [J. Das et. Al, IEEE Trans. Electron Devices, 53 (11), pp ,2006] Relationship Lgg, Temperature and w gu by means of 3D-simulations: Si: W gu = 100 μm Si: W gu = 200 μm Si: W gu = 300 μm SiC: W gu = 100 μm SiC: W gu = 200 μm SiC: W gu = 300 μm Temperature (C) Limiting the temperature to 160 o C imposes a minimum to L gg for a certain w gu The longer the finger, the further they have to be separated from each other Gate pitch L gg (mm) imec restricted
10 Outline 1. Problem + Nomenclature 2. Unit gatewidth w gu 3. Thermal Lgg 4. Number of unit cells N (and n) 5. EM-simulations imec restricted
11 Number of unit cells N (and n) Choose that combination of N, n and w gu that minimizes the chip area through L p = N 2 ( n 1) L gg + w g N n + N 1 L 2 dd taking into account N is integer and n is even w gu has a maximum => a minimum number of fingers is necessary => N x n has a minimum value The cells are measurable by probes => N has a minimum value => Graphical method imec restricted
12 Number of unit cells N (and n) L p,tot in [mm] N L p,tot as a function of N and n. The N,n-plane Working area Forbidden area Projection of Lp on N,n-plane 2. Plot the discrete working grid (cyan diamonds) 3. w gu has maximum N x n is minimum~hyperbole 4. On-wafer characterization Minimum value for N 5. Pick that point in the working area, where L p is minimal n 15 n N imec restricted
13 Outline 1. Problem + Nomenclature 2. Unit gatewidth w gu 3. Thermal Lgg 4. Number of unit cells N (and n) 5. EM-simulations imec restricted
14 EM-simulations Devices in Microstrip Packages Gate,Source,Drain on top of die (CPW) <-> Ground=bottom of MS Package Source-areas connected to bottom of MS Package: Wirebonds Via s Source-Inductance kills performance imec restricted
15 EM-simulations Approximation of MAG: G a max 4G ds R gs + R s + R g ωt L + 2 s ft f + 2 2ω C T gd ( R + R + 2R + ω L ) gs s g T s L s should be minimized L s doesn t scale and is not predictable Any L is proportional with area of membrane of mag flux Surface is difficult to determine because More than 1 via s or WB s (+ coupling) Common for the gate-source path and drain-source path Airbridges => EM-simulations imec restricted
16 EM-simulations S-PARAMETERS VG<VT zero Measurements 3D Simulations (HFSS) Extraction Procedure EQUIV. CIRCUIT Extrinsics (ao L s ) imec restricted
17 EM-simulations Effect of via s <=> they conduct RF Current Excitation of waveports is key No RF current is forced through the via s => Effect is not simulated CPW imec restricted
18 EM-simulations Effect of via s <=> they conduct RF Current Excitation of waveports is key MS CPW imec restricted
19 EM-simulations Applied to 4 configurations AODWB AOGDWB Ls for several types of layouts AODV AOGDV Ls in ph AODWB AOGDWB AODV AOGDV G a max 4Gds R gs f T f ωt Ls + Rs + Rg + + 2ω T C 2 2 gd ( R + R + 2R + ω L ) gs s g T s MAG in [db] MAG afo L s for the designs at the 3 frequencies 2GHz (6x300μm) 5GHz (6x200μm) 10GHz (6x100μm) L s in [ph] imec restricted
20 imec restricted
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