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1 doi:.38/nature09979 I. Graphene material growth and transistor fabrication Top-gated graphene RF transistors were fabricated based on chemical vapor deposition (CVD) grown graphene on copper (Cu). Cu foil was placed in a quartz furnace tube at - 6 Torr. After evacuation, the Cu foil was heated to 875 o C in forming gas and kept at this temperature for 30 minutes to reduce native CuO and increase the Cu grain size. After reduction the Cu foil was exposed to ethylene at 975 C for minutes. The sample was cooled down in forming gas (6 sccm, 20 mtorr). PMMA was spin-coated on top of the graphene layer formed on one side of the Cu foil. The Cu foil was then dissolved in M iron chloride. The remaining graphene/pmma layer was washed with deionized (DI) water water, M HCl and DI water and transferred to the desired substrate. ubsequently, the PMMA was dissolved in hot acetone (80 o C) for one hour. The substrate with graphene was rinsed in methanol and dried in a stream of nitrogen. The CVD graphene was characterized with Raman spectroscopy on four different sites across the wafer as shown in Fig.. The ratio of 2D peak to G peak confirms the single layer nature of the CVD-graphene []. Graphene RF transistors were built using a top-down approach on DLC substrate grown on a high resistivity i susbtrate as shown in Fig. 2a. A Leica Vb6

2 E-beam writer was used for patterning with PMMA as the resist. The typical dose and current during the writing are 200 μc/cm 2 and -40 na, respectively. Dual-channel RF graphene devices were designed with different gate lengths from 550 nm, 40nm, nm, 80 nm and 40 nm with a fixed gate width of 30 μm. A EM image of a typical long channel device with 550 nm channel length is shown in Fig. 2b. The contact resistance is estimated to be 600 Ω μm and Hall mobility is around cm 2 /Vs at zero top gate bias (high density region). Top-gate capacitance is about 9-7 nf/μm 2 from a combination of nm oxidized Al layer and 5 nm ALD Al 2 O 3. It is noted here that the CVD-graphene here went through the iron chloride copper etching process which usually introduced ionic doping. Also the top-gate stack with E-beam evaporated and then oxidized Al layer will also introduce impurity doping. The large Dirac point shift of the finished devices as shown in Fig. (e) mostly originates from the above two factors instead of the DLC substrate. As a comparison, another sample with same CVD-graphene transferred to ic substrate, usually considered to be of high quality and with few traps, also shows similar amount of Dirac point shift. D G 2D Counts (a.u.) Raman hift (cm - ) Figure Raman spectroscopy of the CVD-graphene grown on copper from 4 different sites on the same sample. The ratio of G peak to 2D peak reveals the single layer property. 2

3 a b Figure 2 Images of finished graphene RF devices on a DLC substrate. a, The finished chip of graphene RF transistors on DLC substrate. b, A EM image of a typical long channel device with gate length of 550 nm. The scale bar is 400 nm. II. High frequency measurement and analysis on maximum oscillation frequency cattering () parameter measurement was taken using an Agilent network analyzer. The short circuit current gain can calculated from the obtained parameters using the 22 following formula: h2 ( )( ) , 2 can be converted into db by 20 * log. The current is then plotted against the frequency in log scale, following a /f dependence, which is equivalent to -20 db/dec dependence. The cut off frequency f T is the frequency at which the current is equal to. A commonly used de-embedding procedure using open and short structures is adopted to obtain the intrinsic RF performance. The de-embedding mainly follows this equation: Y [( Y Y ) ( Y Y ) ]. The current gain versus frequency transistor DUT open short open before de-embedding for two representative short channel devices with gate length of 40 nm and 40 nm are shown in Fig

4 a b f T =9.3 GHz L g =40 nm@ 300K Before de-embedding f T = 5 GHz L g = K Before de-embedding 0. Figure 3 Plot of short circuit current gain versus frequency before de-embedding at room temperature at V gs =-8V and V ds =.6 V. a, The extrinsic f T is 9.3 GHz for the 40 nm device. b, The extrinsic f T is 5 GHz for the 40 nm device. In real application, there is another important figure-of-merit called maximum oscillation frequency, which can be determined from the power gain. The maximum available power gain (MAG) is calculated from parameters from the following equation [2]. MAG K K 2 2, where K is the stability factor and 2 K D , where the determinant D 22 2 * 2. Another often cited power gain is Mason s unilateral power gain and it is defined as: U k Re( ) 2 2 2, Both MAG and U can be converted into db by * log MAG and they should follow a /f or -20 db/dec dependence for a well-behaved transistor. The maximum oscillation 4

5 frequency f MAX is defined as the frequency at which the power gain equals to and the results from both MAG and U are expected to be similar. As a fundamental characteristic of a transistor, f MAX holds the physical significance to be the maximum oscillation frequency. f MAX can also be obtained without using parameters by the following equation for field-effect transistors [3]. f MAX ft 2 g ( R R R ) 2 f C R D Gate i T GD Gate, where g D is differential source-drain conductance, R s is the source resistance, R i is the channel-sided charging resistance of the gate-source capacitance, C GD is the gate to drain capacitance and R Gate is the gate resistance which mainly depends on the gate metal thickness and area. As shown in Fig. 4, we have obtained a high f MAX value of more than 20 GHz for the 550 nm device without any optimization of gate structure. Despite the lack of clear current saturation, this large f MAX shows the performance potential for graphene transistors. It is expected that f MAX can be further enhanced by optimizing the gate structure and improving the saturation behavior. a Gain L g =550 nm V ds =.6V V gs =-6V MAG /2 U /2 f T =26 GHz b Gain 0 L g =40 nm V ds =.6V V gs =-8V MAG /2 U /2 f T =70 GHz f max =20 GHz f max =3 GHz 0 5

6 Figure 4 Plot of short circuit current gain (black) and power gain (red and blue) versus frequency. a, The f T is 26 GHz and f MAX is 20 GHz for the 550 nm device. b, The f T is 70 GHz and f MAX is 3 GHz for the 40 nm device. Extrinsic f MAX before de-embedding for the 550 nm device is also shown in Fig. 5 also using MAG and U. Compared to the intrinsic 20 GHz, the extrinsic f MAX is about.5 GHz, which is also highest reported value thus far. MAG /2 U /2 Gain f max =.5 GHz L g =550 nm@ 300K Before de-embedding Figure 5 Plot of power gain versus frequency before de-embedding at room temperature for the 550 nm device. An extrinsic f MAX of.5 GHz is achieved at V gs =-6V and V ds =.6V. III. High frequency measurement at low temperatures Thermal variation of the vector network analyzer (VNA) itself and the cables can cause measurement uncertainties when a standard VNA calibration is performed. To obtain the most accurate microwave measurements at a certain temperature, calibrations are often repeated before taking sensitive measurement. Mechanical and electrical changes in the RF measurement system such as cables, probes and open/short structures can lead to large measurement errors with varying temperatures. It is imperative to perform system 6

7 calibration and open-short measurements for each temperature once the components reach a stable thermal equilibrium. a b c K 50 K 4.3 K GHz 2 GHz 2 GHz 3.5 GHz 3 GHz 2 GHz Figure 6 The extrinsic current gain before de-embedding versus frequency for a 550 nm device. a, 300 K; b, 50 K; c, 4.3 K. The gate voltage steps from -8 to 0 V and the drain voltage is.6 V. The /f dependence holds well across all the temperatures and has the similar gate voltage dependence. These are consistent with the intrinsic current gain plots after de-embedding versus frequency as shown in the main text. A system calibration carried out at 300 K will lead to large inaccuracy for a measurement taken at 4.2 K. In our temperature dependent RF measurements, repeated calibrations were carried out as stated above to ensure reliable and accurate test results. imilarly, efforts need to be taken during the de-embedding procedures to ensure the accuracy of intrinsic results. As shown in Fig. 6, the extrinsic f T values of a 550 nm device measurement at each temperature have the similar gate voltage dependence and result in consistent intrinsic f T values after de-embedding (Intrinsic f T figures are shown in Fig. 4 in the main text). 7

8 The weak temperature dependence largely benefits from the better surface properties of the DLC substrate compared to those of an io 2 substrate. To further explore the surface trapping behavior for different substrates, a side-by-side comparison of graphene transistors fabricated on DLC substrate and io 2 substrate is shown in Fig. 7. Note here that these two sets of devices are made in parallel with identical fabrication procedures and graphene materials. The representative output characteristics of the 550 nm device on io 2 substrate are given in Fig. 7 (a). These characteristics show large hysteresis and change in the device behavior after sweeps at high drain bias. The current exhibits abnormal drain dependence (as indicated by the red arrow) when biased at around 2.5 V for the first sweep (left panel). Different output behavior is observed for the second and subsequent sweeps during which the abnormal drain dependence is absent (right panel). This indicates that large numbers of traps were involved in the transport process when the graphene devices on io 2 were first biased at V ds of 2.5 V, which is within the typical operating range for RF graphene devices. This result is consistent with the experimental work of Ref. [4] that shows strong field-effect induced trapping processes in graphene devices on io 2 substrate under high bias. On the contrary, this abnormal output behavior originating from trapping processes is absent in the device on DLC as shown in Fig. 7 (b), which indicates its advantages in terms of trap density and appropriateness for highfield operation. Devices on DLC showed reproducible output characteristics after repeated sweeps under high bias. In addition, the devices on DLC show much larger current modulations than on io 2. This is attributed to a better mobility and carrier velocity on DLC substrate resulting from less impurity and phonon scattering. 8

9 a b Drain current ma/m) Drain voltage (V) Drain voltage (V) Drain current (mam) Figure 7 The comparison of output characteristics of 550 nm graphene devices on DLC and io 2 substrates with gate voltage sweeping 8 V from Dirac point. a, The graphene device on io 2 substrate shows large hysteresis and change of device characteristics after sweeps at high drain bias. The current exhibits abnormal drain dependence (as indicated by the red arrow) when biased at around 2.5 V for the first sweep (left panel). Drastically different output behavior is observed for the second and subsequent sweeps in which the abnormal drain dependence is absent (right panel). This indicates that large number traps participated in the transport when the graphene device on io 2 was first biased at high V ds. b, The device on DLC substrate shows little change in its output characteristics when biased at around 2.5 V for the first sweep (left panel) and second sweep (right panel), indicating minimal trapping/de-trapping processes. * yming@us.ibm.com (Y.-M. L) and avouris@us.ibm.com (P.A.) References 9

10 [] Li, X.. et al. Large-Area ynthesis of High-Quality and Uniform Grapene Films on Copper Foils. cience, 324, (2009). [2] Gupta, M.. Power Gain in Feedback Amplifiers, a Classic Revisited. IEEE Trans. Microwave theory and Techniques, 40, (992). [3] ze,. M. & Ng, K. K. Physics of emiconductor Devices, Third Edition, Wiley- Interscience (2006). [4] Chiu, H. -Y., Perebeinos, V., Lin, Y. -M. & Avouris, P. Controllable p-n Junction Formation in Monolayer Graphene Using Electrostatic ubstrate Engineering. Nano Lett., (20).