An 85%-Efficiency Fully Integrated 15-Ratio Recursive Switched- Capacitor DC-DC Converter with 0.1-to-2.2V Output Voltage Range
|
|
|
- Marlene James
- 5 years ago
- Views:
Transcription
1 An 85%-Efficiency Fully Integrated 15-Ratio Recursive Switched- Capacitor DC-DC Converter with 0.1-to-2.2V Output Voltage Range Loai G. Salem and Patrick P. Mercier University of California, San Diego ISSCC 2014
2 Higher-frequency exceeds thermal limits High performance & low power: Parallel processing (multi-core) Per-module voltage scaling for adapting power with processing load Fully-integrated DC-DC Converters are required No. of processing engines exponentially increases to meet customer expectations DC/DC ITRS DC/DC T5 SPARC, 16 Core, ISSCC 13 2 of 35
3 On-Die DC-DC Converters Recursive SC Topology All Digital Binary Search Control Measurement Results Conclusions 3 of 35
4 A resistive divider Compact Very lossy No switching noise Fast 2 V drop R pass when V DD goes far below V IN 4 of 35
5 How to convert input DC voltage? Switched Capacitor - + V in - 5 of 35
6 How to convert input DC voltage? Switched Capacitor Voltage doubler fixed 1:2 conversion + V in - V IN 5 of 35
7 How to convert input DC voltage? Swap V IN and R L for V IN /2 instead of a 2V IN swap = 2V IN = V IN /2 5 of 35
8 Why SC ɳ 100%? Large decoupling cap C out R L R L 6 of 35
9 Why SC ɳ 100%? q q out = 2q V IN q = V IN /2 2q E in = E out q q q R L R L Charging discharging 6 of 35
10 Why SC ɳ 100%? Equivalent q q ΔV ½ CΔV 2 f sw f sw => ΔV C => ΔV q q q E loss = CΔV 2 No R on dependence R L R L Charging discharging 6 of 35
11 Loss can be modeled by R out f sw This is how to provide continuous conversion: change R out, like an LDO R out ΔV decreases 2R on f sw 7 of 35
12 Efficiency vs. at V in = 2.5V 2:1 SC 3:2 SC 3:1 SC Requires more ratios 8 of 35
13 Problem: Given certain C, re-use that to produce different ratios 1/3 1/2 3/5 2/3 No. Of caps and switches increases exponentially Each ratio requires a unique arrangement, which is difficult to reuse among other ratios Higher no. of ratios requires a Modular topology 9 of 35
14 Conventional 4:1 = V IN /4 Cap no. 3 SW no Parallel Series 10 of 35
15 Ratio = 1/4 Connect a second 2:1 cell (C 2 ) between cell (C 1 ) output & GND V IN /2 SP 1/4 New 1/4 Cap no. 3 2 SW no = V IN /4 11 of 35
16 Ratio = 3/4 Connect the second 2:1 cell (C 2 ) between V IN & cell (C 1 ) output SP 3/4 New 3/4 Cap no. 3 2 SW no V IN /2 = (V in +V in /2)/2 = 3V IN /4 12 of 35
17 1/4, 3/4 are realized, how to get 1/2 Cells Stacked for 3/4 = 3V IN /4 Route from 1 st cell for 1/2 V IN /2 Cells cascaded for 1/4 V IN /2 = V IN /4 = V IN /2 Wastes the capacitance of the 2 nd cell, lower η 13 of 35
18 1/4, 3/4 are realized, how to get 1/2 Cells Stacked for 3/4 Cells in parallel for 1/2 = 3V IN /4 V IN /2 Cells cascaded for 1/4 V IN /2 = V IN /4 = V IN /2 Recursive Inter-cell Connection:100% of the Caps used among all ratios 14 of 35
19 How to realize 1/2, the switch detail Ratio = 1/2 two cells in parallel 15 of 35
20 How to realize 1/4, the switch detail Ratio Reconfiguration Switches 15 of 35
21 How to realize 1/4, the switch detail q Disabled S R2 & S R3 work as OUTPUT switches 15 of 35
22 How to realize 1/4, the switch detail Disabled q Disabled Disabled S R1 works as INPUT switch S1 15 of 35
23 How to realize 1/4, the switch detail Disabled q MID = MID/2 Ratio = 1/4 two cells in cascade 15 of 35
24 How to realize 3/4, the switch detail q Disabled Disabled S R4 works as GND switch S4 Disabled 15 of 35
25 How to realize 3/4, the switch detail q MID Disabled = (V IN +MID)/2 Ratio = 3/4 two cells are stacked 15 of 35
26 Adding a third 2:1 SC cell: resolution = V in /2 3 V in V in /2 V in /4 = V in /8 16 of 35
27 Realizing 3/8 ratio 3V in /4 = 3V in /8 Move 2 nd cell UP 17 of 35
28 Another way to realize 3/8 ratio V in V in /2 = (V in /2+V in /4)/2 =3V in /8 V in /4 Move 3 rd cell UP 18 of 35
29 Which one is better to realize 3/8 ratio? 3V IN /8 3V IN /8 V in 3q/4 q/2 q/2 q/4 q q/4 q q/2 19 of 35
30 Which one is better to realize 3/8 ratio? Binary relative sizing C/4 C/2 q/4 q/2 C q V in 3q/4 1 st Cell is loaded by extra q/2 q/2 q/4 q/2 q For same q output, SC is less loaded, thus lower losses Higher η Maximizing V in & GND connections maximizes η 20 of 35
31 Now 1/8, 3/8, 5/8, 7/8 are realized, how to achieve 1/2 using 3 cells? Recursion: Connect 3 cells in parallel for 1/2 Cells connected in cascade for n odd /8 21 of 35
32 Now 1/8, 3/8, 5/8, 7/8, and 1/2 are realized, what about 1/4, 3/4? VSlice 3 rd out = 3V in cell /4 into 2 cells C2 C1 C3 2 C3 1 Put the 2 slices in cascade & in parallel to the other 2 cells cascade C3 1 C1 V in /2 C3 2 C2 = 3V in /4 22 of 35
33 A 4-bit Recursive SC topology is implemented Balance between complexity and flat η Realizing 15-ratio, of high η by: Recursive inter-cell connection for 100% cap utilization Maximizing V in & GND connections Binary relative sizing 23 of 35
34 Proposed 4-bit RSC 2:1 3:2 4:3 16:15 3:1 4:1 4.4% predicted ɳ by model All topologies Tech. 0.25µm 16:3 8:1 falls bellow 3-ratio linear regulation Cap 3nF V in 2.5V I L 2mA For same silicon area: widest operating range, highest average efficiency 24 of 35
35 Compare V ref (desired output) with levels from a resistor string to find desired ratio 0 V ref 1 25 of 35
36 Challenge of large number of ratios Decision element Ratio threshold generation For 8-bit resolution~256 accurate resistors and comparators are needed 26 of 35
37 Ratios threshold levels mismatch due to SC R out R out3 R out2 V ref R out changes from one ratio to another R out1 27 of 35
38 Solution: Ratios threshold levels are produced by the SC itself Switching at highest f sw, R out is min SC outputs the max Vout for certain n/m RATIO 28 of 35
39 Binary Search Algorithm: Strobe Reset: R = 1/2 Max resolution V in /2 2 V in Apply Ratio: = RxV in End No Depth<=4 No resistor string 1 comparator & simple gates No R out mismatch Go to higher binary ratio R n = (1+R n-1 )/2 No Yes >V ref Yes Go to lower binary ratio R n = R n-1 /2 29 of 35
40 8 µs response time 1/2 3/4 7/8 13/16 7/8 V ref ~8µs 30 of 35
41 0.25um 2.5V bulk CMOS MIM ~ 0.9 ff/um 2 4C/45 2C/15 C/15 8C/45 8 2:1 cells are used to enable recursion 32C/ C/105 8C/ C/315 Cells are binary weighted for optimal relative sizing 31 of 35
42 0.25µm: Cap = 3nF, V in = 2.5, I L = 2mA 2:1 3:2 4:3 16:15 4:1 3:1 predicted ɳ by model 16:3 8:1 Measurements within 1% of the Model ɳ peak = 85% For same silicon area: widest operating range, highest average efficiency 32 of 35
43 0.25µm: C = 3nF, V in = 2.5, Ratio = 1/2 30µA 1mA Switching losses scale with lower power levels 33 of 35
44 Tracking an input stair control voltage Binary search 500µs stair control voltage 34 of 35
45 A new Modular SC topology comprising individual 2:1 SC High η through: Recursive interconnection achieving 100% cap utilization Maximizing V in & GND connections for minimum overhead charge through the SC Optimal resource allocation (C,G) through BINARY relative sizing Highest average ɳ & widest operating range amongst other SC topologies for same silicon area 35 of 35
EE247 Lecture 16. Serial Charge Redistribution DAC
EE47 Lecture 16 D/A Converters D/A examples Serial charge redistribution DAC Practical aspects of current-switch DACs Segmented current-switch DACs DAC self calibration techniques Current copiers Dynamic
Topic 4. The CMOS Inverter
Topic 4 The CMOS Inverter Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk Topic 4-1 Noise in Digital Integrated
Last Lecture. Power Dissipation CMOS Scaling. EECS 141 S02 Lecture 8
EECS 141 S02 Lecture 8 Power Dissipation CMOS Scaling Last Lecture CMOS Inverter loading Switching Performance Evaluation Design optimization Inverter Sizing 1 Today CMOS Inverter power dissipation» Dynamic»
Very Large Scale Integration (VLSI)
Very Large Scale Integration (VLSI) Lecture 4 Dr. Ahmed H. Madian Ah_madian@hotmail.com Dr. Ahmed H. Madian-VLSI Contents Delay estimation Simple RC model Penfield-Rubenstein Model Logical effort Delay
Switched-Capacitor Circuits David Johns and Ken Martin University of Toronto
Switched-Capacitor Circuits David Johns and Ken Martin University of Toronto (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) University of Toronto 1 of 60 Basic Building Blocks Opamps Ideal opamps usually
THE INVERTER. Inverter
THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)
FAN ma, Low-IQ, Low-Noise, LDO Regulator
April 2014 FAN25800 500 ma, Low-I Q, Low-Noise, LDO Regulator Features V IN: 2.3 V to 5.5 V V OUT = 3.3 V (I OUT Max. = 500 ma) V OUT = 5.14 V (I OUT Max. = 250 ma) Output Noise Density at 250 ma and 10
Power Dissipation. Where Does Power Go in CMOS?
Power Dissipation [Adapted from Chapter 5 of Digital Integrated Circuits, 2003, J. Rabaey et al.] Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit
UPC. 5. Properties and modeling of onchip Power Distribution Networks. Decoupling capacitance
5. Properties and modeling of onchip Power Distribution Networks Decoupling capacitance Electrical properties of on-chip PDN: capacitance Capacitance associated with PDN: Gates Interconnects Well (in standard
Lecture 320 Improved Open-Loop Comparators and Latches (3/28/10) Page 320-1
Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 321 LECTURE 32 IMPROVED OPENLOOP COMPARATORS AND LATCHES LECTURE ORGANIZATION Outline Autozeroing Hysteresis Simple es Summary CMOS Analog
COMP 103. Lecture 16. Dynamic Logic
COMP 03 Lecture 6 Dynamic Logic Reading: 6.3, 6.4 [ll lecture notes are adapted from Mary Jane Irwin, Penn State, which were adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] COMP03
System on a Chip. Prof. Dr. Michael Kraft
System on a Chip Prof. Dr. Michael Kraft Lecture 3: Sample and Hold Circuits Switched Capacitor Circuits Circuits and Systems Sampling Signal Processing Sample and Hold Analogue Circuits Switched Capacitor
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
FEATURES Six fixed voltage regulators Three microprocessor-controlled regulators Two V P -state controlled regulators One fixed voltage regulator (can operate during load dump or thermal shutdown) V P1
Benefits of Stacked-Wafer Capacitors for High-Frequency Buck Converters
Benefits of Stacked-Wafer Capacitors for High-Frequency Buck Converters Michael W. Baker, PhD Maxim Integrated Power SoC Northeastern University, Boston MA. October 7, 2014 Mobile Device Trends Power Management
DATA SHEET. TDA3601Q TDA3601AQ Multiple output voltage regulators INTEGRATED CIRCUITS Dec 13
INTEGRATED CIRCUITS DATA SHEET Supersedes data of September 1994 File under Integrated Circuits, IC01 1995 Dec 13 FEATURES Six fixed voltage regulators Three microprocessor-controlled regulators Two V
Topics. Dynamic CMOS Sequential Design Memory and Control. John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut
Topics Dynamic CMOS Sequential Design Memory and Control Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance
Digital Integrated Circuits. The Wire * Fuyuzhuo. *Thanks for Dr.Guoyong.SHI for his slides contributed for the talk. Digital IC.
Digital Integrated Circuits The Wire * Fuyuzhuo *Thanks for Dr.Guoyong.SHI for his slides contributed for the talk Introduction The Wire transmitters receivers schematics physical 2 Interconnect Impact
[1] (b) Fig. 1.1 shows a circuit consisting of a resistor and a capacitor of capacitance 4.5 μf. Fig. 1.1
![[1] (b) Fig. 1.1 shows a circuit consisting of a resistor and a capacitor of capacitance 4.5 μf. Fig. 1.1](/thumbs/81/83276652.jpg "[1] (b) Fig. 1.1 shows a circuit consisting of a resistor and a capacitor of capacitance 4.5 μf. Fig. 1.1")
1 (a) Define capacitance..... [1] (b) Fig. 1.1 shows a circuit consisting of a resistor and a capacitor of capacitance 4.5 μf. S 1 S 2 6.3 V 4.5 μf Fig. 1.1 Switch S 1 is closed and switch S 2 is left
Spurious-Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4GHz Fractional-N PLL. University of California at San Diego, La Jolla, CA
Spurious-Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4GHz Fractional-N PLL Kevin Wang 1, Ashok Swaminathan 1,2, Ian Galton 1 1 University of California at San Diego, La Jolla, CA 2 NextWave
CMOS Inverter (static view)
Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:
CMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)
CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN
RP mA, Ultra-Low Noise, Ultra-Fast CMOS LDO Regulator. General Description. Features. Applications. Ordering Information. Marking Information
RP122 3mA, Ultra-Low Noise, Ultra-Fast CMOS LDO Regulator General Description The RP122 is designed for portable RF and wireless applications with demanding performance and space requirements. The RP122
Analysis and Design of Differential LNAs with On-Chip Transformers in 65-nm CMOS Technology
Analysis and Design of Differential LNAs with On-Chip Transformers in 65-nm CMOS Technology Takao Kihara, Shigesato Matsuda, Tsutomu Yoshimura Osaka Institute of Technology, Japan June 27, 2016 2 / 16
PARALLEL DIGITAL-ANALOG CONVERTERS
CMOS Analog IC Design Page 10.2-1 10.2 - PARALLEL DIGITAL-ANALOG CONVERTERS CLASSIFICATION OF DIGITAL-ANALOG CONVERTERS CMOS Analog IC Design Page 10.2-2 CURRENT SCALING DIGITAL-ANALOG CONVERTERS GENERAL
Where Does Power Go in CMOS?
Power Dissipation Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit Path between Supply Rails during Switching Leakage Leaking
EE141Microelettronica. CMOS Logic
Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit
Low Power VLSI Circuits and Systems Prof. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur
Low Power VLSI Circuits and Systems Prof. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Lecture No. # 08 MOS Inverters - III Hello, and welcome to today
Digital Integrated Circuits 2nd Inverter
Digital Integrated Circuits The Inverter The CMOS Inverter V DD Analysis Inverter complex gate Cost V in V out complexity & Area Integrity and robustness C L Static behavior Performance Dynamic response
The CMOS Inverter: A First Glance
The CMOS Inverter: A First Glance V DD V in V out C L CMOS Properties Full rail-to-rail swing Symmetrical VTC Propagation delay function of load capacitance and resistance of transistors No static power
S-1000 Series ULTRA-SMALL PACKAGE HIGH-PRECISION VOLTAGE DETECTOR. Features. Applications. Packages. Seiko Instruments Inc. 1.
S-1000 Series www.sii-ic.com ULTRA-SMALL PACKAGE HIGH-PRECISION VOLTAGE DETECTOR Seiko Instruments Inc., 2004-2015 Rev.3.1_00 The S-1000 series is a series of high-precision voltage detectors developed
EECS 141: FALL 05 MIDTERM 1
University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 11-1:3 Thursday, October 6, 6:3-8:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION
Homework Assignment #3 EE 477 Spring 2017 Professor Parker , -.. = 1.8 -, 345 = 0 -
Homework Assignment #3 EE 477 Spring 2017 Professor Parker Note:! " = $ " % &' ( ) * ),! + = $ + % &' (, *,, -.. = 1.8 -, 345 = 0 - Question 1: a) (8%) Define the terms V OHmin, V IHmin, V ILmax and V
PART. Maxim Integrated Products 1
9-79; Rev ; 9/ SC7 Inverting Charge Pumps General Description The / monolithic, CMOS chargepump voltage inverters in the ultra-small SC7 package feature a low Ω output resistance, permitting loads up to
D/A Converters. D/A Examples
D/A architecture examples Unit element Binary weighted Static performance Component matching Architectures Unit element Binary weighted Segmented Dynamic element matching Dynamic performance Glitches Reconstruction
Announcements. EE141- Fall 2002 Lecture 7. MOS Capacitances Inverter Delay Power
- Fall 2002 Lecture 7 MOS Capacitances Inverter Delay Power Announcements Wednesday 12-3pm lab cancelled Lab 4 this week Homework 2 due today at 5pm Homework 3 posted tonight Today s lecture MOS capacitances
EEC 118 Lecture #6: CMOS Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #6: CMOS Logic Rajeevan mirtharajah University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW 3 due this
A LDO Regulator with Weighted Current Feedback Technique for 0.47nF-10nF Capacitive Load
A LDO Regulator with Weighted Current Feedback Technique for 0.47nF-10nF Capacitive Load Presented by Tan Xiao Liang Supervisor: A/P Chan Pak Kwong School of Electrical and Electronic Engineering 1 Outline
DC and Transient. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr.
DC and Transient Courtesy of Dr. Daehyun Lim@WSU, Dr. Harris@HMC, Dr. Shmuel Wimer@BIU and Dr. Choi@PSU http://csce.uark.edu +1 (479) 575-604 yrpeng@uark.edu Pass Transistors We have assumed source is
Switched Capacitor DC/DC Marx Converter Loss Models Advanced Power Electronics Final Project FT08
Switched Capacitor DC/DC Marx Converter Loss Models 6.987 Advanced Power Electronics Final Project FT08 July 14, 2010 John J. Cooley Massachusetts Institute of Technology 1 Introduction The primary goal
EE115C Winter 2017 Digital Electronic Circuits. Lecture 6: Power Consumption
EE115C Winter 2017 Digital Electronic Circuits Lecture 6: Power Consumption Four Key Design Metrics for Digital ICs Cost of ICs Reliability Speed Power EE115C Winter 2017 2 Power and Energy Challenges
Spiral 2 7. Capacitance, Delay and Sizing. Mark Redekopp
2-7.1 Spiral 2 7 Capacitance, Delay and Sizing Mark Redekopp 2-7.2 Learning Outcomes I understand the sources of capacitance in CMOS circuits I understand how delay scales with resistance, capacitance
Advanced Current Mirrors and Opamps
Advanced Current Mirrors and Opamps David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 26 Wide-Swing Current Mirrors I bias I V I in out out = I in V W L bias ------------
MM74C150 MM82C19 16-Line to 1-Line Multiplexer 3-STATE 16-Line to 1-Line Multiplexer
MM74C150 MM82C19 16-Line to 1-Line Multiplexer 3-STATE 16-Line to 1-Line Multiplexer General Description The MM74C150 and MM82C19 multiplex 16 digital lines to 1 output. A 4-bit address code determines
Miscellaneous Lecture topics. Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.]
![Miscellaneous Lecture topics. Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.]](/thumbs/81/84503671.jpg "Miscellaneous Lecture topics. Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.]")
Miscellaneous Lecture topics Mary Jane Irwin [dapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] MOS Switches MOS transistors can be viewed as simple switches. In an N-Switch, the
Itanium TM Processor Clock Design
Itanium TM Processor Design Utpal Desai 1, Simon Tam, Robert Kim, Ji Zhang, Stefan Rusu Intel Corporation, M/S SC12-502, 2200 Mission College Blvd, Santa Clara, CA 95052 ABSTRACT The Itanium processor
Digital Electronics Part II - Circuits
Digital Electronics Part - Circuits Dr.. J. Wassell Gates from Transistors ntroduction Logic circuits are non-linear, consequently we will introduce a graphical technique for analysing such circuits The
Scaling of MOS Circuits. 4. International Technology Roadmap for Semiconductors (ITRS) 6. Scaling factors for device parameters
1 Scaling of MOS Circuits CONTENTS 1. What is scaling?. Why scaling? 3. Figure(s) of Merit (FoM) for scaling 4. International Technology Roadmap for Semiconductors (ITRS) 5. Scaling models 6. Scaling factors
5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1
5.0 CMOS Inverter W.Kucewicz VLSICirciuit Design 1 Properties Switching Threshold Dynamic Behaviour Capacitance Propagation Delay nmos/pmos Ratio Power Consumption Contents W.Kucewicz VLSICirciuit Design
EEC 116 Lecture #5: CMOS Logic. Rajeevan Amirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation
EEC 116 Lecture #5: CMOS Logic Rajeevan mirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW
Pipelined multi step A/D converters
Department of Electrical Engineering Indian Institute of Technology, Madras Chennai, 600036, India 04 Nov 2006 Motivation for multi step A/D conversion Flash converters: Area and power consumption increase
Section 4. Nonlinear Circuits
Section 4 Nonlinear Circuits 1 ) Voltage Comparators V P < V N : V o = V ol V P > V N : V o = V oh One bit A/D converter, Practical gain : 10 3 10 6 V OH and V OL should be far apart enough Response Time:
Integrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 7 Interconnections 1: wire resistance, capacitance,
VLSI GATE LEVEL DESIGN UNIT - III P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT
VLSI UNIT - III GATE LEVEL DESIGN P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) contents GATE LEVEL DESIGN : Logic Gates and Other complex gates, Switch logic, Alternate gate circuits, Time Delays, Driving large
CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic
CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic [dapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey,. Chandrakasan,. Nikolic] Sp11 CMPEN 411
ENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view)
ENGR89 Digital VLSI Design Fall 5 Lecture 4: CMOS Inverter (static view) [Adapted from Chapter 5 of Digital Integrated Circuits, 3, J. Rabaey et al.] [Also borrowed from Vijay Narayanan and Mary Jane Irwin]
Lecture 4: CMOS Transistor Theory
Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q
Errata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg
Errata 2 nd Ed. (5/22/2) Page Errata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg Page Errata 82 Line 4 after figure 3.2-3, CISW CJSW 88 Line between Eqs. (3.3-2)
Today s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model
- Spring 003 Lecture 4 Design Rules CMOS Inverter MOS Transistor Model Today s lecture Design Rules The CMOS inverter at a glance An MOS transistor model for manual analysis Important! Labs start next
Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)
1 Introduction to Transistor-Level Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed
ESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 19: March 29, 2018 Memory Overview, Memory Core Cells Today! Charge Leakage/Charge Sharing " Domino Logic Design Considerations! Logic Comparisons!
Lecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor
Lecture 10, ATIK. Data converters 3
Lecture, ATIK Data converters 3 What did we do last time? A quick glance at sigma-delta modulators Understanding how the noise is shaped to higher frequencies DACs A case study of the current-steering
FPF1003A / FPF1004 IntelliMAX Advanced Load Management Products
August 2012 FPF1003A / FPF1004 IntelliMAX Advanced Load Management Products Features 1.2 V to 5.5 V Input Voltage Operating Range Typical R DS(ON) : - 30 mω at V IN =5.5 V - 35 mω at V IN =3.3 V ESD Protected:
Designing Information Devices and Systems I Fall 2015 Anant Sahai, Ali Niknejad Homework 8. This homework is due October 26, 2015, at Noon.
EECS 16A Designing Information Devices and Systems I Fall 2015 Anant Sahai, Ali Niknejad Homework 8 This homework is due October 26, 2015, at Noon. 1. Nodal Analysis Or Superposition? (a) Solve for the
9/18/2008 GMU, ECE 680 Physical VLSI Design
ECE680: Physical VLSI Design Chapter III CMOS Device, Inverter, Combinational circuit Logic and Layout Part 3 Combinational Logic Gates (textbook chapter 6) 9/18/2008 GMU, ECE 680 Physical VLSI Design
Pass-Transistor Logic
-all 26 Digital tegrated ircuits nnouncements No new homework this week roject phase one due on Monday Midterm 2 next Thursday Review session on Tuesday Lecture 8 Logic Dynamic Logic EE4 EE4 2 lass Material
ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2018
ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2018 ΔΙΑΛΕΞΗ 11: Dynamic CMOS Circuits ΧΑΡΗΣ ΘΕΟΧΑΡΙΔΗΣ (ttheocharides@ucy.ac.cy) (ack: Prof. Mary Jane Irwin and Vijay Narayanan) [Προσαρμογή από
RT9403. I 2 C Programmable High Precision Reference Voltage Generator. Features. General Description. Ordering Information.
I 2 C Programmable High Precision Reference Voltage Generator General Description The RT9403 is a high precision reference voltage generating console consisting of three I 2 C programmable DACs. Each DAC
EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #2: MOSFET Structure and Basic Operation Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 1 this week, report due next week Bring
EECS 141 F01 Lecture 17
EECS 4 F0 Lecture 7 With major inputs/improvements From Mary-Jane Irwin (Penn State) Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND
Nyquist-Rate D/A Converters. D/A Converter Basics.
Nyquist-Rate D/A Converters David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 20 D/A Converter Basics. B in D/A is a digital signal (or word), B in b i B in = 2 1
Objective and Outline. Acknowledgement. Objective: Power Components. Outline: 1) Acknowledgements. Section 4: Power Components
Objective: Power Components Outline: 1) Acknowledgements 2) Objective and Outline 1 Acknowledgement This lecture note has been obtained from similar courses all over the world. I wish to thank all the
ECEN474/704: (Analog) VLSI Circuit Design Spring 2018
ECEN474/704: (Analog) SI Circuit Design Spring 2018 ecture 2: MOS ransistor Modeling Sam Palermo Analog & Mixed-Signal Center exas A&M University Announcements If you haven t already, turn in your 0.18um
University of Toronto. Final Exam
University of Toronto Final Exam Date - Apr 18, 011 Duration:.5 hrs ECE334 Digital Electronics Lecturer - D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last
Lecture 4: DC & Transient Response
Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response David Harris Harvey Mudd College Spring 004 Outline DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Slide
MCP9700/9700A MCP9701/9701A
Low-Power Linear Active Thermistor ICs Features Tiny Analog Temperature Sensor Available Packages: SC-70-5, SOT-23-5, TO-92-3 Wide Temperature Measurement Range: - -40 C to +125 C Accuracy: - ±2 C (max.),
Integrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 14 The CMOS Inverter: dynamic behavior (sizing, inverter
EMC Considerations for DC Power Design
EMC Considerations for DC Power Design Tzong-Lin Wu, Ph.D. Department of Electrical Engineering National Sun Yat-sen University Power Bus Noise below 5MHz 1 Power Bus Noise below 5MHz (Solution) Add Bulk
DESCRIPTION TYPICAL APPLICATION. LTC Micropower, Regulated 5V Charge Pump in a 5-Pin SOT-23 Package FEATURES APPLICATIONS
LTC117- Micropower, Regulated V Charge Pump in a -Pin SOT-23 Package FEATRES ltralow Power: I CC = 6µA Typ Short-Circuit/Thermal Protected V ±% Regulated Output Range: 2.7V to V Output Current: 10mA (
Digital Integrated Circuits A Design Perspective
Digital Integrated Circuits Design Perspective Designing Combinational Logic Circuits Fuyuzhuo School of Microelectronics,SJTU Introduction Digital IC Dynamic Logic Introduction Digital IC 2 EE141 Dynamic
Dual Low Dropout Voltage Regulator
Dual Low Dropout Voltage Regulator TLE 4473 GV55-2 Features Stand-by output 190 ma; 5 V ± 2% Main output: 300 ma, 5 V tracked to the stand-by output Low quiescent current consumption Disable function separately
EE241 - Spring 2003 Advanced Digital Integrated Circuits
EE241 - Spring 2003 Advanced Digital Integrated Circuits Lecture 16 Energy-Recovery Circuits SOI Technology and Circuits Optimal EDP Contours 1 Leakage and Switching ELk 2 = ESw Opt L ln d K tech α avg
PT5108. High-PSRR 500mA LDO GENERAL DESCRIPTION FEATURES APPLICATIONS TYPICAL APPLICATIONS. Ripple Rejection vs Frequency. Ripple Rejection (db)
GENERAL DESCRIPTION The PT5108 is a low-dropout voltage regulator designed for portable applications that require both low noise performance and board space. Its PSRR at 1kHz is better than 70dB. The PT5108
CMOS Digital Integrated Circuits Lec 13 Semiconductor Memories
Lec 13 Semiconductor Memories 1 Semiconductor Memory Types Semiconductor Memories Read/Write (R/W) Memory or Random Access Memory (RAM) Read-Only Memory (ROM) Dynamic RAM (DRAM) Static RAM (SRAM) 1. Mask
Design for Manufacturability and Power Estimation. Physical issues verification (DSM)
Design for Manufacturability and Power Estimation Lecture 25 Alessandra Nardi Thanks to Prof. Jan Rabaey and Prof. K. Keutzer Physical issues verification (DSM) Interconnects Signal Integrity P/G integrity
University of Pennsylvania Department of Electrical Engineering. ESE 570 Midterm Exam March 14, 2013 FORMULAS AND DATA
University of Pennsylvania Department of Electrical Engineering ESE 570 Midterm Exam March 4, 03 FORMULAS AND DATA. PHYSICAL CONSTANTS: n i = intrinsic concentration undoped) silicon =.45 x 0 0 cm -3 @
Design Considerations for Integrated Semiconductor Control Electronics for a Large-scale Solid State Quantum Processor
Design Considerations for Integrated Semiconductor Control Electronics for a Large-scale Solid State Quantum Processor Hendrik Bluhm Andre Kruth Lotte Geck Carsten Degenhardt 1 0 Ψ 1 Quantum Computing
ESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 18: March 27, 2018 Dynamic Logic, Charge Injection Lecture Outline! Sequential MOS Logic " D-Latch " Timing Constraints! Dynamic Logic " Domino
Switched Capacitor: Sampled Data Systems
Switched Capacitor: Sampled Data Systems Basic switched capacitor theory How has Anadigm utilised this. Theory-Basic SC and Anadigm-1 Resistor & Charge Relationship I + V - I Resistance is defined in terms
Lecture 23. Dealing with Interconnect. Impact of Interconnect Parasitics
Lecture 23 Dealing with Interconnect Impact of Interconnect Parasitics Reduce Reliability Affect Performance Classes of Parasitics Capacitive Resistive Inductive 1 INTERCONNECT Dealing with Capacitance
Design of Analog Integrated Circuits
Design of Analog Integrated Circuits Chapter 11: Introduction to Switched- Capacitor Circuits Textbook Chapter 13 13.1 General Considerations 13.2 Sampling Switches 13.3 Switched-Capacitor Amplifiers 13.4
Lecture 4: CMOS review & Dynamic Logic
Lecture 4: CMOS review & Dynamic Logic Reading: ch5, ch6 Overview CMOS basics Power and energy in CMOS Dynamic logic 1 CMOS Properties Full rail-to-rail swing high noise margins Logic levels not dependent
2007 Fall: Electronic Circuits 2 CHAPTER 10. Deog-Kyoon Jeong School of Electrical Engineering
007 Fall: Electronic Circuits CHAPTER 10 Digital CMOS Logic Circuits Deog-Kyoon Jeong dkjeong@snu.ac.kr k School of Electrical Engineering Seoul lnational luniversity it Introduction In this chapter, we
! Charge Leakage/Charge Sharing. " Domino Logic Design Considerations. ! Logic Comparisons. ! Memory. " Classification. " ROM Memories.
ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec 9: March 9, 8 Memory Overview, Memory Core Cells Today! Charge Leakage/ " Domino Logic Design Considerations! Logic Comparisons! Memory " Classification
Precision, Micropower, Low-Dropout, High- Output-Current, SO-8 Voltage References
19-165; Rev ; 7/ Precision, Micropower, Low-Dropout, High- General Description The MAX6167 are precision, low-dropout, micropower voltage references. These three-terminal devices operate with an input
Lecture 15: Scaling & Economics
Lecture 15: Scaling & Economics Outline Scaling Transistors Interconnect Future Challenges Economics 2 Moore s Law Recall that Moore s Law has been driving CMOS [Moore65] Corollary: clock speeds have improved
CPE/EE 427, CPE 527 VLSI Design I Pass Transistor Logic. Review: CMOS Circuit Styles
PE/EE 427, PE 527 VLI Design I Pass Transistor Logic Department of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) Review: MO ircuit
1-OF-8 DECODER/DEMULTIPLEXER High-Speed Silicon-Gate CMOS
1-OF-8 DECODER/DEMULTIPLEXER High-Speed Silicon-Gate CMOS The IN74AC138 is identical in pinout to the LS/ALS138, HC/HCT138. The device inputs are compatible with standard CMOS outputs; with pullup resistors,
EE 466/586 VLSI Design. Partha Pande School of EECS Washington State University
EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 8 Power Dissipation in CMOS Gates Power in CMOS gates Dynamic Power Capacitance switching Crowbar
CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002
CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 18-322 DIGITAL INTEGRATED CIRCUITS FALL 2002 Final Examination, Monday Dec. 16, 2002 NAME: SECTION: Time: 180 minutes Closed