Deep Submicron CMOS and the New Era of Creativity in Analog Design

Transcription

1 Deep Submicron CMOS and the New Era of Creativity in Analog Design John A. McNeill Worcester Polytechnic Institute (WPI), Worcester, MA McNEILL: CREATIVITY IN DSM CMOS MAY 3, 2006

2 Overview Analog / Mixed Signal IC Design Role of Creativity DSM CMOS Effects on Analog Design Short L, Thin t ox Matching Issues Self-Calibrating ADC Overview Design Details Results Conclusion McNEILL: CREATIVITY IN DSM CMOS MAY 3,

3 Overview Analog / Mixed Signal IC Design Role of Creativity DSM CMOS Effects on Analog Design Short L, Thin t ox Matching Issues Self-Calibrating ADC Overview Design Details Results Conclusion 3

4 Career Classification CREATIVE USEFUL ARTIST POET ADVERTISING PROFESSOR ENGINEER DOCTOR TEACHER NURSE LAWYER STOCKBROKER GOOD PAY 4

5 Why be creative? Need Easy problems solved already Tough problems need creative solution Dealing with environment of change Coping, thriving Human nature Fun! 5

6 Creativity Resources 6

7 Creativity Framework Explorer Artist Judge Warrior 7

8 Creativity Framework Explorer Artist Judge Seek out new information Survey the landscape Get off the beaten path Poke around in unrelated areas Gather lots of ideas Shift your mindset Don't overlook the obvious Look for unusual patterns Warrior 8

9 Creativity Framework Explorer Artist Judge Warrior Create something original Multiply options Use your imagination Ask what-if questions Play with ideas Look for hidden analogies Break the rules Look at things backward Change contexts Play the fool 9

10 Creativity Framework Explorer Artist Judge Evaluate options Ask what's wrong Weigh the risk Embrace failure Question assumptions Look for hidden bias Balance reason and hunches Make a decision! Warrior 10

11 Creativity Framework Explorer Artist Judge Warrior Put decision into practice Commit to a realistic plan Get help Find your real motivation See difficulty as challenge Avoid excuses Persist through criticism Sell benefits not features Make it happen Learn from every outcome 11

12 Example: Time (Stages of project) Explorer Background Research Artist Brainstorm Options Judge Choose Solution Warrior Implement Design 12

13 Why a Creativity Model? Education Standardized-test-numbed students Paralysis in face of open-ended problem Designer Awareness of strengths, weaknesses Recognize preferences Not Right or Wrong! One way of looking at process Orchard analogy 13

14 Example: Modes of Thinking Explorer Artist Divergent Soft Qualitative Judge Warrior Convergent Hard Quantitative 14

15 Example: Preferred Problem Solution Explorer Artist Add Complexity Judge Warrior Eliminate Complexity 15

16 Overview Analog / Mixed Signal IC Design Role of Creativity DSM CMOS Effects on Analog Design Short L, Thin t ox Matching Issues Self-Calibrating ADC Overview Design Details Results Conclusion McNEILL: CREATIVITY IN DSM CMOS APRIL 28,

17 Good Old Days W/L I D Large strong inversion region Square law, easy hand analysis Op 't Eynde and Sansen, "Design and Optimization of CMOS Wideband Amplifiers," CICC

18 W [µm] TSMC L=0.25µm process Moderate inversion Graphical / numerical analysis I D [µa] 18

19 DSM CMOS Thin t ox : Gate Leakage µa Gate Currents! Tunneling current through thin t ox R. Van Langevelde et. al., "Gate current: Modeling, L extraction and impact on RF performance, IEDM

20 DSM CMOS: MOSFET Current Gain Bipolar-like current gain for longer L A.-J. Annema et. al., Analog Circuits in Ultra-Deep-Submicron CMOS, IEEE J. Solid-State Circuits, Jan. 2005, pp

21 DSM CMOS: Gate Leakage Long L devices unsuitable R. Van Langevelde et. al., "Gate current: Modeling, L extraction and impact on RF performance, IEDM

22 Overview Analog / Mixed Signal IC Design Role of Creativity DSM CMOS Effects on Analog Design Short L, Thin t ox Matching Issues Self-Calibrating ADC Overview Design Details Results Conclusion McNEILL: CREATIVITY IN DSM CMOS APRIL 28,

23 Matching Classical: Matching improves with Spend area to match Power penalty to drive C OX W L WL Pelgrom et.al., "Matching properties of MOS transistors," IEEE J. Solid-State Circuits, Oct. 1989, pp

24 Technology Dependence As V DD scales down with L min Some improvement in matching A Vth K. Bult, "Analog Design in Deep Sub-Micron CMOS," ESSCIRC2000, Sept

25 Technology Dependence Dynamic Range limited by matching K. Bult, "Analog Design in Deep Sub-Micron CMOS," ESSCIRC2000, Sept

26 Speed / Accuracy / Power Tradeoff Limited by matching, not noise Some improvement with technology Kinget, " Device mismatch and tradeoffs in the design of analog circuits," JSSC, June,

27 Matching / Gate Leakage Issues Spend area: Gate leakage mismatch increases with Limit to attainable matching WL A.-J. Annema et. Al., Analog Circuits in Ultra-Deep-Submicron CMOS, IEEE J. Solid-State Circuits, Jan. 2005, pp

28 Matching / Gate Leakage Issues Break limit: Spend area (same L): But extra power penalty A.-J. Annema et. Al., Analog Circuits in Ultra-Deep-Submicron CMOS, IEEE J. Solid-State Circuits, Jan. 2005, pp

29 Or: Abandon Matching! Options: Fix with analog complexity: Autozero, Enz and Temes, "Circuit Techniques for Reducing the Effects of Op-Amp Imperfections: Autozeroing, Correlated Double Sampling, and Chopper Stabilization," Proceedings of the IEEE, November 1996, pp or Fix with digital complexity 29

30 Overview Analog / Mixed Signal IC Design Role of Creativity DSM CMOS Effects on Analog Design Short L, Thin t ox Matching Issues Self-Calibrating ADC Overview Design Details Results Conclusion McNEILL: CREATIVITY IN DSM CMOS APRIL 28,

31 Self-Calibrating ADC Goals General: Take advantage of CMOS scaling Digital Relax requirements on analog precision All calibration / complexity in digital domain Background Calibration continuous in background Deterministic Short time constant for adaptation No requirements on input signal behavior Specific Implementation: 16b 1MS/s Cyclic ADC in 0.25µm CMOS J. McNeill, et. al., "'Split-ADC' Architecture for Deterministic Digital Background Calibration of a 16b 1MS/s ADC," ISSCC

32 Cyclic ADC RESIDUE AMPLIFIER v IN S/H G +! DAC COMP +/-V REF v RES d k DIGITAL x TIMING 1) Sample input, compare to threshold digital decision d 2) Amplify input by factor G 3) Subtract d. V REF residue voltage v RES 4) Repeat cycle with v RES as input Result: sequence of decisions d k 32

33 v RES(I) Residue amplifier: G + DAC! Cyclic ADC v RES(O) SLOPE = G Residue plot: v RES(O) COMP +/-V REF d k v RES(I) Input-Output Relationship: d = -1 d = +1 v " d! V RES ( O) = G! vres ( I ) REF Multiply input by cyclic gain G, subtract d. V REF 33

34 Example: 3-Cycle ADC Follow residues; start Cycle 1 residue: Cycle 2: Cycle 3: Rearrange: v RES (3) v RES (2) v RES (1) = Gv [! d V ] IN v IN IN! d V " vres (1) = G Gv 1 REF REF! d " vres (2) = G G Gv " REF [ [ IN! d1v REF ]! d2vref ]! d3vref 1 2 V [ ] G d1 + G d2 G d V REF 3 v RES ( 3) = G v IN!

35 1: Cyclic ADC as Negative Feedback Loop [ ] G d1 + G d2 G d V REF 3 v RES ( 3) = G v IN! + 3 Cyclic amplifier trying to "blow up" v IN DAC trying to drive residue to zero Residue voltages bounded if G isn't "too big" Safety margin: Choose G < 2 Bonus: Redundancy 35

36 Redundancy Key: Multiple valid decision paths to output code -1 or +1 OK d = -1 d = +1 d = -1 d = +1 G = 2 G < 2 36

37 2: Digital Correction Divide both sides by G 3 V REF and rearrange v IN RES (3) = d1 + d2 + d 2 3 3! 3 REF G G G G VREF V v Output code x (radix G) Quantization error Digital reconstruction from comparator decisions d k : Use estimated gain G (EST) to calculate output code x : x & = $ 1 #! d & + $ 2 #! d ( EST ) 1 2 G( ) G( ) G! % EST " % EST " % ( EST ) " 3 # d Only G needed to digitally correct ADC linearity Calibration: G (EST) = G to within converter accuracy 1 & + $

38 Output Code v IN = 1 V REF G d G 2 d G 3 d 3 + L Analog: G = 2 to within converter accuracy Calibration: trim, match x Digital: Use estimated gain G (EST) to calculate output code x : & = $ 1 #! d & + $ 2 #! d ( EST ) 1 2 G( ) G( ) G! % EST " % EST " % ( EST ) " 1 & + $ 3 # d Calibration: How to determine G (EST) = G to within converter accuracy?

39 Previous Calibration Techniques Deterministic? (All) Digital? Background? [1] [2] [3] [4] [5] [6] [7] [8] [9] No previous technique has all desired features 1. Galton, "Digital cancellation of D/A converter noise in pipelined ADCs," TCAS-II, March Murmann..., "A 12b 75MS/s Pipelined ADC using open-loop residue amplification," ISSCC Liu.., "A 15b 20MS/s CMOS Pipelined ADC with Digital Background Calibration," ISSCC Nair..., "A 96dB SFDR 50MS/s Digitally Enhanced CMOS Pipelined A/D Converter," ISSCC Ryu..., "A 14b-Linear Capacitor Self-Trimming Pipelined ADC," ISSCC Erdogan..., "A 12-b Digital-Background-Calibrated Algorithmic ADC with -90-dB THD," ISSC Chiu..., "Least mean square adaptive digital background calibration of pipelined ADCs," TCAS-I, Jan Lee, "A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic ADC," JSSC, Apr Karanicolas, "A 15-b 1-MS/s digitally self-calibrated pipeline ADC," JSSC, Dec

40 Previous Digital Background Calibration CONVERSIONS REQUIRED FOR CALIBRATION N [1] Galton2000 [2] Murmann2003 [3] Liu2004 [4] Nair2004 [5] Ryu N BITS RESOLUTION 40

41 Statistical Techniques Problem How long to calibrate with 2 2N samples? 12 bits, 75 MS/s [2] 2 2 " 12! 75Msps 200ms 16 bits, 1 MS/s 2 2 " 16! 1Msps 1 hour Deterministic approach needed The problem: How to do a deterministic calibration procedure in background without a known input? 41

42 Split ADC Architecture ADC OUTPUT CODE ADC "A" x A + + x = x A + x B 2 v IN ADC "B" x B + - "x = x B # x A ERROR ESTIMATION DIFFERENCE Average of A, B results is ADC output code Calibration signal developed from difference 42

43 Intuitive View of Split ADC x v IN ADC "A" x A ADC "B" xb x t RESIDUE MODES ERROR ESTIMATION "x = x B # x A Different paths to (ideally) same answer Estimate errors from "disagreements" Only way for A, B to always agree is for both to be correctly calibrated 43

44 Robert Frost: New Hampshire... a figure of the way the strong of mind and strong of arm should fit together, One thick where one is thin and vice versa. V T N H 44

45 Robert Frost: New Hampshire... a figure of the way the strong of mind and strong of arm should fit together, One thick where one is thin and vice versa. V T N H Key idea: two partners trying to do the same thing in different ways 45

46 Same Area, Noise, Speed, Power ANALOG DIGITAL ANALOG DIGITAL v IN C g m x SPLIT v IN C 2 C 2 g m 2 g m 2 A B x A x B x x A + x B 2 Speed f T = b g m C b g m 2 C 2 = " b g m $ # C % ' & Power P = p " g m p " g m 2 + p " g m 2 = p " g m Noise " x = n kt " 1 C 2 n kt % $ ' # C 2 & 2 " n kt % $ ' # C 2 & 2 = n kt C Negligible impact on analog complexity 46

47 Overview Analog / Mixed Signal IC Design Role of Creativity DSM CMOS Effects on Analog Design Short L, Thin t ox Matching Issues Self-Calibrating ADC Overview Design Details Results Conclusion McNEILL: CREATIVITY IN DSM CMOS APRIL 28,

48 Evaluation Block Diagram REF EVALUATION BOARD FPGA V IN INPUT SIGNAL COND TEST CHIP CYCLIC ANALOG CYCLIC DIGITAL DATA FORMATTING DSP INTERFACE OTHER FPGA FUNCTIONS TO RAM / DSP "PRODUCT" CYCLIC TIMING CNVST EXT TIMING Test chip mostly analog Digital on FPGA (code "synthesis-ready" for product) 48

49 ADC Block Diagram S/H G A + " " $ # 1 ˆ G A % ' & k Σ x A v IN S/H COMPS COMPS G B DAC PATH A PATH B DAC + " d ka d kb A L.U.T. ˆ G A ERROR COEFF L.U.T. ˆ G B B L.U.T. " $ # 1 ˆ G B % ' & k " k 1 % $ ' # G& k Σ Σ Σ Σ Σ " + SDK A µ µ SDK B x B ˆ " A "x ˆ " B ERROR EST. + + x CYCLIC RESIDUE AMPLIFIERS OFF-CHIP DIGITAL PROCESSOR (FPGA) 49

50 ADC Digital Correction S/H G A + " " $ # 1 ˆ G A % ' & k Σ x A v IN S/H COMPS COMPS G B DAC PATH A PATH B DAC + " d ka d kb A L.U.T. ˆ G A ERROR COEFF L.U.T. ˆ G B B L.U.T. " $ # 1 ˆ G B % ' & k " k 1 % $ ' # G& k Σ Σ Σ Σ Σ " + SDK A µ µ SDK B x B ˆ " A "x ˆ " B ERROR EST. + + x CYCLIC RESIDUE AMPLIFIERS OFF-CHIP DIGITAL PROCESSOR (FPGA) 50

51 ADC Digital Correction COMPARATOR DECISIONS [ -1, 0, +1 ] d ka " 1 $ # ˆ G A % ' & DECISION WEIGHT L.U.T. k Σ x A ACCUMULATE OUTPUT CODE Decision weight L.U.T. Periodically recalculated in background Separate L.U.T.s for A, B output codes 51

52 Error Estimation S/H G A + " " $ # 1 ˆ G A % ' & k Σ x A v IN S/H COMPS COMPS G B DAC PATH A PATH B DAC + " d ka d kb A L.U.T. ˆ G A ERROR COEFF L.U.T. ˆ G B B L.U.T. " $ # 1 ˆ G B % ' & k " k 1 % $ ' # G& k Σ Σ Σ Σ Σ " + SDK A µ µ SDK B x B ˆ " A "x ˆ " B ERROR EST. + + x CYCLIC RESIDUE AMPLIFIERS OFF-CHIP DIGITAL PROCESSOR (FPGA) 52

53 x x A B A, B Outputs = x + = x + Error Estimation [ SDK A]! A [ SDK B ]! B Difference [ SDK ] [ ] B! B " SDK A A # x =! IDEAL ERROR Ideal x cancelled from estimation signal path No need for long decorrelation times Deterministic: solve for ε A, ε B from a few Δ x observations SDK error coefficients can be determined from comparator decisions 53

54 Error Estimation Difference: [ SDK ] [ ] B! B " SDK A A # x =! SDK A, SDK B Error coefficients ε A, ε B Fractional errors in G A, G B estimates d ka Σ SDK A ERROR COEFF L.U.T. " k 1 % $ ' # G& k Need different d ka, d kb for visibility to errors 54

55 Multiple Residue Mode Amplifier S/H G A + " " $ # 1 ˆ G A % ' & k Σ x A v IN S/H COMPS COMPS G B DAC PATH A PATH B DAC + " d ka d kb A L.U.T. ˆ G A ERROR COEFF L.U.T. ˆ G B B L.U.T. " $ # 1 ˆ G B % ' & k " k 1 % $ ' # G& k Σ Σ Σ Σ Σ " + SDK A µ µ SDK B x B ˆ " A "x ˆ " B ERROR EST. + + x CYCLIC RESIDUE AMPLIFIERS OFF-CHIP DIGITAL PROCESSOR (FPGA) 55

56 Multiple Residue Mode Amplifier v IN S/H +V TH 0 G SEL + " +V REF 0 "V REF DAC d CYCLE DECISION -1 / 0 / +1 "V TH PATH PATH: 00 CYCLIC 01 HIGH 10 LOW 11 WIDE DECISION d: b PATH sets residue mode entirely in digital domain 56

57 S/H, 1.5b DAC, G=1.92 Cyclic Amplifier v IN S/H +V TH 0 G SEL + " +V REF 0 "V REF DAC d CYCLE DECISION -1 / 0 / +1 "V TH PATH PATH: 00 CYCLIC 01 HIGH 10 LOW 11 WIDE DECISION d: b PATH sets residue mode entirely in digital domain 57

58 INL Shapes Vary by Residue Mode [ SDK ] [ ] B! B " SDK A A # x =! INL shape same as SDK A, SDK B error coefficients 58

59 Cyclic Amplifier: 3-Capacitor? Advantages Easier to do signal-independent reference current Decouple reference, cyclic gain paths (CM!) Disadvantages Extra capacitor area Extra noise gain (killer!) Output only valid on one phase (1/2 cycle) Less time for comparator DAC cap Feedback cap Signal cap P. Ferguson, Practical Aspects of Delta-Sigma Data Converter Design, MEAD Microelectronics 59

60 Cyclic Amplifier: 2-Capacitor Advantages Less cap area Lower noise gain Output valid both phases Easier on comparator SDBVOUT DB C D DT VOUT STPA VCM SFBVIN CF SCF VIN SFBVIN SFBVOUT SDTA SDBP SDBZ SDBM SDTVCM A VREFP VCM VREFM VCM Disadvantages Signal-dependent reference current Reference, cyclic gain paths constrained (CM!) 60

61 Cyclic Amplifier: 2-Capacitor 2-Cap chosen: Lower total capacitance for a given noise performance Different feedback β in DAC, sample modes Changes effect of amplifier noise "DAC mode" β ~ 1/2 "Sample mode" β ~ 1 C D CF CF C D VCM VCM 61

62 S/H, 1.5b DAC, G=1.92 Cyclic Amplifier V CM V INP V OP 13.5pF 15pF V REFP V CM V CM V OP V REFM V OM 13.5pF 15pF V OM kt/c noise limited large C V CM V INM 62

63 Op-Amp V CM V INP V OP 13.5pF 15pF V REFP V CM V CM V OP V REFM V OM 13.5pF 15pF V OM kt/c noise limited large C V CM V INM 63

64 Op-Amp Requirements Param C L I DD f T A OL V OUT SR Spec 20-30pF 33mA 150 MHz 100 db +/- 1.8V 500 V/us Comments Required by kt/c noise limit 80% of total IC power goal (100mW) 16 bit settling, 30 ns, 1st half cycle Maintain over full signal range Trade SNR, linearity Trade with ft, settling time 64

65 Op-Amp VB5 VB1 VB5 V IP V OP V IM V OM VB2 VB3 VB4 SNR ±2Vpp swing Output not cascoded 16b linear ~100dB A OL 2-stage First stage Gain boosted cascode Bult & Geelen, "A fast-settling CMOS op amp for SC circuits with 90-dB DC gain," JSSC, Dec 1990 Pan et. al., "A 3.3-V 12-b 50-MS/s A/D converter in 0.6-µm CMOS with over 80-dB SFDR," JSSC, Dec

66 Op-Amp: Design for 90dB SNR Noise contributors: VOUT VCM VIN Sample cap kt/c SFBVIN SFBVIN Op-amp g m SDBVOUT STPA CF SFBVOUT C D DB DT SCF SDTA SDBP SDBZ SDBM SDTVCM A VREFP VCM VREFM VCM Plot SNR, total current I BIAS as function of C F, I BIAS g m 66

67 Op-Amp: I BIAS C F Optimization DIFF PAIR I BIAS [A] SNR [db] TOTAL OP-AMP CURRENT [ma] SAMPLE CAPACITANCE C F [F] 67

68 Op-Amp: I BIAS C F Optimization C F limited g m limited SNR 90dB Bias current, sample cap tradeoff 68

69 Overview Analog / Mixed Signal IC Design Role of Creativity DSM CMOS Effects on Analog Design Short L, Thin t ox Matching Issues Self-Calibrating ADC Overview Design Details Results Conclusion McNEILL: CREATIVITY IN DSM CMOS APRIL 28,

70 Die Photo ADC "A" ADC "B" SWITCHED CAP NETWORK OP-AMP COMPARATORS 70

71 Measured INL 71

72 Temperature Performance 72

73 Calibration Convergence 73

74 Comparison with Previous Work CONVERSIONS REQUIRED FOR CALIBRATION N [1] Galton2000 [2] Murmann2003 [3] Liu2004 [4] Nair2004 [5] Ryu THIS WORK Long decorrelation times not necessary N BITS RESOLUTION 74

75 Performance Summary Technology Supply Voltage Resolution Conversion Rate SNR INL DNL Power Consumption * Die Area * 0.25µm 1P4M CMOS 2.5 V 16 b 1 MS/s 89 db +2.1 / -4.8 LSB / 0.47 LSB 105mW 1.16mm x 1.38mm * Excludes digital on FPGA 75

76 "Split ADC" architecture Average: Output code Difference: Drive to zero to correct errors Deterministic: Rapid self-calibration Suitable for high resolution ADCs 16b 1MSps Cyclic ADC Self-calibration in ~ 10,000 conversions Complexity moved into digital domain 76

77 Overview Analog / Mixed Signal IC Design Role of Creativity DSM CMOS Effects on Analog Design Short L, Thin t ox Matching Issues Self-Calibrating ADC Overview Design Details Results Conclusion McNEILL: CREATIVITY IN DSM CMOS APRIL 28,

78 DSM CMOS Conclusions Performance challenges Change in role of analog techniques Opportunities Digital complexity enabled Need for designer creativity Choose best from both worlds 78

79 Acknowledgments Analog Devices Precision Nyquist Converters group Bob Adams Bob Brewer Larry DeVito Paul Ferguson Colin Lyden Katsu Nakamura Richard Schreier Larry Singer Stanford University Boris Murmann 79

80 80

81 Creativity References Self-Calibrating ADCs R. Von Oech, "A Whack on the Side of the Head" New York: Warner, ISBN R. Von Oech, "A Kick in the Seat of the Pants" New York: HarperCollins, ISBN CMOS Design Op 't Eynde and Sansen, "Design and Optimization of CMOS Wideband Amplifiers," Proc. CICC, R. van Langevelde, A. J. Scholten, R. Duffy, F. N. Cubaynes, M. J. Knitel, and D. B. M. Klaassen, "Gate current: Modeling, L extraction and impact on RF performance, Proc. IEDM, A.-J. Annema, B. Nauta, R. van Langevelde, and H. Tuinhout, Analog Circuits in Ultra-Deep-Submicron CMOS, IEEE J. Solid-State Circuits, Jan C. Enz and G. Temes, "Circuit Techniques for Reducing the Effects of Op-Amp Imperfections: Autozeroing, Correlated Double Sampling, and Chopper Stabilization," Proceedings of the IEEE, Nov J. McNeill, M. Coln, and B. Larivee, "'Split-ADC' Architecture for Deterministic Digital Background Calibration of a 16b 1MS/s ADC," ISSCC2005 B. Murmann and B. Boser, "A 12-bit 75-MS/s Pipelined ADC Using Open-Loop Residue Amplification," IEEE J.Solid-State Circuits, Dec Matching M. Pelgrom, A. Duinmaijer, and A. Welbers, "Matching properties of MOS transistors," IEEE J. Solid-State Circuits, Oct P. R. Kinget, " Device mismatch and tradeoffs in the design of analog circuits," JSSC, June, K. Bult, "Analog Design in Deep Sub-Micron CMOS," ESSCIRC2000, Sept