Pipelined ADC Design - A Tutorial -

Transcription

1 epartment of Electrical and omputer Engineering Pipelined A esign - A Tutorial - Based on Slides from r. Bibhudatta Sahoo University of Illinois at Urbana-hampaign Slides by Bibhudatta Sahoo --

2 Outline Review of Pipelined As Impact of Scaling on ata onverter esign Why alibration? Basics of igital alibration Techniques Survey of igital alibration Techniques onclusion Slides by Bibhudatta Sahoo -2-2

3 Introduction ata onverter esign is challenging in Nanoelectronics Era: Low intrinsic device gain High nonlinearity Reduced headroom (reduced dynamic range) Large variability and mismatches Survival in digital-driven system-on-chip (SO) environment Trends in data converter design igitally Assisted Analog esign Fuelled by aggressive device scaling Slides by Bibhudatta Sahoo 3-3-

4 Pipeline A - Review - Slides by Bibhudatta Sahoo -4-4

5 Generic Pipelined A V IN Stage- Stage-2 Stage-M 2 N N NM + - Flash A sub-a sub-a sub-a sub-a sub-a sub-a (N +)-bits 2 (N 2 +)-bits M (N M +)-bits N (M+) -bits (N + N N M )-bits 2 -N 2 -N2 2 -NM igital ombiner Each stage resolves a small number of bits (i.e. N, N 2,, N M bits). The overall resolution of the A is P = (N +N 2 + +N M +N M+ ). OUT Output of stage-i (called residue r i ) is digitized to (P- i j= N j )-bits. The low resolution A digitizing r i is called the backend of stage-i. Slides by Bibhudatta Sahoo -5-5

6 Switched-apacitor (S) ircuit An Overview () Key building blocks: Switches apacitors Op amp Two-phase non-overlapping clock generator Sample/Reset phase is high Switches S to S 4 are controlled by, i.e. S to S 4 close when is high. It is called sample-phase as input signal is sampled. It is also called reset-phase as opamp is reset (more later). Hold/Amplification phase 2 is high Switches S 5 to S 7 are controlled by 2, i.e. S 5 to S 7 close when 2 is high. V out is an amplified and held version of the sampled V in. Slides by Bibhudatta Sahoo -6-6

7 Switched-apacitor (S) ircuit An Overview (2) Falling edge of samples the input, V in and V in2. In 2 the sampled values get amplified to give V out & V out2, respectively. uring the sampled charge is Q S = S V in. uring 2 the charge is Q H = F V out. Since charge is conserved, Q S = Q H V out = S F V in. The gain of the circuit is the ratio of the sampling capacitor ( S ) to feedback capacitor ( F ). Slides by Bibhudatta Sahoo -7-7

8 Switched-apacitor omparator Φ 2 uring the sampled charge Q S = if V in. Since charge is conserved the charge during 2 is given by Q H = if V THi V X resulting in V X = V in V THi. When the comparator is clocked with the falling edge of 2 it makes a decision based on whether V in > V THi or V in < V THi. Slides by Bibhudatta Sahoo -8-8

9 Switched-apacitor 4-bit Flash A 4-bit flash incorporates 5 switched capacitor comparators. The threshold voltages V TH to V TH5 are generated by a resistor ladder comprising of 6 equal resistors. V TH Φ 2 T The outputs of the comparator give a 5-bit wide thermometer code which controls the A of the MA. The thermometer code is converted to 4-bit binary code using an on-chip look-up table, also called read-onlymemory (ROM). V TH5 Φ 2 T 5 Note: A switched capacitor N-bit flash would incorporate 2 N- switched capacitor comparators and a resistor ladder comprising 2 N resistors to generate the 2 N- threshold voltages, V TH to V TH2 N. Slides by Bibhudatta Sahoo -9-9

10 Switched-apacitor MA () An M-bit MA incorporates 2 M unit capacitors ( i, i= to 2 M ), feedback capacitor F, switches, and an op amp. This block does the following operations: is high (Sample phase/reset phase): Sampling of input 2 is high (Amplification phase): igital-to-analog onversion (A) Subtraction quantization noise generation Amplification (Multiplying) scaling of the quantization noise to the full-scale for the later stages to digitize to relax the sensitivity requirements of the later stage circuits. Note: A switched capacitor 4-bit flash would incorporate 2 4 unit capacitors. Slides by Bibhudatta Sahoo --

11 Switched-apacitor MA (2) uring sample phase the sampled charge is, uring amplification phase the charge is given by, Q s = 2 M i V in i= Q a = 2 M i= T i i V R + F V res By conservation of charge we get, V res = i= 2 M 2 i V in M i= B i i V R F where, B i = if T i = and B i = if T i =. If F = i then gain 2 M, if F = 2 i then gain 2 M-. Slides by Bibhudatta Sahoo --

12 Sources of Errors in Pipelined A V IN Stage- Stage-2 Stage-M 2 N N NM + - Flash A sub-a sub-a sub-a sub-a sub-a sub-a (N +)-bits (N 2 +)-bits 2 M N (N M +)-bits (M+) -bits (N + N N M )-bits 2 -N 2 -N2 2 -NM igital ombiner OUT omparator Offset Op Amp Nonlinearity apacitor Mismatch Op Amp Offset Op Amp Gain harge Injection Mismatch Op Amp Input apacitance Op Amp and kt/ Noise 2 Slides by Bibhudatta Sahoo -2-

13 omparator Offset Missing Levels Missing odes omparator offset saturates the later stage. Redundancy can overcome this. Slides by Bibhudatta Sahoo -3-

14 Overcoming omparator Offset () F = i, M=3 No redundancy V res = i= 2 M 2 i V in M i= B i i V R F If F = 2 i then gain 2 M- resulting in comparator offset tolerance of V REF /2 M. F = 2 i, M=3 Redundancy Slides by Bibhudatta Sahoo -4-

15 Overcoming omparator Offset.5-bit Architecture +V REF V REF 2 V REF 2 V REF 4 V REF 4 Offset orrection Range Flip-around Topology +V REF V OUT -V REF V OUT = S + F V IN k S V REF F where, k = ±, -V REF +V REF V IN -V REF V REF 4 + V REF 4 Ref: S. Lewis et al, A -b 2-MS/s Analog-to-igital onverter, IEEE JSS., pp , March 992 Slides by Bibhudatta Sahoo -5-

16 Overcoming omparator Offset.5-bit Architecture +V REF V REF 2 V REF 2 V REF 4 V REF 4 Offset orrection Range Non-Flip-around Topology +V REF V OUT -V REF V OUT = S V in kv REF F where, k = ±/2, -V REF +V REF V IN -V REF V REF 4 + V REF 4 Slides by Bibhudatta Sahoo -6-

17 apacitor Mismatch M=2, i.e., 2-bit stage V res = i= 2 M 2 i V in M i= Bi i V REF F where, B i = if T i = and B i = if T i = apacitor mismatch Missing Levels Missing odes 7 Slides by Bibhudatta Sahoo -7-

18 Finite Op amp Gain M=2, i.e., 2-bit stage V res = i= 2 M 2 i V in + M i= Bi i V REF F + 2 F + P + M i= i A where, B i = if T i = and B i = if T i = and A= Finite op amp gain Missing odes Slides by Bibhudatta Sahoo -8-

19 Op amp Nonlinearity () Weakly nonlinear op amp open-loop input-output characteristic can be given by a 3 rd order polynomial, V OUT = α V in + α 2 V 2 3 in + α 3 V in The inverse can be given by another polynomial 2 3 V in = β V out + β 2 V out + β 3 V out where, β =, β α 2 = α 2 α 3, and β 3 = 2α 2 α 5 2 α 3 α 4 B. Sahoo and B. Razavi, IEEE JSS, vol. 44, pp , Jan Slides by Bibhudatta Sahoo -9-

20 Op amp Nonlinearity (2) The input-output characteristic of the MA can be obtained by solving the following non-linear equation: 2 M 2 i= i V in = M 2 i= i V REF + F V res β V out + β 2 V out M=2, i.e. 2-bit stage Missing odes 3 + β 3 V out 2 F + P + M i= i Slides by Bibhudatta Sahoo -2-

21 Thermal Noise onsideration () Signal-to-noise ratio of an A is given by, where, 2 SNR = log P sig Q N +N T P sig = signal power = V p p (for input V 8 in = V p p sin 2πft ) 2 Q N = Δ2, 2 N T = Input referred thermal noise power of the A Δ = V p p 2N, where N = A resolution. SNR of Semiconductor As are limited by thermal noise of: Switches Op amps Switch thermal noise can be minimized by using large capacitors. The thermal noise of the switches is given by kt/, where k = , T =Temperature in K, and is the sampling capacitor. Op amp thermal noise can be minimized by burning more current. Slides by Bibhudatta Sahoo -2-

22 Thermal Noise onsideration (2) It is costly in terms of power, area, and speed to make input thermal noise smaller than quantization noise for A resolution, N > bits. For example: If full-scale A input is V, then for a -bit A the quantization noise power is given by: 2 2 = 4μVrms 2 Q N = V LSB 2 = 2 2 If thermal noise voltage power (N T ) is same as quantization noise power then the SNR takes a 3 db hit. If SNR has to take < db hit then the N T Q N. Size of the capacitor required to achieve this for bit system is 2 pf. For a 2-bit system the capacitor required would be 8 pf (a large value). For a 6-bit system the capacitor size would be 2 nf (almost physically unrealizable on chip). Slides by Bibhudatta Sahoo -22-

23 SNR (db) SNR (db) Thermal Noise onsideration (3) Ignoring other noise sources if thermal noise is only modeled by kt/ then the SNR if given by: SNR = log P sig Q N + kt SNR Vs apacitance (Full Swing = 2V) E-3.E-2.E-.E-.E-9 apacitance SNR Vs apacitance (Full Swing = V) E-3.E-2.E-.E-.E-9 apacitance 8-bit -bit 2-bit 4-bit 6-bit Slides by Bibhudatta Sahoo -23-

24 istribution of Thermal Noise Each stage contributes to the thermal noise. How do we distribute the thermal noise so that the overall inputreferred thermal noise is minimized to maximize the SNR? Lets consider a pipelined A built using -bit stages (MA gain = 2) onsidering only kt/ sampled noise the total input referred noise power: N T kt G 2 2 G 2 G G 2 G N N Slides by Bibhudatta Sahoo -24-

25 Stage Scaling for Optimal Noise () + G 2 2 N T kt G 2 G G 2 G2 N N If = 2 = N then backend stages contribute very little noise Wasteful as power G m How about scaling by 2 M where M is the resolution of each stage. Same amount of noise from each stage. Power can be reduced. Slides by Bibhudatta Sahoo -25-

26 SHA-less Architecture V IN Main Sampling Path 2 Any mismatch between the main sampling path and flash A path results in different voltages being sampled on and /α. The mismatch can be translated to time-constant mismatch ( ). 2 / For a signal of amplitude A and frequency f in the difference in voltage sampled on and / is: Flash A Path Elements that can have mismatch V = 2 f in A Match the flash and MA paths. [Mehr 2] Slides by Bibhudatta Sahoo -26-

27 Pipeline A - Area, Power, Speed, Resolution Slides by Bibhudatta Sahoo -27- Optimization-

28 Pipeline A Area, Power, Speed, Resolution Trade-off V IN Stage- 2 N + - r i Backend A sub-a sub-a (N +)-bits (P-N )-bits 2 -N igital ombiner P-bits OUT For a given A resolution, the number of stages and number of bits resolved in each stage determines: power consumption area Slides by Bibhudatta Sahoo -28-

29 .5-bit Stage 2 V REF 2 V REF 2 +V REF -V REF V REF 4 V REF 4 Offset orrection Range V OUT Feedback factor = ½. V IN 2 F S ±V REF, S F X F V ks ksv X A IN Offset correction range = ±V REF /4 (i.e. ±5 mv for V REF =.6V). REF Settling Requirement on the op amp reduced by -bit. Input referred noise = ½ of output noise. V X F V OUT Slides by Bibhudatta Sahoo -29-

30 2.5-bit Stage V IN b 2 b ±V REF 4 ±V REF b 5 2 V X X 2 2 = 2 = 8 V OUT V REF 2 V REF 2 +V REF -V REF Offset orrection Range Feedback factor =/4. Offset correction range = ±V REF /8 (i.e. ±75 mv for V REF =.6V). Settling Requirement on the op amp reduced by 2-bits. Input referred noise is ¼ of output noise. Input-Output transfer function is: V i IN i3 8 i i VOUT 2 2 A ±V REF 8 5 bv i REF X Slides by Bibhudatta Sahoo -3-

31 3.5-bit Stage 2 Feedback factor = /8. V IN b 2 b ±V REF 4 b 3 2 ±V REF 6 V X X 2 = 2 = 6 V OUT V REF 2 V REF 2 +V REF -V REF Offset orrection Range V OUT 6 i Offset correction range = ±V REF /6 (i.e. ±37.5 mv for V REF =.6V). Settling Requirement on the op amp reduced by 3-bits. Input referred noise is /8 of output noise. Input-Output transfer function is: V i IN 2 3 i i3 bv 2 A i REF X ±V REF Slides by Bibhudatta Sahoo -3-

32 Architecture Summary Summary of A Stage Architectures Feedback Factor Offset orrection Range Reduction in Settling Requirement Noise Scaling Reduction in apacitor Matching Requirement.5-bit Stage 2.5-bit Stage 3.5-bit Stage Parameter effected V REF 6 V REF Speed and Power 8 Linearity of A V REF -bit 2-bits 3-bits Speed and Power 2 4 SNR, Power, & 8 Area -bit 2-bits 3-bits Power and Area For resolutions more than -bits it is better to resolve more bits in the first stage: relaxing op amp settling. capacitor matching. reducing capacitance input referred noise is reduced. OES NOT relax the op amp open loop gain requirement (more later). Slides by Bibhudatta Sahoo -32-

33 Why not resolve more bits in st Stage? V IN Main Sampling Path 2 2 / Flash A Path Elements that can have mismatch Any mismatch between the main sampling path and flash A path results in different voltages being sampled on and /. The mismatch can be translated to timeconstant mismatch ( ). The difference in voltage should be within the offset correction range of the Flash A. Resolving more bits in the st stage reduces the offset-correction range and hence could result in missing codes. Offset correction range should include: omparator offsets in the flash. Time constant mismatch ( ). For a signal of amplitude A and frequency f in the difference in voltage sampled on and / is: V=2 f in A Slides by Bibhudatta Sahoo -33-

34 Gain Requirement of op amp in each stage V IN Stage- 2 N sub-a sub-a (N +)-bits N r i Backend A (P-N )-bits igital ombiner Residue voltage V ri has to settle to LSB/2 of the backend-a. Gain error: Ve V ideal A 2 PN V ri P-bits OUT V e Resolution reduces but the feedback factor also reduces by the same amount gain is defined by the resolution of the A and not the resolution of the backend A that follows. The above holds true for the op amps in the later stages of the pipeline. t Slides by Bibhudatta Sahoo -34-

35 Architecture Optimization () Some expressions used for architecture optimization i.e. number of pipeline stages and number of bits/stage: Settling time for N-bit accuracy: t settle N ln2 Two stage op amp poles and unity gain bandwidths: g m2 m p, p2, u, and p2 5 R gm2r2 L Variance of input referred sampled noise: g u kt kt N IN 2 2 op ref jitter i2 i Gi where, i = sampling caps in each stage, and G i = gain of each stage. 2 nd stage of the op amp is a common source stage. For maximum output swing at the highest speed typical gain in the 2 nd stage is. Overdrive voltage to maximize swing is chosen to be around V OV =5 mv and hence current in each branch in the two stages are I = g m V OV /2 and I 2 = g m2 V OV /2. Slides by Bibhudatta Sahoo -35-

36 Architecture Optimization (2) Signal swing = ±75 mv for.5 V supply Resolution = 2-bits (determines quantization noise) f MAX, IN = MHz f S = 2 MHz t slewing =.5 ns t non overlap =.2 ns t settling =.8 ns Noise Budget: Quantization Noise Sampled Thermal Noise Op amp Noise Reference Noise Jitter Noise Input signal buffer Noise Slides by Bibhudatta Sahoo -36-

37 Architecture Optimization (3) Jitter Specification The variance of jitter voltage is given by: where, jitter t j = variance of jitter. 2 t f in = frequency of the input signal. A = amplitude of the input signal. For maximum input frequency of MHz and jitter limited SNR of 8 db the required rms jitter is 7 fs. j f in A Slides by Bibhudatta Sahoo -37-

38 Architecture Optimization (4) Noise Budget Noise Budget LSB () V p p.5 = 366 µv Reference Noise 9 µv Op Amp Noise 2 µv Sampled Noise (kt/) 64 µv (2 pf) Jitter Noise ) 66 µv (2 fs RMS jitter) ( t f V / 2 2 j in p p Overall SNR 67.8 db (in MHz band) Slides by Bibhudatta Sahoo -38-

39 Architecture Optimization (5) Sl. No. Architecture Sampling apacitor (pf) apacitance switching to Reference (pf) Power (mw) 9,.5-bit stages, 3-bit flash , 2.5-bit stages, 4-bit flash , 3.5-bit stages, 3-bit flash bit st stage, 6,.5-bit stages, and 4-bit flash bit st stage, 5,.5-bit stages, and 4-bit flash Optimization based on the following: V in(p-p)(diff) =.5 V Quantization noise is at 2-bit level. Thermal noise limited to 66 db in MHz band. Architecture 5 is optimal. Slides by Bibhudatta Sahoo -39-

40 alibration : A Necessity Slides by Bibhudatta Sahoo -4-

41 Why alibrate? Basic Pipeline Stage A ( N ) ( N ) As technology scales it is difficult to get: get high op amp gain to. remove gain error 2. suppress nonlinearity low op amp offset. capacitor matching to remove A nonlinearity. For example, op amp gain in a 2-bit system should exceed 2 8 db. Slides by Bibhudatta Sahoo -4-

42 urrent A esign Trends hoose capacitors to satisfy kt/ noise, not matching. hoose op amp with high swing kt/ noise relaxed power consumption reduced. Relaxes op amp linearity requirement hoose best trade-off between speed, power, and noise of op amp regardless of its gain. igitally correct for everything! 42 Slides by Bibhudatta Sahoo -42-

43 How to alibrate? Inverse Operator estimation can be done in: Background Foreground 43 Slides by Bibhudatta Sahoo -43-

44 apacitor Mismatch alibration Slides by Bibhudatta Sahoo -44-

45 omparator Forcing Based alibration where, and B. Sahoo and B. Razavi, IEEE JSS, vol. 48, pp , Jan. 23. Slides by Bibhudatta Sahoo -45-

46 omputation of β j (I) In other words, 46 Slides by Bibhudatta Sahoo -46-

47 omputation of β j (II) In other words, 47 s can be calculated using adders and right shifts. B. Sahoo and B. Razavi, A -b -GHz 33-mW MOS A, IEEE Journal of Solid- State ircuits, vol. 48, pp , Jun. 23. A. Karanicolas, et. al., A 5-b -Msample/s digitally self-calibrated pipeline A,, IEEE Journal of Solid-State ircuits, vol. 28, pp , ec Slides by Bibhudatta Sahoo -47-

48 Slides by Bibhudatta Sahoo -48- apacitor Mismatch alibration (). and where, , 6 5, 6 6 5, A A V A V V V A V A V V A V A V V m m P F F i m m m P F F m R j m m j R j IN OUT m m P F F m R j m m IN OUT m m P F F m m R j m m IN m OUT ividing both sides by V R we get, =backend digital output j IN j IN The input output characteristic of a 4-bit stage is: 9

49 Slides by Bibhudatta Sahoo -49- apacitor Mismatch alibration (2) Region 6 : Region 5: IN i i P F F IN IN i i P F F IN A A Region 3: Region 2 : Region : IN i i P F F IN IN i i P F F IN IN i i P F F IN A A A

50 apacitor Mismatch alibration (3) The digital output goes from to 5 when the input changes from V R to +V R. Apply V j close to the comparator threshold and force the flash A output so that the residue is once in region j and then in region (j+). The redundancy/offset correction range in the architecture prevents the A from clipping. The backend A gives two different codes for the same input voltage. Slides by Bibhudatta Sahoo -5-

51 apacitor Mismatch alibration (4) Applying V j to the A in region j we get,, j j j Similarly applying V j and forcing the flash A output to be in region (j+) we get, Since, same voltage is applied we can equate both of them: j, f, j, f j, j, f, j j j which is not dependent on gain error. Repeat the above steps for j= to 5. Slides by Bibhudatta Sahoo -5-

52 Slides by Bibhudatta Sahoo -52- apacitor Mismatch alibration (5) Thus we end up with: 5,5,5, 5 4,4,4, 4 3,3,3, 3 2,2,2, 2,,,,,, 9,9,9, 9 8,8,8, 8 7,7,7, 7 6,6,6, 6 5,5,5, 5 4,4,4, 4 3,3,3, 3 2,2,2, 2,,, f f f f f f f f f f f f f f f,5,5,,4,4,,3,3,,2,2,,,,,,,,9,9,,8,8,,7,7,,6,6,,5,5,,4,4,,3,3,,2,2,,,, f f f f f f f f f f f f f f f Solving for j is straight forward and does not require multiplication.

53 Slides by Bibhudatta Sahoo -53- apacitor Mismatch alibration (6) Thus j can be obtained as follows without the need of multipliers:,5,5,,4,4,,3,3,,2,2,,,,,,,,9,9,,8,8,,7,7,,6,6,,5,5,,4,4,,3,3,,2,2,,,, f f f f f f f f f f f f f f f ombining the bits with appropriate j : Flash A output tells us which region the analog voltage is in. The above information can be used appropriately combine the bits.

54 Gain alibration for Multi-bit MA Slides by Bibhudatta Sahoo -54-

55 omputation of Need to obtain / eq, 2 / eq,, 6 / eq. Fortunately, We already have these values from previous measurements 55 Slides by Bibhudatta Sahoo -55-

56 omputation of 6 / eq Swap and 6 : Thus, is obtained. 56 Slides by Bibhudatta Sahoo -56-

57 Gain Error alibration () We can obtain a similar set of measurements by connecting 6 to V R (controlled by A ) and to V M. Instead of to 5 we can define to 5 as shown on the side. Similarly we can solve for to 5 by matrix inversion. Region : Region 2 : Region 3: Region 5: Region 6 : IN IN IN IN IN 6 6 F 6 6 F F F F F F Slides by Bibhudatta Sahoo i 6 i 6 i 6 6 i i 5 A F F F P P 5 5 A 5 5 P P P A A i A i i i i IN IN IN IN 2 IN 5 3

58 Slides by Bibhudatta Sahoo -58- Gain Error alibration (2) A i i P F X A i i P F F We can rewrite to 5 in terms to 6 as shown below: Similarly, we can rewrite to 5 in terms 2 to 6. Solving the two matrices we can obtain i /( F - X ) where, for i= to 6. Gain error, 6 i X F i

59 Gain Error alibration.5 bit stages Backend stages need gain error calibration. Perturbation based calibration []: Applying V IN we get and. Applying (V IN + ) we get and. Applying we get and. V IN and (V IN + ) should produce different codes. Thus, gain error is obtained as follows: V IN V IN [] B. Sahoo and B. Razavi, "A 2-Bit 2-MHz MOS A, IEEE Journal of Solid- State ircuits, vol. 44, pp , Sept. 29 Slides by Bibhudatta Sahoo -59-

60 Gain alibration for.5-bit Non-flip-around MA Slides by Bibhudatta Sahoo -6-

61 .5-Bit Stages where, is the gain. S and F cannot be swapped to obtain gain as it would lead to over-range. 6 Slides by Bibhudatta Sahoo -6-

62 alibration Algorithm* (.5-Bit Stages) Apply V mv Apply V REF /4 Apply V REF /4+V * B. Sahoo and B. Razavi, IEEE Journal of Solid-State ircuits, vol. 44, pp , Sept Slides by Bibhudatta Sahoo -62-

63 .5-Bit Stages - omputing Inverse Gain (/) Apply V Apply V REF /4, force comparator output to be Apply (V REF /4+V), force comparator output to be Inverse Gain = Obtained using Newton-Raphson iterative method instead of division. 63 Slides by Bibhudatta Sahoo -63-

64 Gain alibration for.5-bit Flip-around, 2.5-bit, etc. MA Slides by Bibhudatta Sahoo -64-

65 Gain alibration for.5-bit Flip-around MA () 65 V out = P A V in P V out = αv in KβV R, where α = A KV R, where K = ±, P A, and β = Slides by Bibhudatta Sahoo P A β can be solved by applying V T or V T2 and forcing the corresponding comparator to or. Unlike, an N-bit architecture as mentioned earlier we cannot swap the capacitors here to solve for α. Swapping capacitors changes the denominator P *. Ravi, V. Sarma, and B. Sahoo, IEEE NEWAS, June 25 A to P A

66 Gain alibration for.5-bit Flip-around MA (2) 66 V out = P A V in P V out = αv in KβV R, where α = A KV R, where K = ±, P A, and β = Applying V R the back-end A output can be given as: 2 Slides by Bibhudatta Sahoo P A V out = αv R βv R V out = 2 + V R = P A P A The β obtained using the comparator forcing algorithm can be added to the above measurement to obtain α *. Ravi, V. Sarma, and B. Sahoo, IEEE NEWAS, June 25 2

67 Gain alibration for 2.5-bit Flip-around MA V out = 67 8 i= i V in i= 8 V out = αv in β i V R i + P A 6 i= T i i i= 8 *. Ravi, V. Sarma, and B. Sahoo, IEEE NEWAS, June 25 i + P A V R omparator forcing based calibration technique is used to obtain β to β 6. Just as in.5-bit flip-around topology swapping capacitor changes the denominator and hence cannot be used to solve for the gain α. Applying the full-scale input to the MA and digitizing the output using the backend we obtain, = i= Now, β 6 = i= i= 8 i + P A i 8 i + P A α = + β 6 an be extended to 3.5-bit. Slides by Bibhudatta Sahoo -67-.

68 alibration at Full-Speed Speed of existing calibration methods are limited by ircuitry which applies the calibration inputs alibration at low speed doesn't capture the error in residue ue to insufficient settling of the op amp at high frequency Incorrect gain estimation In order to facilitate calibration at full-speed the calibration voltages have to be generated using capacitors switching to ±V R. This eliminates the resistor ladder to generate the calibration voltages. *. Ravi, V. Sarma, and B. Sahoo, IEEE NEWAS, June Slides by Bibhudatta Sahoo -68-

69 alibration Signal Generation for.5-bit Stage () Split the sampling capacitor and the feedback capacitor into two equal unit capacitors uring normal operation Sampling phase: Input is sampled onto all the capacitors Amplification phase: 2 capacitors are flipped around Remaining two capacitors switch to KV R *. Ravi, V. Sarma, and B. Sahoo, IEEE NEWAS, June Slides by Bibhudatta Sahoo -69-

70 alibration Signal Generation for.5-bit Stage (2) uring alibration, Sampling phase: VR sampled onto one sampling capacitors Remaining capacitors connected to ground for applying V T = VR/4. Amplification phase: Two capacitors connected to KV R Two capacitors flipped around Resulting residue voltage is V out = V R + KV R A This residue is same as if V IN = VR/4 is applied *. Ravi, V. Sarma, and B. Sahoo, IEEE NEWAS, June 25 7 Slides by Bibhudatta Sahoo -7-

71 alibration Signal Generation for.5-bit Stage (3) Similarly, we can mimic the generation of V T2 = VR/4 by Applying V R to one sampling capacitor Remaining connected to ground *. Ravi, V. Sarma, and B. Sahoo, IEEE NEWAS, June 25 7 Slides by Bibhudatta Sahoo -7-

72 Background Gain alibration for Multi-bit,.5-bit, 2.5-bit, etc. MAs Slides by Bibhudatta Sahoo -72-

73 Slides by Bibhudatta Sahoo -73- Pipeline Stage I/O haracteristic. and where, , 6 5, 6 6 5, A A V A V V V A V A V V A V A V V m m P F F i m m m P F F m R j m m j R j IN OUT m m P F F m R j m m IN OUT m m P F F m m R j m m IN m OUT ividing both sides by V R we get, where, j is the capacitor mismatch independent of op amp gain is the gain (G ) function of op amp gain. j IN j IN The input output characteristic of a 4-bit stage is: 9 73

74 Proposed alibration Algorithm Initially estimate the gain (=G ) and the capacitor mismatch ( j ) in the foreground using the calibration technique in. Then estimate the inter-stage gain α, in the background. 9 B. Sahoo, and B. Razavi, A -bit -GHz 33-mW MOS A, IEEE JSS, June 23. Slides by Bibhudatta Sahoo -74-

75 Pipelined Stage Residue haracteristic with MA Gain Variation 2-bit MA residue characteristics V res Vs V in with Gain variation 2-bit MA residue characteristics Vs V in with Gain variation MA gain (α) changes slope of the residue characteristic changes. Residue quantized by an ideal M-bit back-end to give a digital estimate,,, min= 2 M-2 and, max= 3 2 M-2 - Ideally =, max/vlsb/2. Parameter drift changes, min and, max. Slides by Bibhudatta Sahoo -75-

76 alibration Algorithm Estimate the MA gain, α in the foreground mode using technique in. Estimate,max in the background mode, immediately after the foreground calibration is done. Thus, =,max /V LSB /2. alibration engine keeps on estimating,max. If the gain drifts a new back-end maximum,,max2 is obtained, resulting in new =,max2 /V LSB /2. Thus, new max 2 max new max 2 max B. Sahoo, and B. Razavi, A -bit -GHz 33-mW MOS A, IEEE JSS, June 23. Slides by Bibhudatta Sahoo -76-

77 Effect of Non-Idealities The estimation of, MAX can be corrupted due to the following non-idealities: omparator Offset apacitor mismatch Thermal Noise Slides by Bibhudatta Sahoo -77-

78 Effect of omparator Offset With comparator offset maximum backend code changes from region to region, but slope in each region is the same. Maximum in any one region gives the accurate estimate of inter-stage gain The region should be such that the calibration can work even with lower signal swing For 2-bit MA, characteristic corresponding to output code of or 2 is chosen For 3-bit and 4-bit MAs calibration would work for /4 th and /8 th of the signal swing. Proposed calibration would thus require a minimum swing that is either 2 db or 8 db below full scale. Slides by Bibhudatta Sahoo -78-

79 Effect of apacitor Mismatch apacitor mismatch changes the residue/back-end characteristic. Although the slope is the same in each region the maximum in each region is different. alibration obtains the maximum back-end code for a particular region Slides by Bibhudatta Sahoo -79-

80 Effect of Thermal Noise Thermal noise corrupts the measurement of,max. Histogram of the back-end code estimates the true maximum code and eliminates the absolute maximum code. For a noisy bin to have the same height as that of a noiseless bin, the thermal noise should have a variance, σ NTH > LSB SNR degradation of approx. 3 db. Noisy bins cannot be of the same height as noiseless bins Slides by Bibhudatta Sahoo -8-

81 Multi-stage Gain alibration Algorithm first calibrates the 2 nd stage that has an ideal backend onsider the 2 nd stage onwards as an ideal back-end and calibrate the st stage alibration starts from the later stages and moves to the st stage Slides by Bibhudatta Sahoo -8-

82 igital Hardware omplexity Histogram requires counters and finding the maximum requires comparators. For M-bit back-end, do we need 2 M comparators and counters! No Foreground calibration gives an initial estimate of,max and noise corrupts this by maximum of ± to ±2 back-end codes Hence maximum of 4 digital comparators and counters used ivision operation is realized using Newton-Raphson technique, which requires a multiplier and adder Slides by Bibhudatta Sahoo -82-

83 Survey of igital alibration Techniques Slides by Bibhudatta Sahoo -83-

84 Survey of alibration Techniques Sl. No. Author (Year) Type of MA Foreground/ Background Notes. Lee (992) 2. Karanicolas (992) 3. Erdogan (999) 4. Ming (2) Multi-bit Foreground apacitor mismatch and gain error -bit Foreground Gain error -bit Background Gain error.5-bit nonflip around 5. Li (23).5-bit fliparound 6. Murmann (23) 7. Wang (24) 8. Verma (29) Background Background Gain error Gain error 3-bit Background apacitor mismatch, op amp nonlinearity, and gain error.5-bit fliparound.5-bit fliparound Background Foreground Gain error and capacitor mismatch. Gain error, op amp nonlinearity, and capacitor mismatch Slides by Bibhudatta Sahoo -84-

85 alibration of Multistep A () S-H. Lee and B-S. Song, IEEE JSS, vol. 27, pp , ec Slides by Bibhudatta Sahoo -85-

86 alibration of Multistep A (2) Error ( j ) and Error ( j + ) are the errors with digital codes j and j +. S-H. Lee and B-S. Song, IEEE JSS, vol. 27, pp , ec Slides by Bibhudatta Sahoo -86-

87 alibration of Multistep A (3) Measure the feedthrough voltage, i.e. offset, charge-injection, etc. hange the digital code by and measure the output voltage. When digital code is changed by then the change in the output should be exactly ½ V REF. Thus the Error ( j+ ) can be obtained from the above measurement and stored in memory. S-H. Lee and B-S. Song, IEEE JSS, vol. 27, pp , ec Slides by Bibhudatta Sahoo -87-

88 5-bit Self alibrated Pipelined A () V out = 2 + α + α V in V ref where, 2 = + α apacitor mismatch is merged with the gain term. A. Karanicolas and H. S. Lee, IEEE JSS, vol. 28, pp , ec Slides by Bibhudatta Sahoo -88-

89 5-bit Self alibrated Pipelined A (2) Measure two quantities S and S 2 by applying V in = and forcing = and =. Thus, the output can be given by, Y = X if = = X + S S 2 if =. alibration estimates only S and S 2 for each stage, stores them and then uses them in the digital calibration logic. alibration does not require multiplication. alibration starts from the later stages and moves to the earlier stages. ifficult for a multi-bit stage. A. Karanicolas and H. S. Lee, IEEE JSS, vol. 28, pp , ec Slides by Bibhudatta Sahoo -89-

90 Queue Based Algorithmic A alibration () Queue based background gain error calibration. Having n sample-and-hold (SHA) and choosing f c > f s, time slots for calibrating the A can be obtained without compromising the normal operation of the A. The number of SHAs is given by: n T cal T S where, T cal is the calibration time and T s = /f s. Each of the SHA adds noise and degrades the SNR of the A. Also the additional SHA s consume significant power. The paper demonstrates this for a Algorithmic A. It can also be extended to a pipelined A. O. E. Erdogan, P. J. Hurst, and S. H. Lewis, IEEE JSS, vol. 34, pp , ec Slides by Bibhudatta Sahoo -9-

91 Queue Based Algorithmic A alibration (2) O. E. Erdogan, P. J. Hurst, and S. H. Lewis, IEEE JSS, vol. 34, pp , ec Slides by Bibhudatta Sahoo -9-

92 Queue Based Algorithmic A alibration (3) After the queue is empty the A goes into calibration mode. The A uses a -bit architecture just like in Karanicolas 993. The nominal gain m < 2 to make sure that there are no missing levels. Since the actual value of m is not known an initial estimate of m is used to obtain the digital output: = N i= m i d i uring calibration an input of V is applied and the comparator output is forced to and to obtain respectively and. LMS is used to estimate m as per the following: m j + = m j + μ LSB O. E. Erdogan, P. J. Hurst, and S. H. Lewis, IEEE JSS, vol. 34, pp , ec Slides by Bibhudatta Sahoo -92-

93 8-bit Pipelined A With Background alibration ().5-bit MA architecture V out = S F + A + S + X A F V in kv REF V out = G I G E V in kv REF where, G I = S and G E = F + A + S + X A F Adjust V R = V R2 G E J. Ming and S. H. Lewis, IEEE JSS, vol. 36, pp , Oct. 2. to overcome the gain-error. Slides by Bibhudatta Sahoo -93-

94 8-bit Pipelined A With Background alibration (2) A pseudo-random generator generates a digital number. The random number is converted to analog by A. The output of A is digitized by the back-end A and by a slow-butaccurate A. The slow-but-accurate A output should be subtracted from the backend A output to recover the digital representation of Vin. The gain error of the stage can be obtained if e i does not contain the random input N(i). This is possible if: V n G V R2 V n V R = V R = V R2 G J. Ming and S. H. Lewis, IEEE JSS, vol. Slides by Bibhudatta Sahoo , pp , Oct. 2.

95 8-bit Pipelined A With Background alibration (3) Needs extensive analog hardware for calibration. The A in the calibration system should be accurate difficult to calibrate high resolution As (> - bits). alibration technique can effectively calibrate.5-bit/stage architecture and not multi-bit architecture. Extension to multi-bit architecture is very hardware intensive. Multi-stage calibration J. Ming and S. H. Lewis, IEEE JSS, vol. 36, pp , Oct. 2. Slides by Bibhudatta Sahoo -95-

96 Radix Based alibration () V O = + S + F A F S + F F V O = + δ 2 + α V i where, + δ = and + β = S F V i S F V ref + β 2 + α V ref F, + S + F A F, 2 + α = S+F V O = 2 S F + 2 V S + i F 2 V ref A F V O = + δ 2 + α V i V ref where, + δ = + S + F A and 2 + α = S+ F F, J. Li and Un-Ku Moon, IEEE TAS-I, vol. 5, pp , Sept. 23. Slides by Bibhudatta Sahoo -96-

97 Radix Based alibration (2) Representation of the pipelined A with each stage using.5-bit non-flip around topology. The digital output can be represented as: O = n + n ra + n ra ra n where, ra = + δ 2 + α and reference voltage of each stage is scaled. Since the reference is scaled for each stage this is not attractive. However if each stage uses a non-flip-around topology then, O = n + n ra + n ra ra n where, ra = + δ 2 + α and reference voltage of each stage is not scaled. J. Li and Un-Ku Moon, IEEE TAS-I, vol. 5, pp , Sept. 23. Slides by Bibhudatta Sahoo -97-

98 Radix Based alibration (3) The new radix is. ra = + β i + δ i 2+α i+ +β i+. The reference voltage is not scaled from stage-to-stage. J. Li and Un-Ku Moon, IEEE TAS-I, vol. 5, pp , Sept. 23. Slides by Bibhudatta Sahoo -98-

99 Radix Based alibration (4) J. Li and Un-Ku Moon, IEEE TAS-I, vol. 5, pp , Sept. 23. Slides by Bibhudatta Sahoo -99-

100 Radix Based alibration (5) Large convergence time as has to be correlated for a long time to guarantee that P N res vanishes. Generation of precise analog voltage V PN whose digital value is PN. Reduction in dynamic range of the A due to injection of pseudorandom voltage V PN. J. Li and Un-Ku Moon, IEEE TAS-I, vol. 5, pp , Sept. 23. Slides by Bibhudatta Sahoo --

101 Open Loop Op amp Nonlinearity alibration () B. Murmann and B. E. Boser, IEEE JSS, vol. 38, pp , ec. 23. The 2-bit pipelined A incorporates: 3-bit stage- realized using open-loop amplifier. -bit stage-2 (with redundant bit to incorporate the signal injection for calibration). Seven.5-bit stages 3-bit flash A. Although 4-bits of raw data the last two bits are used for calibration purpose. Only stage- is calibrated for linear gain error and nonlinearity. All other stages form an ideal Back-end A. Slides by Bibhudatta Sahoo --

102 Open Loop Op amp Nonlinearity alibration (2) Amplifier Model Stage- that incorporates an open-loop amplifier is modeled as per the above block diagram with various error sources: V OS op amp offset gain error modeled by calibration parameter p. a 3 3 rd order nonlinear term of the open-loop op amp. B. Murmann and B. E. Boser, IEEE JSS, vol. 38, pp , ec. 23. Slides by Bibhudatta Sahoo -2-

103 Open Loop Op amp Nonlinearity alibration (3) Amplifier model with input referred nonlinearity e V res = V res 2 3p 2 cos π cos where, V res is digitized by the back-end A and a 3 p 2 = Amplifier model with output referred nonlinearity 2 B. Murmann and B. E. Boser, IEEE JSS, vol. 38, pp , ec. 23. V res 27p 2 Slides by Bibhudatta Sahoo -3-

104 Open Loop Op amp Nonlinearity alibration (4) A igital ombiner e b = b 2 3p 2 cos π cos 2 B. Murmann and B. E. Boser, IEEE JSS, vol. 38, pp , ec. 23. Slides by Bibhudatta Sahoo -4- b 27p 2 where, b is the back-end A output and the calibration engine estimates p 2.

105 Open Loop Op amp Nonlinearity alibration (5) V res can generate two curves based on the digital random-bit MOE. In order to accommodate the two transfer curves and not saturate the back-end A stage-2 has -bit of redundancy. The residue characteristic with nonlinearity shows compression. Nonlinearity is overcome if h = h 2, i.e. the distance between the two residue characteristic is constant at all points. Its sufficient to estimate the distance at the center and at the extremes. B. Murmann and B. E. Boser, IEEE JSS, vol. 38, pp , ec. 23. Slides by Bibhudatta Sahoo -5-

106 Open Loop Op amp Nonlinearity alibration (6) B. Murmann and B. E. Boser, IEEE JSS, vol. 38, pp , ec. 23. Slides by Bibhudatta Sahoo -6-

107 Open Loop Op amp Nonlinearity alibration (7) Estimation of the gain error (p ) is similar to the method in Li23. Estimation of nonlinearity (p 2 ) is based on an LMS method which minimizes the MSE of H H 2. H H 2 is a function of p 2 as per e b = b 2 3p 2 cos π cos b 2 27p 2 B. Murmann and B. E. Boser, IEEE JSS, vol. 38, pp , ec. 23. Slides by Bibhudatta Sahoo -7-

108 Open Loop Op amp Nonlinearity alibration (8) Requires that the inputs be sufficiently busy, i.e., the analog input to the A be such that it exercises all the A levels. If the signal is not full scale then the calibration cannot estimate the nonlinearity. As shown below in the residue characteristic of stage-, if the signal is within /6 th of the full scale then also it exercises the full-scale of the back-end A and hence estimates the nonlinearity. The open-loop amplifier is very susceptible to gain variation due to temperature. If the LMS loop has a smaller time-constant as opposed to the gain variation then the calibration works. B. Murmann and B. E. Boser, IEEE JSS, vol. 38, pp , ec. 23. Slides by Bibhudatta Sahoo -8-

109 Nested igital Background alibration () The algorithmic A and Pipelined A are realized using.5- bit flip-around topology whose input-output characteristic is given by, V O = where, 2 + ε g = S + F + V S + F i F + S + F A F A F V O = 2 + ε g V i + ε A V ref S + F, and + ε A = F + S + F A F S F V ref X. Wang, P. J. Hurst, and S. H. Lewis, IEEE JSS, vol. 39, pp , Nov. 24. Slides by Bibhudatta Sahoo S + F A F S F

110 Nested igital Background alibration (2) igital output computation from the raw bits, V i = V R. 5 + ε b ε 2 b 2 + q a ε 3 where, ε = ε 2, ε 2 = ε + ε 22 + ε ε 2, ε 3 = ε + ε 2 + ε ε 2, and q a is the quantization noise. So 4 parameters are needed for a 2-stage pipeline Three (ε, ε 2, and ε 3 ) for the gain errors One more for the overall offset of the pipelined stages. For a K-stage A, (K+2) parameters need to be estimated, including the offset term. X. Wang, P. J. Hurst, and S. H. Lewis, IEEE JSS, vol. 39, pp , Nov. 24. Slides by Bibhudatta Sahoo --

111 Nested igital Background alibration (3) Pipelined A core has 3- stages. First 5-stages are calibrated. igital output computation from the raw bits, pip (V i ) = 3 i=. 5 i b i + i= X. Wang, P. J. Hurst, and S. H. Lewis, IEEE JSS, vol. 39, pp , Nov i ε i b i q + offset LMS optimization can be used to minimize the error, e = pip alg The update equation is, ε i m + = ε i m + μ pip e e ε i Slides by Bibhudatta Sahoo --

112 Nested igital Background alibration (4) For ε to ε 5, the derivative of MSE is zero, E e 2 = E 2e e = E 2e pip ε i ε i ε i = 2. 5 i E e b i = i 5. For ε 6, E e 2 = E 2e e = E 2e pip ε 6 ε 6 ε 6 = E e q = For offset, E e 2 = E 2e e (os) (os) = E 2e pip (os) = 2E e = X. Wang, P. J. Hurst, and S. H. Lewis, IEEE JSS, vol. 39, pp , Nov. 24. Slides by Bibhudatta Sahoo -2-

113 Nested igital Background alibration (5) The algorithmic A is calibrated based on the calibration technique proposed by Erdogan 999. Erdogan used a -bit architecture for the stage. Here.5-bit flip-around topology is used instead. X. Wang, P. J. Hurst, and S. H. Lewis, IEEE JSS, vol. 39, pp , Nov. 24. Slides by Bibhudatta Sahoo -3-

114 -bit 5 MHz 55 mw MOS A () A. Verma and B. Razavi, IEEE JSS, vol. 44, pp , Nov. 29. All stages use.5-bit flip-around topology. Gain error, capacitor mismatch, and op amp nonlinearity correction done in the st two stages. Gain error and capacitor mismatch calibration done in stage 3 to 6. No calibration for the remaining stages. LMS is used to do gain error and op amp nonlinearity calibration. Slides by Bibhudatta Sahoo -4-

115 -bit 5 MHz 55 mw MOS A (2) alibration requires a precision A. For the -bit system here the reference A has to be -bit linear alibration applies VR/2, VR/4, and from the reference A to stage-j for calibration. Stage-j is configured in multiply-by-2 configuration. The digitized output of stage-j is given by tot = α BK + α 3 BK and 3 are updated using the following LMS equation: α k + = α k + μ cal tot BK 3 α 3 k + = α 3 k + μ cal tot BK 3 A. Verma and B. Razavi, IEEE JSS, vol. 44, pp , Nov. 29. Slides by Bibhudatta Sahoo -5-

116 -bit 5 MHz 55 mw MOS A (3) A. Verma and B. Razavi, IEEE JSS, vol. 44, pp , Nov. 29. Slides by Bibhudatta Sahoo -6-

117 -bit 5 MHz 55 mw MOS A (5) alibration requires a precision A. For a-bit system the reference A has to be -bit linear For a 2-bit system the reference A has to be 3-bit linear ifficult to realize highly linear and precise As The calibration technique cannot be used to calibrate more than -bit systems. alibration applies signals from the resistor ladder calibration cannot be run at the full-speed of the A because of the R-settling issue. High frequency settling behavior of the op amps is not captured. A. Verma and B. Razavi, IEEE JSS, vol. 44, pp , Nov. 29. Slides by Bibhudatta Sahoo -7-

118 onclusion In the last 2 years various digital calibration techniques have been developed. Goal is to overcome various circuit non-idealities like finite op amp gain, op amp nonlinearity, and capacitor mismatch. igital calibration techniques can be categorized as: Background Foreground igital calibration technique calibrates for: apacitor mismatch Linear Gain Error Op amp nonlinearity Slides by Bibhudatta Sahoo -8-

119 Thank You 9 Slides by Bibhudatta Sahoo -9-

120 References Scaling Trends: [] S. Borkar, esign challenges of technology scaling, IEEE Micro, vol. 9, no. 4, pp , 999. [2] K. Bult, The Effect of Technology Scaling on Power issipation in Analog ircuits, in Analog ircuit esign, M. Steyaert, et. al., Eds. Springer, 26, pp [3] B. Murmann, A Performance Survey [Online]. Available: [4] B. Murmann, Limits on A Power issipation, in Analog ircuit esign, M. Steyaert, A. H. M. Roermund, and J. H. van Huijsing, Eds. Springer, 26. [5] T. Sundstrom, B. Murmann, and. Svensson, Power issipation Bounds for High-Speed Nyquist Analog-to-igital onverters, IEEE Trans. ircuits and Systems-I, vol. 56, pp , Mar. 29. [6] P. Kinget and M. Steyaert, Impact of transistor mismatch on the speed-accuracy-power trade-off of analog MOS circuits, Proc. I, 996, pp [7] M. J. M. Pelgrom, H. P. Tuinhout, and M. Vertregt, Transistor matching in analog MOS applications, Proc. IEM, 998, pp [8] E. A. Vittoz, Future of analog in the VLSI environment, Proc. ISAS, 99, pp [9] B. J. Hosticka, Performance comparison of analog and digital circuits, Proc. of the IEEE, vol. 73, no., pp , 985. [] E. A. Vittoz and Y. P. Tsividis, Frequency-ynamic Range-Power, in Trade-Offs in Analog ircuit esign,. Toumazou, et. al., Eds. Boston: Kluwer Academic Publishers, 22, pp [] A. Marques, V. Peluso, M. Steyaert, and W. Sansen, Analysis of the trade-off between bandwidth, resolution, and power in ΔΣ analog to digital converters, Proc. IES, 998, pp Slides by Bibhudatta Sahoo -2-

121 References 2. Y. hiu, Scaling of analog-to-digital converters into ultra-deep submicron MOS, Proc. I, pp , Sep A.-J. Annema, et al., "Analog ircuits in Ultra-eep-Submicron MOS," IEEE J. Solid-State ircuits, vol. 4, no., pp , Jan. 25. Pipelined A Overview and esign Strategies: [4] Stephen H. Lewis, Video-Rate Analog-to-igital onversion Using Pipelined Architectures, Ph Thesis, University of alifornia, Berkeley, 987 [5] Thomas ho, Low-Power Low-Voltage Analog-to-igital onversion Techniques Using Pipelined Architectures, Ph Thesis, University of alifornia, Berkeley, 995 [6]. W. line, Noise, Speed, and Power Trade-offs in Pipelined Analog-to-igital onverters, Ph Thesis, University of alifornia, Berkeley, 995 [7] Rudy Van Plassche, MOS Integrated Analog-to-igital and igital-to-analog onverters, Springer, 2nd edition, 23 [8] I. Mehr and L. Singer, "A 55-mW, -bit, 4-Msample/s Nyquist-Rate MOS A ", IEEE J. Solid-State ircuits, vol. 35, pp , Mar 2. [9] Hirotomo Ishii, Ken Tanabe, Tetsuya Iida, A.V 4mW b MS/s Pipeline A in 9nm MOS, IEEE I, pp , Sept. 25 [2] B. Sahoo and B. Razavi, "A Fast Simulator for Pipelined A/ onverters," Proc. Midwest Symp. on ircuits and Systems, pp , August 29. [2]. Y. hang, "esign Techniques for a Pipelined A Without Using a Front-End Sampleand-Hold Amplifier", IEEE Trans. on ircuits and Systems-I, vol. 5, no., pp , Nov. 24. Slides by Bibhudatta Sahoo -2-

122 References [22] B. Razavi, Principles of ata onversion System esign, Wiley-IEEE Press; edition, 994 [23] F. Maloberti, ata onverters, Springer; 27 [24] M. J. M. Pelgrom, Analog-to-igital onversion, Springer; 2nd edition, 23 alibration Techniques for Pipelined As: [25] S-H. Lee and B-S. Song, igital-omain alibration of Multistep Analog-to-igital onverters, IEEE J. Solid-State ircuits, vol. 27, pp , ec [26] A. Karanicolas and et. al., "A 5-b -Msamples/s igitally self-calibrated Pipeline A", IEEE J. Solid-State ircuits, vol. 28, pp , ec 993. [27] P.. Yu and H.-S. Lee, "A 2.5-V, 2-b, 5-MSsamples/s Pipelined MOS A", IEEE J. Solid- State ircuits, vol. 3, no. 2, pp , ec [28] U.-K. Moon and B.-S. Song, "Background igital alibration Techniques for Pipelined A's", IEEE Trans. ircuits Syst. II, vol. 44, pp. 2 9, Feb [29] J. M. Ingino and B. A. Wooley, "A ontinuously alibrated 2-b, -MS/s, 3.3-V A/ onverter", IEEE J. Solid-State ircuits, vol. 33, pp , ec [3] O. E. Erdogan, P. J. Hurst, and S. H. Lewis, A 2-b igital-background-alibrated Algorithmic A with 9-dB TH, IEEE J. Solid-State ircuits, vol. 34, pp , ec [3] E. Siragusa and I. Galton, "Gain Error orrection Technique for Pipelined Analogue-to-igital onverters", Electronics Letters, pp , Mar. 2. [32] J. Ming and S. H. Lewis, An 8-bit 8-Msample/s Pipelined Analog-to-igital onverter With Background alibration, IEEE J. Solid-State ircuits, vol. 36, pp , Oct. 2. Slides by Bibhudatta Sahoo -22-

123 References [33] J. Li and U.-K. Moon, "Background alibration Techniques for Multistage Pipelined As With igital Redundancy", IEEE Trans. on ircuits and Systems-II, vol. 5, no. 9, pp , Sept. 23. [34] B. Murmann and B. E. Boser, "A 2-b 75 MS/s Pipelined A using Open-Loop Residue Amplification", IEEE J. Solid-State ircuits, vol. 38, pp , ec 23. [35] E. Siragusa and I. Galton, "A igitally Enhanced.8-V 5-bit 4-MSamples/s MOS Pipelined A", IEEE J. Solid-State ircuits, vol. 39, pp , ec 24. [36] X. Wang, P. J. Hurst, and S. H. Lewis, A 2-Bit 2-Msample/s Pipelined Analog-to-igital onverter With Nested igital Background alibration, IEEE J. Solid-State ircuits, vol. 39, pp , Nov. 24. [37]. R. Grace, P. J. Hurst, and S. H. Lewis, "A 2b 8MS/s Pipelined A with Bootstrapped igital alibration", IEEE J. Solid-State ircuits, vol. 4, pp , May 25. [38] I. Ahmed and. A. Johns, "An -bit 45-MS/s, Pipelined A with Rapid alibration of A Errors in a Multibit Pipeline Stage", IEEE J. Solid-State ircuits, vol. 43, no. 7, pp , July 28. [39] B.. Sahoo and B. Razavi, "A 2-Bit 2-MHz MOS A", IEEE J. Solid-State ircuits, vol. 44, no. 9, pp , Sept. 29. [4] A. Verma and B. Razavi, "A -b 5-MHz 55-mW MOS A", IEEE J. Solid-State ircuits, vol. 44, no., pp , Nov. 29. [4] A. Panigada and I. Galton, "A 3 mw MS/s Pipelined A with 69 db SNR Enabled by igital Harmonic istortion orrection", IEEE J. Solid-State ircuits, vol. 44, pp , ec. 29. [42] B. Sahoo and B. Razavi, "A -b -GHz 33-mW MOS A", Symposium on VLSI ircuits ig. Of Tech. Papers, pp. 3-3, June 23 Slides by Bibhudatta Sahoo -23-

124 References [43] B. Sahoo and B. Razavi, "A -b -GHz 33-mW MOS A", IEEE J. Solid-State ircuits, vol. 48, no. 6, pp , June 23. [44]. Ravi, R. Thottathil, and B. Sahoo, "A Histogram Based eterministic igital alibration Technique for Pipelined A", 27th Intl. onf. on VLSI esign, India, pp , Jan. 24. [45] H. Wei, P. Zhang, B. Sahoo, and B. Razavi, An 8-Bit 4-GS/s 2-mW MOS A, IEEE Journal of Solid State ircuits, Vol. 49, No. 8, pp , Aug. 24 [46] (invited) B. Sahoo, An Overview of igital alibration Techniques for Pipelined As, 57 th IEEE International Midwest Symposium on ircuits and Systems, ollege Station, USA. [47]. Ravi, V. Sarma, and B. Sahoo, At Speed igital Gain Error alibration of Pipelined As, IEEE NEWAS, June 25 Slides by Bibhudatta Sahoo -24-