Advanced Analog Integrated Circuits. Operational Transconductance Amplifier I & Step Response

Transcription

1 Advanced Analog Integrated Circuits Operational Transconductance Amplifier I & Step Response Bernhard E. Boser University of California, Berkeley boser@eecs.berkeley.edu Copyright 2016 by Bernhard Boser 1

2 High-Level View Transistors are transconductors Some OTA designs consist of >40 transistors Only few (typically 1 2) provide the transconductance in the signal path The rest is support, e.g. increasing low frequency gain output voltage range biasing Hierarchical design strategies are imperative Unless you like nodal equations for 40 transistors 2

3 Divide and Conquer 3

4 In SC Circuit 4

5 In SC Circuit Amplifier is active only in φ " : 5

6 Capacitive Feedback Simulation R $% 20 GΩ 6

7 Small-Signal Model Absorb C gd, C db, etc. in C f, C L, 7

8 Advanced Analog Integrated Circuits Loop-Gain & Stability Bernhard E. Boser University of California, Berkeley Copyright 2016 by Bernhard Boser 8

9 Model 9

10 Loop-Gain Analysis 10

11 Loop-Gain T(s) T s = β g 1 s 2 C 4565 Feedback factor β = v % v 6 = Effective Load Capacitance C C C C + C $ + C % 1 a H6 C 4565 = C β C C 11

12 Frequency Response of T(s) T(jw) T s = βg 1 s 2 C 4565 T o w ω R T 6 ω R = βg 1 C o w -90 o 12

13 Advanced Analog Integrated Circuits Closed-Loop Response Bernhard E. Boser University of California, Berkeley Copyright 2016 by Bernhard Boser 13

14 Closed-Loop Analysis Feedback-Only Model Generalized Model Ref: P. Hurst, A comparison of two approaches to feedback circuit analysis, IEEE Trans. edu., Aug. 1992, pp

15 Closed-Loop Transfer Function 15

16 A T 16

17 d 17

18 Closed-Loop Gain A s = A T T s 1 + T s + d 1 + T s = C $ C C = C $ C C C C 1 s g s C = 4565 βg 1 βg 1 s 2 C βg + 1 s 2 C 4565 s C $ 1 z C C 1 s p β C $ C βg 1 s 2 C 4565 p = βg 1 C 4565 z = + g 1 C C 18

19 Advanced Analog Integrated Circuits Stability and T(s) with Simulator Bernhard E. Boser University of California, Berkeley Copyright 2016 by Bernhard Boser 19

20 T(s) Verification with Simulator Infinite impedance point to break loop usually not accessible E.g. inside transistor [ Hspice manual ] 20

21 Workaround (Don t do this!) v return C 2 Vo C 1 1Gig Mock Load v test [ Drawing by B. Murmann ] 21

22 General Problem Any single loop feedback circuit can be represented as: available breakpoint Z 1 v x Z 2 T ( s) = g m Z Z 1 1 Z + Z 2 2 g m v x [ Drawing by B. Murmann ] Breakpoint at ideal source is not available. But there is a breakpoint between finite impedances 22

23 Middlebrook Double Injection Method v x v test (ac) Z 1 Z 2 v y v v y x º T v = g m Z 2 + Z Z 2 1 Solving yields: i x i y True Loop Gain: T = g m Z1Z2 Z + Z 1 2 T = TvTi -1 T + T + 2 v i Z 1 Z2 i i y x º T i = g m Z 1 + Z Z 1 2 i test (ac) [ Drawing by B. Murmann ] [ Middlebrook 75 ] No DC break in the loop, all loading effects covered. Measure T v and T i, then calculate actual T Variant implemented in many simulators, e.g. stb-analysis in Spectre 23

24 SPICE 24

25 Multiple Feedback Loops Break all loops at a single point If such a point does not exist: [Bode 45] If a circuit is stable when all its tubes have their nominal gains, the total number of clockwise and counterclockwise encirclements of the critical point must be equal to each other in the series of Nyquist diagrams for the individual tubes obtained by beginning with all tubes dead and restoring the tubes successively in any order to their nominal gains Suggestion: take a controls class if your circuit depends on this! 25

26 Nonlinearities Real circuits are nonlinear frequency response depends on signal amplitude. Bode:... thus the circuit may sing when the tubes begin to lose their gain because of age, and it may also sing, instead of behaving as it should, when the gain increases from zero as power is supplied to the circuit... Always run a large signal transient analysis for a complete stability check! With realistic (large) signal amplitudes including overload Power supply ramping. Is a special order required? 26

27 Advanced Analog Integrated Circuits Settling Bernhard E. Boser University of California, Berkeley Copyright 2016 by Bernhard Boser 27

28 Step Response 28

29 Closed-Loop Gain Use favorite analysis method, e.g. return-ratio analysis*, nodal analysis, A s = V 6(s) V \ (s) = C $ C C C C 1 s g s C = 4565 βg 1 s C $ 1 z C C 1 s p ω^= βg 1 C 4565 ω defg hi j $ = ω R hi k($) ω ] ω^ ω ] = g 1 C C = C 4565 βc C usually 1 *Note: 2-port analysis ignores the feedforward path and therefore does not get the zero 29

30 Dynamic Error (no zero) Assume switch onresistance contribution to settling is negligible 30

31 Dynamic Settling Error 31

32 Dynamic Settling Error (single pole) ε d t s τ 1% % %

33 Amplifier Bandwidth versus f s ε f f defg f $ 1% % %

34 Static Settling Error 34

35 Example C $ = 4pF C C = 1pF C % = 1pF g 1 r 6 =

36 Dynamic Error (with zero) Instant response to step determined by capacitive feed-forward C C 1 s g 1 A s = V 6(s) V \ (s) = C $ C C 1 + s C 4565 βg 1 z = + g 1 C C p = βg 1 C

37 Step Response with Zero v 6,$5x^ t = V $5x^ 2 G \ 1 1 p z ed5 1 p z = 1 C C 1 β C C + C 4 t $ = τ ln ε f C C 1 β C C + C 4 37

38 Advanced Analog Integrated Circuits Phase Margin Bernhard E. Boser University of California, Berkeley Copyright 2016 by Bernhard Boser 38

39 Cascode 39

40 Phase Margin f^" Phase Margin f R 90 o 5 ~80 o 1/5 ~28 o 40

41 Step Response v s ( t, 1) v s ( t, 3) v s ( t, 100) 1-e - t t 10 41

42 Relative Settling Error for f^" f R = e s ( t, 3) e - t t 10 42

43 Settling Time versus f^" f R ε f = 0.1% t s ( e, K) - ln( e ) K f^" f R 10 43

44 Noise [ B. Murmann ] 44

45 Advanced Analog Integrated Circuits Design Example Bernhard E. Boser University of California, Berkeley Copyright 2016 by Bernhard Boser 45

46 Design Example: Specification 46

47 Design: Gain & Feedback Factor 47

48 Design: Dynamic Range 48

49 Design: Settling 49

50 Design: Power Dissipation 50

51 Could we go Faster? 51

52 Advanced Analog Integrated Circuits Gain Boosting Bernhard E. Boser University of California, Berkeley Copyright 2016 by Bernhard Boser 52

53 Openloop Gain a H6 = g 1 R 6 53

54 Openloop Gain a H6 = g 1 R 6 54

55 Gain Boosting 55

56 Gain Boosting Use feedback to boost lowfrequency output resistance References B. J. Hosticka, Improvement of the gain of MOS amplifiers, JSSC, Dec. 1979, pp E. Sackinger and W. Guggenbuhl, A high-swing high-impedance MOS cascode circuit, JSSC, Feb. 1990, pp K. Bult, G. Geelen, A fast-settling CMOS op-amp for SC circuits with 90-dB DC gain, JSSC, Dec. 1990, pp

57 High Frequency Analysis 57

58 Overall Amplifier Response v 6 v \ ω ] ω 6 f Doublet Ref: M. Das, Improved design criteria of gain boosted CMOS OTA with high-speed optimizations, IEEE CAS II, March 2002, pp

59 Advanced Analog Integrated Circuits Pole-Zero Doublets Bernhard E. Boser University of California, Berkeley Copyright 2016 by Bernhard Boser 59

60 Pole-Zero Doublets Ref: Y. Kamath, R. G. Meyer, and P. R. Gray, Relationship between frequency response and settling time of operational amplifiers, IEEE J. Solid-State Circuits, pp , Dec

61 Doublet Settling Amplifier model: replace G mo with G m ( s) = G mo s 1+ wz s 1+ w p Notation from Y. Kamath, R. G. Meyer, and P. R. Gray, Relationship between frequency response and settling time of operational amplifiers, IEEE J. Solid-State Circuits, pp , Dec

62 Doublet Settling Amplifier model: replace G mo with G m ( s) = G mo s 1+ wz s 1+ w p w p = bw-3db, w-3db w p with wz = a a = 1+ e with e << 1 isbandwidth of T ( s) Closed-loop response V V o in = -c 1+ s 1 C FG Leff m ( s) - s 1+ w æ s ç 1+ ç wz ç s ç1+ è w -3dB pp ö ø with w -3dB w pp = FG w p mo Leff Notation from Y. Kamath, R. G. Meyer, and P. R. Gray, Relationship between frequency response and settling time of operational amplifiers, IEEE J. Solid-State Circuits, pp , Dec

63 Doublet Step Response v o, step ( ) ( ) -tw -tw t -cv 1+ Ae + Be -3dB = step pp with -1 b e b 63

64 Doublet Example v s_no_doublet ( t) v s_doublet_term ( t, a, b) v s_doublet ( t, a, b) t 10 a = 1.5 b = v s_no_doublet ( t) ( ) 1-v s_doublet t, a, b t 16 64

65 Gain Boosting Doublets 65