UNIVERSITÀ DEGLI STUDI DI CATANIA. Dottorato di Ricerca in Ingegneria Elettronica, Automatica e del Controllo di Sistemi Complessi, XXII ciclo

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1 UNIVERSITÀ DEGLI STUDI DI CATANIA DIPARTIMENTO DI INGEGNERIA ELETTRICA, ELETTRONICA E DEI SISTEMI Dottorato di Ricerca in Ingegneria Elettronica, Automatica e del Controllo di Sistemi Complessi, XXII ciclo Dott. Ing. Davide Marano REVERSED NESTED MILLER FREQUENCY COMPENSATION SWITCHED-CAPACITOR Σ A/D CONVERTER Tutor: Prof. G. PALUMBO Coordinatore: Prof. L. FORTUNA XIX Brainstorming Day 3rd October 009, Catania

2 Frequency Compensation in Feedback Amplifiers Each compensation technique must ensure stability for all possible feedback configurations. If the feedback factor f is not specified, compensation should be performed in the worst-case, with the highest GBW (f=1 and T 0 =A 0 ). G Fo (s) = V out (s) V (s) in G F (s) ω =ω c T(s) T ω = ω = G p = A p = ω = ω GF GF A A GBW T Fo F1 0 1 T GBW As the GBW of the loop-gain equals the closed-loop pole, frequency analysis of the open-loop gain not only gives information on closed-loop stability, but is the fundamental base for determining the maximum achievable bandwidth.

3 NMC vs. : Analytic Comparison RHP zero CC CC1CC 1 s s A0 gm3 gm gm3 A( s) = s 1 1 C C p g g g g C L CC s s 1 m m3 m m3 CC CC1CC 1 s s A0 gm gmgm3 A( s) = s C C C C C C s + p g C g g g g C L C C L C 1 m3 C1 m3 m m m3 RHP zero s NMC Inner amplifier Since C C has no connection to the load capacitor, the inner amplifier is a single-pole system. As a consequence, inner loop stability is virtually achieved for all values of C C. turns out to be more power efficient than NMC for the same bandwidth, or attains a larger bandwidth than NMC for the same power consumption.

4 Analytic and Numeric Figures of Merit In order to be able of judging the effectiveness of all the analyzed compensation approaches, a very important analytic figure of merit has been introduced, which compares, for a specific design condition and loading capacitance, the amplifier closed-loop bandwidth to the power consumption which is necessary to realize it. G G Nm1 Nm = = g g g g m1 m 3 m m 3 Normalized gain stage transconductances ωgbw C F. O. M. = gm i Analytic figure of merit i L ω ω GBW GBW = π f g = C m1 C1 GBW Open-loop amplifier gain-bandwidth product In order to provide a performance comparison among the simulated amplifier topologies, four fundamental numeric figures of merit are commonly employed: FOM S = f V GBW DD. C I DD L FOM L = SR C V DD. L I DD IFOM S = f GBW I DD. C L IFOM L = SR C I. L DD

5 : Feedforward and Nulling Resistors g m1 g m3 g m A( s) 1 g R 1 g 1+ RC + R + R + C s + RR + + R C C s mff mff C1 C C C C1 C A0 gm gmgm3 gm3 gmgm3 gmgm3 = s CC CL CC 1 gmff CC CL RC CC s s p gm3cc 1 gm3 gm gmg m3 gmg m3 Dominant pole from Miller effect Right-half plane zero s -coefficient

6 : Voltage and Current Buffers CF-FF-NR technique g m1 g m g m3 VF-FF-NR technique g m3 g m1 g m

7 : Feedforward and Dual-Active Buffers g m g m1 g m3 A V ( s) ( ) ( s) ( ) ( + ) Vout s AV rc CC 1 + rv CC s + rc rv CC1CC s V in s C C C r ω g p1 m 3CC1 g m 3 C L C1 c rv CC s CC C L s Dominant pole from Miller effect Right-half plane zero s -coefficient

8 Step-Response Optimization Techniques Proposed solution A Proposed solution B Performance parameter Basic OTA First strategy Second strategy proposed solution A C L (pf) Power (µw) A V0 (db) f GBW (MHz) φ (deg) SR + /SR - (V/µs) ( * ) 1.66/ / /1.71 1% T S + /T S - (ns) ( * ) 0.1% T S+ /T S- (ns) ( * ) 40/ / / /660 40/ /640 proposed solution B original RNM amplifier (*) In unity-gain feedback configuration.

9 : Analytical Figure of Merit Comparison 6 G Nm =0.5, φ =70, c NC =0.01, G Nmv =0.5, G Nmc =0.5 9 G Nm =0.5, φ =70, c NC =0.01, G Nmv =0.1, G Nmc =1 5 -FF -FF-NR -CF-FF-NR -VF-CF-FF 8 7 -FF -FF-NR -CF-FF-NR -VF-CF-FF 4 6 FOM 3 1 FOM G Nm G Nm1 ( ) FOM VF CF FF φ B = Nm1 1 + G + Nm1 G + Nm GNmv cnc tan B G + Nm1 tan B 1 1 c NC VF CF FF = tan GNm1 + GNmv GNm1( GNm1+ tan φ ) ( ) 1 G ( φ φ ) ( φ φ )

10 Analytical F.O.M. Comparison Transistor-level Spectre simulations are in excellent agreement with the expected results. Technique G Nm1 G Nm A 0 (db) C C1 /C C (pf) PM (deg) f GBW (MHz) SR (V/µs) Power (µw) FOM Analyt. FOM Simul. FF / FF-NR / FF-NR / CF-FF / CF-FF-NR / VF-FF / VF-FF-NR / VF-FF-NR / VF-CF-FF /

11 : Monte Carlo Simulation Results σgbw (khz) FF-NR FF-NR OBCF-FF OBCF-FF NR VF-FF VF-FF NR VF-FF OBNR VF-CF FF σgbw (khz) 147, 144,4 17, , ,3 89, σpm (deg) 4,5 4 3,5 3,5 1,5 1 0,5 0 FF-NR FF-NR OBCF-FF OBCF-FF NR VF-FF VF-FF NR VF-FF OBNR VF-CF FF σpm (deg) 1,6 1,9,68 4,06,8,4 1,8 1,4 Standard deviations of the gain-bandwidth distributions (N=1000) Standard deviations of the phase margin distributions (N=1000)

12 Future Perspectives Frequency compensation of three-stage feedback amplifiers employing reversed nested Miller compensation () for low-power contests has been discussed. Some new original frequency compensation techniques for RHP-zero cancellation of integrated three-stage OTA topologies have been investigated in detail. Analytic figure of merit evaluation has been carried out for each amplifier topology. Some of the most proficient amplifier topologies are currently being fabricated using a 0.35-µm process, and measurements will be executed in the near future. -VF-CF-FF Microphotograph of the layout (AMI 0.35 µm) -VF-CF-FF Microphotograph of the chip (AMI 0.35 µm)

13 Sigma-Delta (Σ ) Modulation Theory It joins Oversampling and Noise Shaping techniques in order to increase the SNR of a basic low-resolution converter (1 bit) to obtain and equivalent converter with a high number of bits (until 0 bits) at a medium frequency. It employs Digital Filtering techniques implemented through high-density technological processes, therefore providing low costs and high reliability. S a (t) S q [nt s ] A/D N q T s S a (t) S a [nt s ] S q [nt s ] + N q Correspondence between the quantizator bits and the converter (S/N) max : every additional bit in resolution entails a (S/N) increase of nearly 6dB. S N max ( db ) max S = 10 log10 = n N ( db)

14 Over-Sampling Technique Increasing the bandwidth of the sampled signal f s / reduces the noise power spectral density in the band of the input signal f x, since the noise quantization power remains constant all over the frequency range and only depends on the quantizer resolution. S Q in-band noise S Q {(f Ny /)} P Q = 0 f s / S df Q Over-sampling ratio M = K S Q {M(f Ny /)} f x f s /=f Ny / f s /=M(f Ny /) f Every doubling of the sampling frequency entails a 3-dB noise reduction in the signal band and thus produces an increment of 0.5 bits in the equivalent number of bits of the converter. S N ( ) S = + 3K N K s Ny s Ny f = f / f = f / ( db ) ( db ) ( db )

15 Noise-Shaping Technique It is based on the idea of processing the input signal and the quantization noise in two different ways. This type of modulation exploits the feedback configuration to realize a low-pass filter for the input signal and a high-pass filter for the quantization noise. N(z) S(z) - + H(z) + Y(z) H ( z) 1 Y ( z) = S( z) + N ( z) 1 + H ( z) 1 + H ( z) Every doubling of the sampling frequency entails a 9-dB noise reduction in the signal band and thus produces an increment of 1.5 bits in the equivalent number of bits of the converter. S N max ( db ) max S = 10 log10 = n+ 3K db N ( )

16 Higher-order Σ Modulators Higher-order modulators are realized with L-bit quantizers, entailing an extra increment of 6dB for every doubling of the sampling frequency. S N max ( db) ( ) ( 1) ( ) = C n + K L + db 14 S Qo (f)/s Qi (f) = L sin L (π f/f s ) 1 10 L=1 L= L=3 L=4 L=5 S Qo (f)/s Qi (f) f/f s

17 First-order Switched-Capacitor Σ Converter A new particular feedback configuration adopting 10 combined switches has been profitably exploited to implement a first-order modulator with a resolution of 10 bits. I/O Transfer Functions 3 C I z Vout ( z ) C F = Vin ( z ) 1 VREF C 1 z 1 VDD C F 3 V j T DD C ω I e Vout ( jω ) VREF C = Vin ( jω ) VDD CF 1+ jωt 1 V REF C Discrete-time Miller integrator 1-bit quantizer Edge-triggered D flip-flop T = 5.1M Hz K M = = 51 1 C I z 1 C 1 z Vout z Vin z N z C VREF C VREF z + 1 z 1 C F V + DD C F V DD F ( ) = ( ) + ( ) C I = 0.5 pf C F = 1 pf C1 = C = 1.5 pf

18 Σ Transient and Frequency Responses transient response to a 1V 10kHz-ac signal 10kHz-resolution frequency response Frequency band of interest = 0kHz Fundamental frequency Zero-crossing Shaped noise S a f a f a f... 60dB N = > a a a db 1 db db 3 db S N max ( db) ( ) = n db n = 10 bits

19 Clock generator D flip-flop Σ Converter Layout metal-1/metal- vias Miller integrator 1-bit comparator Digital blocks Common-centroid capacitors Analog blocks

20 Integrated Circuit Fabrication Σ converter layout Voltage Regulators Σ converter IC Voltage Regulators IC The complete layout was sent to the Austria Microsystems (AMS) silicon foundry, and the relevant integrated circuit has been recently fabricated using a 0.35-µm process. Measurements on the chip package are being executed. Integrated Circuit and Chip Package

21 Scientific Publications (1/) International Journals D. Marano, G. Palumbo, S. Pennisi, A New Compact Low-Power Rail-to-Rail Class-B Buffer for LCD Applications, IEEE Journal of Display Technology, accepted for publication. D. Marano, G. Palumbo, S. Pennisi, Step-Response Optimization Techniques for Low-Power Three-Stage Operational Amplifiers for High Capacitive Load Applications, Analog Integrated Circuits and Signal Processing, accepted for publication. D. Marano, G. Palumbo, S. Pennisi, Advanced RNM Compensation Topology with Active Buffers for High-Load Three-Stage OTAs, Microelectronics Journal, accepted for publication. D. Marano, G. Palumbo, S. Pennisi, Improved Low-Power High-Speed Buffer Amplifier with Slew-Rate Enhancement for LCD Applications, Journal of Circuits, Systems and Computers, accepted for publication. D. Marano, G. Palumbo, S. Pennisi, Improved Power-Efficient Technique with Voltage Buffer and Nulling Resistors for Low-Power High-Load Three-Stage Amplifiers, Journal of Circuits, Systems and Computers, accepted for publication. A. D. Grasso, D. Marano, G. Palumbo, S. Pennisi, Analytical Comparison of Reversed Nested Miller Frequency Compensation Techniques, International Journal of Circuit Theory and Applications, in press. A. D. Grasso, D. Marano, G. Palumbo, S. Pennisi, Improved Reversed Nested Miller Frequency Compensation Technique with Voltage Buffer and Nulling Resistor, IEEE Transactions on Circuits and Systems II, vol. 54, no. 5, pp , May 007.

22 Scientific Publications (/) International Conferences D. Marano, G. Palumbo, S. Pennisi, Self-Biased Dual-Path Push-Pull Output Buffer Amplifier Topologies for LCD Driver Applications, Proceeding ISCAS 10, Paris, France, accepted for publication. D. Marano, G. Palumbo, S. Pennisi, A Novel Low-Power High-Speed Rail-to-Rail Class-B Buffer Amplifier Topology for LCD Output Drivers, Proceeding ICECS 09, Hammamet, Tunisia, accepted for publication. D. Marano, G. Palumbo, S. Pennisi, A High-Speed Low-Power Output Buffer Amplifier for Large-Size LCD Applications, Proceeding ICECS 09, Hammamet, Tunisia, accepted for publication. D. Marano, G. Palumbo, S. Pennisi, An Efficient RNM Compensation Topology with Voltage Buffer and Nulling Resistors for Large-Capacitive-Load Three-Stage OTAs, Proceeding ICECS 09, Hammamet, Tunisia, accepted for publication. D. Marano, G. Palumbo, S. Pennisi, A New Advanced Technique with Dual-Active Current and Voltage Buffers for Low-Power High-Load Three-Stage Amplifiers, Proceeding IEEE ISCAS 09, Tapei, Taiwan, May 009, in press. D. Marano, G. Palumbo, S. Pennisi, Step-Response Optimization Techniques for Low-Power Three-Stage Operational Amplifiers Driving Large Capacitive Loads, Proceeding IEEE ISCAS 09, Tapei, Taiwan, May 009, in press. A. D. Grasso, D. Marano, G. Palumbo, S. Pennisi, Reversed Double Pole Zero Cancellation Frequency Compensation Technique for Three-Stage Amplifiers, Proceeding IEEE PRIME 06, pp , Otranto, Italy, June 006.