BSIM4.6.0 MOSFET Model

Transcription

1 BSIM4.6.0 MOSFET Model - User s Manual Mohan. Dunga, Xuemei (Jane) Xi, Jin He, Weidong Liu, Kanyu M. Cao, Xiaodong Jin, Jeff J. Ou, Mansun Chan, Ali M. Niknejad, Chenming Hu Department of Electrical Engineering and Computer Sciences University of California, Berkeley, CA 9470 Copyright 006 The Regents of the University of California All Rights Reserved

2 Developers: BSIM4.6.0 Developers: Professor Chenming Hu (project director), UC Berkeley Professor Ali M. Niknejad(project director), UC Berkeley Mohan. Dunga, UC Berkeley Developers of BSIM4 Previous ersions: Dr. Weidong Liu, Synopsys Dr. Xiaodong Jin, Marvell Dr. Kanyu (Mark) Cao, UC Berkeley Dr. Jeff J. Ou, Intel Dr. Jin He, UC Berkeley Dr. Xuemei (Jane) Xi, UC Berkeley Mohan. Dunga, UC Berkeley Professor Chenming Hu, UC Berkeley Web Sites: BSIM4 web site with BSIM source code and documents: Compact Model Council: Technical Support: Mohan. Dunga:

3 Acknowledgement: The development of BSIM4.6.0 benefited from the input of many BSIM users, especially the Compact Model Council (CMC) member companies. The developers would like to thank Keith Green, Tom rotsos, Suhail Murtaza, David Zweidinger, Britt Brooks and Doug Weiser at TI, Joe Watts and Richard Q Williams at IBM, Yu-Tai Chia, Ke-Wei Su, Chung- Kai Chung, and Y-M Sheu at TSMC, Rainer Thoma, Ivan To, Young-Bog Park and Colin McAndrew at Motorola, Paul Humphries, Geoffrey J. Coram and Andre Martinez at Analog Devices, Andre Juge and Gilles Gouget at STmicroelectronics, Mishel Matloubian at Mindspeed, Judy An at AMD, Bernd Lemaitre, Joachim Assenmacher, Laurens Weiss and Peter Klein at Infinion, Ping-Chin Yeh and Dick Dowell at HP, Shiuh-Wuu Lee, Wei-Kai Shih, Paul Packan, Sivakumar P Mudanai and Rafael Rio at Intel, Xiaodong Jin at Marvell, Weidong Liu at Synopsys, Marek Mierzwinski at Tiburon-DA, Jean-Paul MALZAC at Silvaco, Min-Chie Jeng, Ping Chen, Jushan Xie, and Zhihong Liu at Cadence, Mohamed Selim and Ahmed Ramadan at Mentor Graphics, Peter Lee, Kazunori Onozawa at Renesas, Toshiyuki Saito and Shigetaka Kumashiro at NEC, Richard Taylor at NSC, for their valuable assistance in identifying the desirable modifications and testing of the new model. The BSIM project is partially supported by SRC and CMC.

4 Table of Contents Chapter 1: 1.1 Gate Dielectric Model Poly-Silicon Gate Depletion Effective Channel Length and Width 1-5 Effective Oxide Thickness, Channel Length and Channel Width 1-1 Chapter : Threshold oltage Model -1.1 Long-Channel Model With Uniform Doping -1. Non-Uniform ertical Doping -.3 Non-Uniform Lateral Doping: Pocket (Halo) Implant -5.4 Short-Channel and DIBL Effects -6.5 Narrow-Width Effect -9 Chapter 3: Channel Charge and Subthreshold Swing Models Channel Charge Model Subthreshold Swing n 3-5 Chapter 4: Gate Direct Tunneling Current Model Model selectors 4-4. oltage Across Oxide ox Equations for Tunneling Currents 4-3 Chapter 5: Drain Current Model Bulk Charge Effect Unified Mobility Model 5-5.3Asymmetric and Bias-Dependent Source/Drain Resistance Model Drain Current for Triode Region elocity Saturation Saturation oltage dsat Saturation-Region Output Conductance Model Single-Equation Channel Current Model 5-16 BSIM4.6.0 Manual Copyright 006 UC Berkeley 1

5 5.9 New Current Saturation Mechanisms: elocity Overshoot and Source End elocity Limit Model 5-17 Chapter 6: Body Current Models Iii Model IGIDL Model 6- Chapter 7: Capacitance Model General Description Methodology for Intrinsic Capacitance Modeling Charge-Thickness Capacitance Model (CTM) Intrinsic Capacitance Model Equations Fringing/Overlap Capacitance Models 7-19 Chapter 8: High-Speed/RF Modelsm Charge-Deficit Non-Quasi-Static (NQS) Model Gate Electrode Electrode and Intrinsic-Input Resistance (IIR) Model Substrate Resistance Network 8-8 Chapter 9: Noise Modeling Flicker Noise Models Channel Thermal Noise Other Noise Sources Modeled 9-7 Chapter 10: Asymmetric MOS Junction Diode Models Junction Diode I Model Junction Diode C Model 10-6 Chapter 11: Layout-Dependent Parasitics Model Geometry Definition Model Formulation and Options 11-3 Chapter 1: Temperature Dependence Model Temperature Dependence of Threshold oltage 1-1 BSIM4.6.0 Manual Copyright 006 UC Berkeley

6 1.Temperature Dependence of Mobility 1-1.3Temperature Dependence of Saturation elocity Temperature Dependence of LDD Resistance Temperature Dependence of Junction Diode I Temperature Dependence of Junction Diode C Temperature Dependences of Eg and ni 1-1 Chapter 13: Stress Effect Model Stress effect model development Effective SA and SB for irregular LOD 13- Chapter 14: Well Proximity Effect Model Well Proximity effect model 14-1 Chapter 15: Parameter Extraction Methodology Optimization strategy Extraction Strategy Extraction Procedure 15-3 Appendix A: Complete Parameter List A-1 A.1 BSIM4.0.0 Model Selectors/Controllers A-1 A. Process Parameters A-3 A.3 Basic Model Parameters A-5 A.4 Parameters for Asymmetric and Bias-Dependent Rds Model A-10 A.5 Impact Ionization Current Model Parameters A-11 A.6 Gate-Induced Drain Leakage Model Parameters A-1 A.7 Gate Dielectric Tunneling Current Model Parameters A-13 A.8 Charge and Capacitance Model Parameters A-16 A.9 High-Speed/RF Model Parameters A-18 A.10 Flicker and Thermal Noise Model Parameters A-0 A.11 Layout-Dependent Parasitics Model Parameters A- A.1 Asymmetric Source/Drain Junction Diode Model Parameters A-4 A.13 Temperature Dependence Parameters A-9 A.14 Stress Effect Model Parameters A-31 BSIM4.6.0 Manual Copyright 006 UC Berkeley 3

7 A.15 Well-Proximity Effect Model Parameters A-33 A.16 dw and dl Parameters A-35 A.17 Range Parameters for Model Application A-35 A.18 Notes 1-8 A-35 Appendix B: Core Parameter List for General Parameter Extraction B-1 Appendix C: References C-1 BSIM4.6.0 Manual Copyright 006 UC Berkeley 4

8 Chapter 1: Effective Oxide Thickness, Channel Length and Channel Width BSIM4, as the extension of BSIM3 model, addresses the MOSFET physical effects into sub-100nm regime. The continuous scaling of minimum feature size brought challenges to compact modeling in two ways: One is that to push the barriers in making transistors with shorter gate length, advanced process technologies are used such as non-uniform substrate doping. The second is its opportunities to RF applications. To meet these challenges, BSIM4 has the following major improvements and additions over BSIM3v3: (1) an accurate new model of the intrinsic input resistance for both RF, high-frequency analog and high-speed digital applications; () flexible substrate resistance network for RF modeling; (3) a new accurate channel thermal noise model and a noise partition model for the induced gate noise; (4) a non-quasi-static (NQS) model that is consistent with the Rg-based RF model and a consistent AC model that accounts for the NQS effect in both transconductances and capacitances. (5) an accurate gate direct tunneling model for multiple layer gate dielectrics; (6) a comprehensive and versatile geometrydependent parasitics model for various source/drain connections and multi-finger devices; (7) improved model for steep vertical retrograde doping profiles; (8) better model for pocket-implanted devices in th, bulk charge effect model, and Rout; (9) asymmetrical and bias-dependent source/drain resistance, either internal or external to the intrinsic MOSFET at the user's discretion; (10) acceptance of either the electrical or physical gate oxide thickness as the model input at the user's BSIM4.6.0 Manual Copyright 006 UC Berkeley 1-1

9 Gate Dielectric Model choice in a physically accurate maner; (11) the quantum mechanical charge-layerthickness model for both I and C; (1) a more accurate mobility model for predictive modeling; (13) a gate-induced drain/source leakage (GIDL/GISL) current model, available in BSIM for the first time; (14) an improved unified flicker (1/f) noise model, which is smooth over all bias regions and considers the bulk charge effect; (15) different diode I and C charatistics for source and drain junctions; (16) junction diode breakdown with or without current limiting; (17) dielectric constant of the gate dielectric as a model parameter; (18) A new scalable stress effect model for process induced stress effect; device performance becoming thus a function of the active area geometry and the location of the device in the active area; (19) A unified current-saturation model that includes all mechanisms of current saturation- velocity saturation, velocity overshoot and source end velocity limit; (0) A new temperature model format that allows convenient prediction of temperature effects on saturation velocity, mobility, and S/D resistances. 1.1Gate Dielectric Model As the gate oxide thickness is vigorously scaled down, the finite charge-layer thickness can not be ignored [1]. BSIM4 models this effect in both I and C. For this purpose, BSM4 accepts two of the following three as the model inputs: the electrical gate oxide thickness TOXE 1, the physical gate oxide thickness TOXP, and their difference DTOX = TOXE - TOXP. Based on these parameters, the effect of effective gate oxide capacitance C oxeff on I and C is modeled []. 1. Capital and italic alphanumericals in this manual are model parameters. 1- BSIM4.6.0 Manual Copyright 006 UC Berkeley

10 Gate Dielectric Model High-k gate dielectric can be modeled as SiO (relative permittivity: 3.9) with an equivalent SiO thickness. For example, 3nm gate dielectric with a dielectric constant of 7.8 would have an equivalent oxide thickness of 1.5nm. BSIM4 also allows the user to specify a gate dielectric constant (EPSROX) different from 3.9 (SiO ) as an alternative approach to modeling high-k dielectrics. Figure 1-1 illustrates the algorithm and options for specifying the gate dielectric thickness and calculation of the gate dielectric capacitance for BSIM4 model evaluation. TOXE and TOXP both given? No TOXE given? No TOXP given? No Yes Yes Yes TOXE TOXE TOXP TOXP TOXE TOXE TOXP TOXE - DTOX TOXE TOXP + DTOX TOXP TOXP Default case EPSROX ε C 0 oxe =, C TOXE oxe is used to calculate th, subthreshold swing, gsteff, A bulk, mobiliy, dsat, K 1ox, K ox, capmod = 0 and 1, etc EPSROX ε C 0 oxp = TOXP, C oxp is used to calculate C oxeff for drain current and capmod = through the charge-layer thickness model: cm X DC = 0.7 gsteff + 4( TH 0 FB Φ s ) 1 + TOXP If DTOX is not given, its default value will be used. Figure 1-1. Algorithm for BSIM4 gate dielectric model. BSIM4.6.0 Manual Copyright 006 UC Berkeley 1-3

11 Poly-Silicon Gate Depletion 1. Poly-Silicon Gate Depletion When a gate voltage is applied to the poly-silicon gate, e.g. NMOS with n + polysilicon gate, a thin depletion layer will be formed at the interface between the polysilicon and the gate oxide. Although this depletion layer is very thin due to the high doping concentration of the poly-silicon gate, its effect cannot be ignored since the gate oxide thickness is small. Figure 1- shows an NMOSFET with a depletion region in the n + poly-silicon gate. The doping concentration in the n + poly-silicon gate is NGATE and the doping concentration in the substrate is NSUB. The depletion width in the poly gate is X p. The depletion width in the substrate is X d. The positive charge near the interface of the poly-silicon gate and the gate oxide is distributed over a finite depletion region with thickness X p. In the presence of the depletion region, the voltage drop across the gate oxide and the substrate will be reduced, because part of the gate voltage will be dropped across the depletion region in the gate. That means the effective gate voltage will be reduced. BSIM4.6.0 Manual Copyright 006 UC Berkeley 1-4

12 Poly-Silicon Gate Depletion NGATE Figure 1-. Charge distribution in a MOSFET with the poly gate depletion effect. The device is in the strong inversion region. The effective gate voltage can be calculated in the following manner. Assume the doping concentration in the poly gate is uniform. The voltage drop in the poly gate poly can be calculated as (1..1) poly = 0.5X poly E poly qngate X = ε si poly where E poly is the maximum electrical field in the poly gate. The boundary condition at the interface of poly gate and the gate oxide is BSIM4.6.0 Manual Copyright 006 UC Berkeley 1-5

13 Poly-Silicon Gate Depletion (1..) EPSROX E ox = ε E = qε si poly si NGATE poly where E ox is the electric field in the gate oxide. The gate voltage satisfies (1..3) Φ = + gs FB s poly ox where ox is the voltage drop across the gate oxide and satisfies ox = E ox TOXE. From (1..1) and (1..), we can obtain (1..4) ( Φ ) = 0 a gs FB s poly poly where (1..5) EPSROX a = qε NGATE TOXE si By solving (1..4), we get the effective gate voltage gse which is equal to (1..6) gse ( FB Φ ) qε EPSROX singate TOXE gs s = FB + Φ s EPSROX qε NGATE TOXE si BSIM4.6.0 Manual Copyright 006 UC Berkeley 1-6

14 Effective Channel Length and Width 1.3 Effective Channel Length and Width The effective channel length and width used in the drain current model are given below where XL and XW are parameters to account the channel length/width offset due to mask/etch effect Leff = Ldrawn+ XL dl (1.3.1) Wdrawn Weff = + XW dw NF (1.3.a) W eff W ' = NF drawn + XW dw' (1.3.b) The difference between (1.3.a) and (1.3.b) is that the former includes bias dependencies. NF is the number of device fingers. dw and dl are modeled by dw = dw ' + DWG WL dw ' = WINT + WLN L gsteff WW + W + DWB WWN (1.3.3) ( Φ Φ ) s WWL + WLN L W WWN bseff s LL LW LWL dl + L W L W = LINT + + LLN LWN LLN LWN (1.3.4) BSIM4.6.0 Manual Copyright 006 UC Berkeley 1-7

15 Effective Channel Length and Width WINT represents the traditional manner from which "delta W" is extracted (from the intercept of straight lines on a 1/R ds ~W drawn plot). The parameters DWG and DWB are used to account for the contribution of both gate and substrate bias effects. For dl, LINT represents the traditional manner from which "delta L" is extracted from the intercept of lines on a R ds ~L drawn plot). The remaining terms in dw and dl are provided for the convenience of the user. They are meant to allow the user to model each parameter as a function of W drawn, L drawn and their product term. By default, the above geometrical dependencies for dw and dl are turned off. MOSFET capacitances can be divided into intrinsic and extrinsic components. The intrinsic capacitance is associated with the region between the metallurgical source and drain junction, which is defined by the effective length (L active ) and width (W active ) when the gate to source/drain regions are under flat-band condition. L active and W active are defined as (1.3.5) Lactive= Ldrawn+ XL dl Wdrawn Wactive= + XW dw NF (1.3.6) LLC LWC LWLC dl = DLC LLN LWN LLN L W L W LWN (1.3.7) BSIM4.6.0 Manual Copyright 006 UC Berkeley 1-8

16 Effective Channel Length and Width WLC WWC WWLC dw = DWC WLN WWN WLN L W L W WWN (1.3.8) The meanings of DWC and DLC are different from those of WINT and LINT in the I- model. Unlike the case of I-, we assume that these dimensions are biasdependent. The parameter δl eff is equal to the source/drain to gate overlap length plus the difference between drawn and actual POLY CD due to processing (gate patterning, etching and oxidation) on one side. The effective channel length L eff for the I- model does not necessarily carry a physical meaning. It is just a parameter used in the I- formulation. This L eff is therefore very sensitive to the I- equations and also to the conduction characteristics of the LDD region relative to the channel region. A device with a large L eff and a small parasitic resistance can have a similar current drive as another with a smaller L eff but larger R ds. The L active parameter extracted from capacitance is a closer representation of the metallurgical junction length (physical length). Due to the graded source/drain junction profile, the source to drain length can have a very strong bias dependence. We therefore define L active to be that measured at flat-band voltage between gate to source/drain. If DWC, DLC and the length/width dependence parameters (LLC, LWC, LWLC, WLC, WWC and WWLC) are not specified in technology files, BSIM4 assumes that the DC bias-independent L eff and W eff will be used for the capacitnace models, and DWC, DLC, LLC, LWC, LWLC, WLC, WWC and WWLC will be set to the values of their DC counterparts. BSIM4.6.0 Manual Copyright 006 UC Berkeley 1-9

17 Effective Channel Length and Width BSIM4 uses the effective source/drain diffusion width W effcj for modeling parasitics, such as source/drain resistance, gate electrode resistance, and gateinduced drain leakage (GIDL) current. W effcj is defined as (1.3.9) Wdrawn WLC WWC WWLC Weffcj + XW- DWJ+ + + WLN WWN WLN NF Ł L W L W = WWN ł Note: Any compact model has its validation limitation, so does BSIM4. BSIM4 is its own valid designation limit which is larger than the warning limit, shown in following table. For users reference, the fatal limitation in BSIM4 is also shown. Parameter name Designed Limitation(m) Warning Limitation(m) Fatal Limitation(m) Leff 1e-8 1e-9 0 LeffC 1e-8 1e-9 0 Weff 1e-7 1e-9 0 WeffC 1e-7 1e-9 0 Toxe 5e-10 1e-10 0 Toxp 5e-10 1e-10 0 Toxm 5e-10 1e-10 0 Table 1-1. BSIM4.6.0 Geometry Limitation BSIM4.6.0 Manual Copyright 006 UC Berkeley 1-10

18 Chapter : Threshold oltage Model.1 Long-Channel Model With Uniform Doping Accurate modeling of threshold voltage th is important for precise description of device electrical characteristics. th for long and wide MOSFETs with uniform substrate doping is given by th = FB + Φ + γ Φ = TH 0 + γ s s bs (.1.1) ( Φ Φ ) s bs s where FB is the flat band voltage, TH0 is the threshold voltage of the long channel device at zero substrate bias, and γ is the body bias coefficient given by (.1.) γ = qε si C N oxe substrate where N substrate is the uniform substrate doping concentration. Equation (.1.1) assumes that the channel doping is constant and the channel length and width are large enough. Modifications have to be made when the substrate doping concentration is not constant and/or when the channel is short, or narrow. BSIM4.6.0 Manual Copyright 006 UC Berkeley -1

19 Non-Uniform ertical Doping Consider process variation, a new instance parameter DELTO is added to TH0 as: (a) If TH0 is given, (.1.3) TH 0 = TH 0 + DELTO (a) If TH0 isn t given, (.1.4) FB TH = FB + DELTO 0 = FB + F s + g F s. Non-Uniform ertical Doping The substrate doping profile is not uniform in the vertical direction and therefore γ in (.1.) is a function of both the depth from the interface and the substrate bias. If N substrate is defined to be the doping concentration (NDEP) at X dep0 (the depletion edge at bs = 0), th for non-uniform vertical doping is (..1) th qd 0 qd1 = th, NDEP + + K1NDEP ϕ s bs ϕ s bs Coxe ε si where K1 NDEP is the body-bias coefficient for N substrate = NDEP, - BSIM4.6.0 Manual Copyright 006 UC Berkeley

20 Non-Uniform ertical Doping th, NDEP = TH 0 + K1 NDEP ( ϕ ϕ ) s bs s (..) with a definition of (..3) ϕ s k BT NDEP = ln q ni where n i is the intrinsic carrier concentration in the channel region. The zero-th and 1st moments of the vertical doping profile in (..1) are given by (..4) and (..5), respectively, as (..4) D 0 = D 00 + D 01 = X dep0 0 X dep ( N( x) NDEP) dx + ( N( x) NDEP) X dep0 dx D = D D 11 = X dep0 0 (..5) X dep ( N( x) NDEP) xdx + ( N( x) NDEP) X dep0 xdx By assuming the doping profile is a steep retrograde, it can be shown that D 01 is approximately equal to -C 01 bs and that D 10 dominates D 11 ; C 01 represents the profile of the retrograde. Combining (..1) through (..5), we obtain (..6) th ( Φ s bs Φ s ) K bs = TH 0 + K1 BSIM4.6.0 Manual Copyright 006 UC Berkeley -3

21 Non-Uniform ertical Doping where K = qc 01 / C oxe, and the surface potential is defined as (..7) Φ k T NDEP B = ln q n i s + PHIN where PHIN = qd 10 ε si TH0, K1, K, and PHIN are implemented as model parameters for model flexibility. Appendix A lists the model selectors and parameters. Detail information on the doping profile is often available for predictive modeling. Like BSIM3v3, BSIM4 allows K1 and K to be calculated based on such details as NSUB, XT, BX, BM, etc. ( with the same meanings as in BSIM3v3): (..8) K 1 = γ K Φ s BM K = ( γ 1 γ )( Φ s BX Φ s ) Φ ( Φ BM Φ ) + BM s s s (..9) where γ 1 and γ are the body bias coefficients when the substrate doping concentration are equal to NDEP and NSUB, respectively: -4 BSIM4.6.0 Manual Copyright 006 UC Berkeley

22 Non-Uniform Lateral Doping: Pocket (Halo) Implant (..10) γ 1 = qε si C NDEP oxe (..11) γ = qε si C NSUB oxe BX is the body bias when the depletion width is equal to XT, and is determined by qndep XT ε si = Φ s (..1) BX.3 Non-Uniform Lateral Doping: Pocket (Halo) Implant In this case, the doping concentration near the source/drain junctions is higher than that in the middle of the channel. Therefore, as channel length becomes shorter, a th roll-up will usually result since the effective channel doping concentration gets higher, which changes the body bias effect as well. To consider these effects, th is written as BSIM4.6.0 Manual Copyright 006 UC Berkeley -5

23 Non-Uniform Lateral Doping: Pocket (Halo) Implant th = TH0 + K1 ( Φ Φ ) LPE K Φ L eff s bs s s eff (.3.1) LPEB 1+ K bs L In addition, pocket implant can cause significant drain-induced threshold shift (DITS) in long-channel devices [3]: (.3.) ds / vt ( 1 e ) L ( ) ( ) eff = th DITS nvt ln DTP1 ds Leff + DTP0 1+ e For ds of interest, the above equation is simplified and implemented as for tempmod = 1: (.3.3a) D Leff th( DITS) = -nvt ln Ł L eff DTP0 ds DTP ( 1 e ) ł for tempmod = : (.3.3b) ( DITS ) ln L eff th = nvt 1 eff + DTP0 L DTP ( + ) ds 1 e -6 BSIM4.6.0 Manual Copyright 006 UC Berkeley

24 Short-Channel and DIBL Effects Note: when tempmod =, drain-induced threshold voltage shift (DITS) due to pocket implant has no temperature dependence, so nominal temperature (TNOM) is used as equation(.3.4). when tempmod=0 or 1, equation(.3.3) is used. (.3.4) Leff Dth( DITS) = -nvtnom ln - 1 ds Ł Leff + DTP0 + DTP ( 1 e ) ł.4 Short-Channel and DIBL Effects As channel length becomes shorter, th shows a greater dependence on channel length (SCE: short-channel effect) and drain bias (DIBL: draininduced barrier lowering). th dependence on the body bias becomes weaker as channel length becomes shorter, because the body bias has weaker control of the depletion region. Based on the quasi D solution of the Poisson equation, th change due to SCE and DIBL is modeled [4] th [ ] ( SCE, DIBL) = θ ( L ) ( Φ ) + th eff bi s ds (.4.1) where bi, known as the built-in voltage of the source/drain junctions, is given by (.4.) bi k BT NDEP NSD ln q ni = BSIM4.6.0 Manual Copyright 006 UC Berkeley -7

25 Short-Channel and DIBL Effects where NSD is the doping concentration of source/drain diffusions. The short-channel effect coefficient θ th (L eff ) in (.4.1) has a strong dependence on the channel length given by ( ) θ th L eff 0.5 = Leff cosh( ) 1 l t (.4.3) l t is referred to as the characteristic length and is given by (.4.4) l t = ε si TOXE X EPSROX η dep with the depletion width X dep equal to X dep = ( Φ ) ε si s qndep bs (.4.5) X dep is larger near the drain due to the drain voltage. X dep / η represents the average depletion width along the channel. Note that in BSIM3v3 and [4], θ th (L eff ) is approximated with the form of (.4.6) θ th L L eff eff ( L ) + eff = exp exp lt lt -8 BSIM4.6.0 Manual Copyright 006 UC Berkeley

26 Short-Channel and DIBL Effects which results in a phantom second th roll-up when L eff becomes very small (e.g. L eff < LMIN). In BSIM4, the function form of (.4.3) is implemented with no approximation. To increase the model flexibility for different technologies, several parameters such as DT0, DT1, DT, DSUB, ETA0, and ETAB are introduced, and SCE and DIBL are modeled separately. To model SCE, we use θ th ( SCE) 0.5 DT0 = cosh Leff ( DT1 ) 1 lt (.4.7) th ( SCE) = θ ( SCE) ( Φ ) th bi s (.4.8) with l t changed to (.4.9) l t ε si TOXE X dep = EPSROX ( 1+ DT ) bs To model DIBL, we use θ th ( DIBL) 0.5 = Leff cosh( DSUB ) 1 lt 0 (.4.10) BSIM4.6.0 Manual Copyright 006 UC Berkeley -9

27 Narrow-Width Effect th ( DIBL) = θ th( DIBL) ( ETA + ETAB bs ) ds 0 (.4.11) and l t0 is calculated by (.4.1) l t0 = ε si TOXE X EPSROX dep0 with (.4.13) X dep0 = ε siφ s qndep DT1 is basically equal to 1/(η) 1/. DT and ETAB account for substrate bias effects on SCE and DIBL, respectively..5 Narrow-Width Effect The actual depletion region in the channel is always larger than what is usually assumed under the one-dimensional analysis due to the existence of fringing fields. This effect becomes very substantial as the channel width decreases and the depletion region underneath the fringing field becomes comparable to the "classical" depletion layer formed from the vertical field. The net result is an increase in th. This increase can be modeled as -10 BSIM4.6.0 Manual Copyright 006 UC Berkeley

28 Narrow-Width Effect (.5.1) πqndep X C oxe W dep,max eff = 3π TOXE W eff Φ s This formulation includes but is not limited to the inverse of channel width due to the fact that the overall narrow width effect is dependent on process (i.e. isolation technology). th change is given by (.5.) th TOXE W ' + W 0 ( Narrow width1) = ( K3 + K3B bs ) Φ s eff In addition, we must consider the narrow width effect for small channel lengths. To do this we introduce the following (.5.3) th ( Narrow width ) DT0W LeffWeff ( DT1W ) = ' cosh ltw 1 ( Φ ) bi s with l tw given by (.5.4) l tw ε si TOXE X dep = EPSROX ( 1+ DT W ) bs The complete th model implemented in SPICE is (.5.5) BSIM4.6.0 Manual Copyright 006 UC Berkeley -11

29 Narrow-Width Effect th = TH0 + + K 1ox 0. 5 cosh DSUB ( K Φ K1 Φ ) 1ox LPE L eff DT0W 0. 5 coshdt W ( K3+ K3B ) + LeffWeff ' Leff ( 1 ) 1 coshdt ( 1 ) Leff ( ) lt 0 s 1 ltw bseff Φ s + ( ETA0 + ETAB ) s bseff LPEB 1+ K L bseff DT0 lt ds eff TOXE Φ W ' + W0 eff 1 ( Φ ) bi ox nv t.ln L s eff bseff s L ( ) eff DTP1 DS + DTP0. 1+ e where TOXE dependence is introduced in model parameters K1 and K to improve the scalibility of th model over TOXE as K1 ox = K1 TOXE TOXM (.5.6) and K ox = K TOXE TOXM (.5.7) Note that all bs terms are substituted with a bseff expression as shown in (.5.8). This is needed in order to set a low bound for the body bias during simulations since unreasonable values can occur during SPICE iterations if this expression is not introduced. BSIM4.6.0 Manual Copyright 006 UC Berkeley -1

30 Narrow-Width Effect (.5.8) ( ) + ( ) bs bc δ1 bs bc δ δ bseff = bc 1 bc where δ 1 = 0.001, and bc is the maximum allowable bs and found from d th /d bs = 0 to be (.5.9) bc K1 = 0.9 Φ s 4K For positive bs, there is need to set an upper bound for the body bias as: (.5.10) ' ( 0.95Φ δ ) + 4δ.0. Φ ' bseff 0.95Φ s Φ s bseff δ1 + s bseff = s BSIM4.6.0 Manual Copyright 006 UC Berkeley -13

31 Chapter 3: Channel Charge and Subthreshold Swing Models 3.1 Channel Charge Model The channel charge density in subthreshold for zero ds is written as (3.1.1) Q chsubs0 = qndepε Φ s si v t exp gse th off ' nvt where OFFL off ' = OFF + L eff (3.1.1a) OFFL is used to model the length dependence of off on non-uniform channel doping profiles. In strong inversion region, the density is expressed by Q chs0 = C oxe ( ) gse th (3.1.) A unified charge density model considering the charge layer thickness effect is derived for both subthreshold and inversion regions as BSIM4.6.0 Manual Copyright 006 UC Berkeley 3-1

32 Channel Charge Model (3.1.3) Q ch0 = C oxeff gsteff where C oxeff is modeled by (3.1.4) C oxeff C = C oxe oxe C + C cen cen with C cen = ε X si DC and X DC is given as (3.1.5) X DC = 1+ gsteff ( TH 0 FB Φ ) TOXP m s 0.7 In the above equations, gsteff, the effective ( gse - th ) used to describe the channel charge densities from subthreshold to strong inversion, is modeled by gsteff = m + nc oxe m nvt ln 1 + exp Φ s exp qndepε si ( ) gse nv t th ( 1 m )( ) gse nv t (3.1.6a) th off' where arctan m = ( MIN ) π (3.1.6b) 3- BSIM4.6.0 Manual Copyright 006 UC Berkeley

33 Channel Charge Model MIN is introduced to improve the accuracy of G m, G m /I d and G m /I d in the moderate inversion region. To account for the drain bias effect, The y dependence has to be included in (3.1.3). Consider first the case of strong inversion Q chs ( ) ( y) = C A ( y) oxeff gse th bulk F (3.1.7) F (y) stands for the quasi-fermi potential at any given point y along the channel with respect to the source. (3.1.7) can also be written as Q chs ( y) Q + Q ( y) = chs0 chs (3.1.8) The term Q chs (y) = -C oxeff A bulk F (y) is the incremental charge density introduced by the drain voltage at y. In subthreshold region, the channel charge density along the channel from source to drain can be written as Q chsubs ( y) A exp = bulk F Qchsubs0 nvt ( y) (3.1.9) Taylor expansion of (3.1.9) yields the following (keeping the first two terms) BSIM4.6.0 Manual Copyright 006 UC Berkeley 3-3

34 Channel Charge Model A Q ( ) chsubs y Qchsubs0 1 = bulk F nvt ( y) (3.1.10) Similarly, (3.1.10) is transformed into Q chsubs ( y) Q + Q ( y) = chsubs0 chsubs (3.1.11) where Q chsubs (y) is the incremental channel charge density induced by the drain voltage in the subthreshold region. It is written as ( y) Qchsubs = Qchsubs0 A bulk nv F t ( y) (3.1.1) To obtain a unified expression for the incremental channel charge density Q ch (y) induced by ds, we assume Q ch (y) to be Q ch ( y) Q = Q chs chs ( y) Qchsubs( y) ( y) + Q ( y) chsubs (3.1.13) Substituting Q ch (y) of (3.1.8) and (3.1.1) into (3.1.13), we obtain Q ch ( y) F = ( y) b Q ch0 (3.1.14) 3-4 BSIM4.6.0 Manual Copyright 006 UC Berkeley

35 Subthreshold Swing n where b = ( gsteff + nv t ) / A bulk. In the model implementation, n of b is replaced by a typical constant value of. The expression for b now becomes b = + vt Abulk gsteff (3.1.15) A unified expression for Q ch (y) from subthreshold to strong inversion regions is ( ) F Qch y Coxeff gsteff 1 = b ( y) (3.1.16) 3. Subthreshold Swing n The drain current equation in the subthreshold region can be expressed as (3..1) I ds 1 exp vt exp = ds gs th I0 nvt off ' where (3..) I 0 W = µ L qε sindep v Φ s t v t is the thermal voltage and equal to k B T/q. off = OFF + OFFL / L eff is the offset voltage, which determines the channel current at gs = 0. In (3..1), n is the BSIM4.6.0 Manual Copyright 006 UC Berkeley 3-5

36 Subthreshold Swing n subthreshold swing parameter. Experimental data shows that the subthreshold swing is a function of channel length and the interface state density. These two mechanisms are modeled by the following n C dep = 1+ NFACTOR + C oxe Cdsc Term + CIT C oxe (3..3) where Cdsc-Term, written as Cdsc Term = ( CDSC + CDSCD + CDSCB ) ds bseff cosh 0.5 Leff ( DT1 ) 1 lt represents the coupling capacitance between drain/source to channel. Parameters CDSC, CDSCD and CDSCB are extracted. Parameter CIT is the capacitance due to interface states. From (3..3), it can be seen that subthreshold swing shares the same exponential dependence on channel length as the DIBL effect. Parameter NFACTOR is close to 1 and introduced to compensate for errors in the depletion width capacitance calculation. 3-6 BSIM4.6.0 Manual Copyright 006 UC Berkeley

37 Chapter 4: Gate Direct Tunneling Current Model As the gate oxide thickness is scaled down to 3nm and below, gate leakage current due to carrier direct tunneling becomes important. This tunneling happens between the gate and silicon beneath the gate oxide. To reduce the tunneling current, high-k dielectrics are being studied to replace gate oxide. In order to maintain a good interface with substrate, multi-layer dielectric stacks are being proposed. The BSIM4 gate tunneling model has been shown to work for multi-layer gate stacks as well. The tunneling carriers can be either electrons or holes, or both, either from the conduction band or valence band, depending on (the type of the gate and) the bias regime. In BSIM4, the gate tunneling current components include the tunneling current between gate and substrate (Igb), and the current between gate and channel (Igc), which is partitioned between the source and drain terminals by Igc = Igcs + Igcd. BSIM4.6.0 Manual Copyright 006 UC Berkeley 4-1

38 Model selectors The third component happens between gate and source/drain diffusion regions (Igs and Igd). Figure 4-1 shows the schematic gate tunneling current flows. Igs Igd Igcs Igcd Igb Figure 4-1. Shematic gate current components flowing between NMOST terminals in version. 4.1 Model selectors Two global selectors are provided to turn on or off the tunneling components. igcmod = 1, turns on Igc, Igs, and Igd; igbmod = 1 turns on Igb. When the selectors are set to zero, no gate tunneling currents are modeled. When tempmod =, following t (= kt/q) will be replaced by tnom(=ktnom/q) 4. oltage Across Oxide ox The oxide voltage ox is written as ox = oxacc + oxdepinv with 4- BSIM4.6.0 Manual Copyright 006 UC Berkeley

39 Equations for Tunneling Currents (4..1a) oxacc = fbzb FBeff (4..1b) Φ + oxdepinv = K 1 ox s gsteff (4..1) is valid and continuous from accumulation through depletion to inversion. fbzb is the flat-band voltage calculated from zero-bias th by (4..) fbzb = Φ K1 th zerobs andds s Φ s and (4..3) ( ) + ( ) fbzb gb 0.0 fbzb gb FBeff fbzb = fbzb 4.3 Equations for Tunneling Currents Note: when tempmod =, nominal temperature(tnom) is used to replace the operating temperature in following gate tunneling current equations. When tempmod=0, or 1, operating temperature is still used. BSIM4.6.0 Manual Copyright 006 UC Berkeley 4-3

40 Equations for Tunneling Currents Gate-to-Substrate Current (Igb = Igbacc + Igbinv) Igbacc, determined by ECB (Electron tunneling from Conduction Band), is significant in accumulation and given by (4.3.1) Igbacc = W eff exp L eff A T oxratio gb aux [ B TOXE( AIGBACC BIGBACC ) ( 1+ CIGBACC )] oxacc oxacc where the physical constants A = 4.973e-7 A/, B = e11 (g/fs ) 0.5, and T oxratio TOXREF = TOXE NTOX 1 TOXE aux = NIGBACC v t gb fbzb log 1+ exp NIGBACC vt Igbinv, determined by EB (Electron tunneling from alence Band), is significant in inversion and given by Igbinv = W eff exp L eff A T oxratio gb aux (4.3.) [ B TOXE( AIGBIN BIGBIN ) ( 1+ CIGBIN )] oxdepinv oxdepinv where A = e-7 A/, B = 9.8e11 (g/f-s ) 0.5, and 4-4 BSIM4.6.0 Manual Copyright 006 UC Berkeley

41 Equations for Tunneling Currents aux = NIGBIN v t log 1+ exp EIGBIN NIGBIN v t oxdepinv 4.3. Gate-to-Channel Current (Igc0) and Gate-to-S/D (Igs and Igd) Igc0, determined by ECB for NMOS and HB (Hole tunneling from alence Band) for PMOS at ds=0, is formulated as Igc0 = W exp eff L eff A T oxratio gse aux (4.3.3) [ B TOXE( AIGC BIGC ) ( 1+ CIGC )] oxdepinv oxdepinv where A = A/ for NMOS and A/ for PMOS, B = e11 (g/f-s ) 0.5 for NMOS and e1 (g/f-s ) 0.5 for PMOS, and for igcmod = 1: aux = NIGC v t gse TH 0 log 1+ exp NIGC vt for igcmod = : aux = NIGC v t gse TH log 1+ exp NIGC vt Igs and Igd -- Igs represents the gate tunneling current between the gate and the source diffusion region, while Igd represents the gate tunneling current between the gate and the drain diffusion region. Igs and Igd are determined by ECB for NMOS and HB for PMOS, respectively. BSIM4.6.0 Manual Copyright 006 UC Berkeley 4-5

42 Equations for Tunneling Currents Igs = W eff exp DLCIG A T oxratioedge gs ' gs (4.3.4) ' ' [ B TOXE POXEDGE ( AIGS BIGS ) ( 1 + CIGS )] gs gs and (4.3.5) Igd = W eff exp DLCIGD A T oxratioedg e gd ' gd ' ' [ B TOXE POXEDGE ( AIGD BIGD ) ( 1+ CIGD )] gd gd where A = A/ for NMOS and A/ for PMOS, B = e11 (g/f-s ) 0.5 for NMOS and e1 (g/f-s ) 0.5 for PMOS, and T oxratioedge TOXREF = TOXE POXEDGE NTOX 1 ( TOXE POXEDGE) ' gs ' gd ( ) = e gs fbsd ( ) = e gd fbsd fbsd is the flat-band voltage between gate and S/D diffusions calculated as If NGATE > 0.0 k BT NGATE = log q NSD fbsd + FBSDOFF Else fbsd = BSIM4.6.0 Manual Copyright 006 UC Berkeley

43 Equations for Tunneling Currents Partition of Igc To consider the drain bias effect, Igc is split into two components, Igcs and Igcd, that is Igc = Igcs + Igcd, and Igcs = Igc PIGCD + exp dseff 0 PIGCD dseff ( PIGCD ) dseff +.0e 4 (4.3.6) e 4 and Igcd = Igc 1 ( PIGCD + 1) exp( PIGCD ) dseff 0 PIGCD dseff +.0e 4 dseff (4.3.7) + 1.0e 4 Where Igc0 is Igc at ds=0. If the model parameter PIGCD is not specified, it is given by (4.3.8) PIGCD = B TOXE 1 gsteff dseff gsteff BSIM4.6.0 Manual Copyright 006 UC Berkeley 4-7

44 Chapter 5: Drain Current Model 5.1 Bulk Charge Effect The depletion width will not be uniform along channel when a non-zero ds is applied. This will cause th to vary along the channel. This effect is called bulk charge effect. BSIM4 uses A bulk to model the bulk charge effect. Several model parameters are introduced to account for the channel length and width dependences and bias effects. A bulk is formulated by A L A0 L + eff dep bulk = 1+ F doping eff XJ X 1 AGS gsteff L eff + L eff XJ X dep (5.1.1) 1 B + KETA Weff + B ' 1 bseff where the second term on the RHS is used to model the effect of non-uniform doping profiles (5.1.) F doping = 1+ LPEB Φ s L eff bseff K 1ox + K ox TOXE K3B Φ W ' + W 0 eff s BSIM4.6.0 Manual Copyright 006 UC Berkeley 5-1

45 Unified Mobility Model Note that A bulk is close to unity if the channel length is small and increases as the channel length increases. 5. Unified Mobility Model A good mobility model is critical to the accuracy of a MOSFET model. The scattering mechanisms responsible for surface mobility basically include phonons, coulombic scattering, and surface roughness. For good quality interfaces, phonon scattering is generally the dominant scattering mechanism at room temperature. In general, mobility depends on many process parameters and bias conditions. For example, mobility depends on the gate oxide thickness, substrate doping concentration, threshold voltage, gate and substrate voltages, etc. [5] proposed an empirical unified formulation based on the concept of an effective field E eff which lumps many process parameters and bias conditions together. E eff is defined by Eeff QB + ( Q = n ) εsi (5..1) The physical meaning of E eff can be interpreted as the average electric field experienced by the carriers in the inversion layer. The unified formulation of mobility is then given by µ eff µ = 0 ν 1 + ( Eeff E0 ) (5..) For an NMOS transistor with n-type poly-silicon gate, (5..1) can be rewritten in a more useful form that explicitly relates E eff to the device parameters 5- BSIM4.6.0 Manual Copyright 006 UC Berkeley

46 Unified Mobility Model (5..3) E eff gs + th 6TOXE BSIM4 provides three different models of the effective mobility. The mobmod = 0 and 1 models are from BSIM3v3..; the new mobmod =, a universal mobility model, is more accurate and suitable for predictive modeling. mobmod = 0 (5..4) µ eff = 1+ ( UA+ UC ) bseff gsteff + TOXE th U0 f ( L eff + + gsteff th UB TOXE ) + UD gsteff th TOXE + th µ eff mobmod = 1 (5..5) = gsteff + 1+ UA TOXE th + + gsteff UB TOXE U0 f ( L th eff ) ( 1+ UC ) bseff + UD gsteff th TOXE + th µ eff = 1+ mobmod = ( UA+ UC ) bseff gsteff + C 0 U0 f ( L ) eff ( THO FB Φ ) TOXE s EU + UD gsteff (5..6) th TOXE + th where the constant C 0 = for NMOS and.5 for PMOS. BSIM4.6.0 Manual Copyright 006 UC Berkeley 5-3

47 Asymmetric and Bias-Dependent Source/Drain Resistance Model f ( L eff Leff ) = 1 UP exp LP (5..7) 5.3 Asymmetric and Bias-Dependent Source/ Drain Resistance Model BSIM4 models source/drain resistances in two components: bias-independent diffusion resistance (sheet resistance) and bias-dependent LDD resistance. Accurate modeling of the bias-dependent LDD resistances is important for deepsubmicron CMOS technologies. In BSIM3 models, the LDD source/drain resistance R ds () is modeled internally through the I- equation and symmetry is assumed for the source and drain sides. BSIM4 keeps this option for the sake of simulation efficiency. In addition, BSIM4 allows the source LDD resistance R s () and the drain LDD resistance R d () to be external and asymmetric (i.e. R s () and R d () can be connected between the external and internal source and drain nodes, respectively; furthermore, R s () does not have to be equal to R d ()). This feature makes accurate RF CMOS simulation possible. The internal R ds () option can be invoked by setting the model selector rdsmod = 0 (internal) and the external one for R s () and R d () by setting rdsmod = 1 (external). R ds ( ) rdsmod = 0 (Internal R ds ()) (5.3.1) RDSWMIN + RDSW = 1 1e6 PRWB ( Φ s bseff Φ s ) + PRWG 1+ gsteff ( W ) WR effcj rdsmod = 1 (External R d () and R s ()) 5-4 BSIM4.6.0 Manual Copyright 006 UC Berkeley

48 Asymmetric and Bias-Dependent Source/Drain Resistance Model R d ( ) RDWMIN + RDW = 1 1e6 PRWB bd + PRWG ( gd fbsd ) 1+ (5.3.) WR [( W ) NF] effcj R s ( ) RSWMIN + RSW = 1 1e6 PRWB bs + PRWG ( gs fbsd ) 1+ (5.3.3) WR [( W ) NF] effcj fbsd is the calculated flat-band voltage between gate and source/drain as given in Section The following figure shows the schematic of source/drain resistance connection for rdsmod = 1. R sdiff +R s () R ddiff +R d () The diffusion source/drain resistance R sdiff and R ddiff models are given in the chapter of layout-dependence models. BSIM4.6.0 Manual Copyright 006 UC Berkeley 5-5

49 Drain Current for Triode Region 5.4 Drain Current for Triode Region R ds ()=0 or rdsmod=1 ( intrinsic case ) Both drift and diffusion currents can be modeled by I ( y) = WQ ( y) ( y) ds ch µ ne df dy ( y) (5.4.1) where u ne (y) can be written as (5.4.) µ ne( y) = µ eff E 1+ E y sat Substituting (5.4.) in (5.4.1), we get I ds ( y) ( y) µ eff d ( y) = F WQch 0 1 E b 1+ E y sat F dy (5.4.3) (5.4.3) is integrated from source to drain to get the expression for linear drain current. This expression is valid from the subthreshold regime to the strong inversion regime 5-6 BSIM4.6.0 Manual Copyright 006 UC Berkeley

50 elocity Saturation (5.4.4) I ds0 = Wµ eff ds Qch0ds 1 b L + ds 1 EsatL 5.4. R ds () > 0 and rdsmod=0 ( Extrinsic case ) The drain current in this case is expressed by I ds Idso = R I 1 + ds dso ds (5.4.5) 5.5 elocity Saturation elocity saturation is modeled by [5] µ eff E v = 1 + E E = SAT sat E < E E E sat sat (5.5.1) where E sat corresponds to the critical electrical field at which the carrier velocity becomes saturated. In order to have a continuous velocity model at E = E sat, E sat must satisfy BSIM4.6.0 Manual Copyright 006 UC Berkeley 5-7

51 Saturation oltage dsat E sat SAT = µ eff (5.5.) 5.6 Saturation oltage dsat Intrinsic case In this case, the LDD source/drain resistances are either zero or non zero but not modeled inside the intrinsic channel region. It is easy to obtain dsat as [7] dsat = EsatL( gsteff + vt) AbulkEsatL + gsteff + vt (5.6.1) 5.6. Extrinsic Case In this case, non-zero LDD source/drain resistance R ds () is modeled internally through the I- equation and symetry is assumed for the source and drain sides. dsat is obtained as [7] b b ac dsat = 4 a (5.6.a) where 5-8 BSIM4.6.0 Manual Copyright 006 UC Berkeley

52 Saturation oltage dsat (5.6.b) 1 a = Abulk WeffSATCoxeRds + Abulk 1 λ b = + 3A ( + v ) gsteff bulk t 1 + A λ bulk E sat ( + ) gsteff vt WeffSATCoxeRds L eff (5.6.c) c = (5.6.d) ( gsteff + vt ) EsatLeff + ( gsteff + vt ) WeffSATCoxeRds λ = A1 gsteff + A (5.6.e) λ is introduced to model the non-saturation effects which are found for PMOSFETs dseff Formulation An effective ds, dseff, is used to ensure a smooth transition near dsat from trode to saturation regions. dseff is formulated as (5.6.3) dseff 1 = dsat dsat ( ) + ( ) + dsat ds δ dsat ds δ 4δ where δ (DELTA) is a model parameter. BSIM4.6.0 Manual Copyright 006 UC Berkeley 5-9

53 Saturation-Region Output Conductance Model 5.7 Saturation-Region Output Conductance Model A typical I- curve and its output resistance are shown in Figure 5-1. Considering only the channel current, the I- curve can be divided into two parts: the linear region in which the current increases quickly with the drain voltage and the saturation region in which the drain current has a weaker dependence on the drain voltage. The first order derivative reveals more detailed information about the physical mechanisms which are involved in the device operation. The output resistance curve can be divided into four regions with distinct R out ~ ds dependences. The first region is the triode (or linear) region in which carrier velocity is not saturated. The output resistance is very small because the drain current has a strong dependence on the drain voltage. The other three regions belong to the saturation region. As will be discussed later, there are several physical mechanisms which affect the output resistance in the saturation region: channel length modulation (CLM), drain-induced barrier lowering (DIBL), and the substrate current induced body effect (SCBE). These mechanisms all affect the output resistance in the saturation range, but each of them dominates in a specific region. It will be shown 5-10 BSIM4.6.0 Manual Copyright 006 UC Berkeley

54 Saturation-Region Output Conductance Model next that CLM dominates in the second region, DIBL in the third region, and SCBE in the fourth region Triode CLM DIBL SCBE 1 I ds (ma) R out (KOhms) ds () 0 Figure 5-1. General behavior of MOSFET output resistance. The channel current is a function of the gate and drain voltage. But the current depends on the drain voltage weakly in the saturation region. In the following, the Early voltage is introduced for the analysis of the output resistance in the saturation region: I ds (, ) = I (, ) gs ds = I dsat dsat gs dsat + (, ) ds 1 ( gs, dsat ) 1 + dd ds dsat I dsat ds A gs d ds d (5.7.1) d BSIM4.6.0 Manual Copyright 006 UC Berkeley 5-11

55 Saturation-Region Output Conductance Model where the Early voltage A is defined as (5.7.) A = I dsat I ds 1 (, ) gs d ds We assume in the following analysis that the contributions to the Early voltage from all mechanisms are independent and can be calculated separately Channel Length Modulation (CLM) If channel length modulation is the only physical mechanism to be taken into account, the Early voltage can be calculated by (5.7.3) ACLM = I dsat I ds 1 (, ) gs L ds L d Based on quasi two-dimensional analysis and through integration, we propose ACLM to be ACLM = C clm ( ) ds dsat (5.7.4) where (5.7.5) C clm 1 = PCLM F 1 + PAG E gsteff sat L eff Rds I 1+ dseff dso L eff + E dsat sat 1 litl BSIM4.6.0 Manual Copyright 006 UC Berkeley 5-1

56 Saturation-Region Output Conductance Model and the F factor to account for the impact of pocket implant technology is 1 F = 1+ FPROUT gsteff L eff + v t (5.7.6) and litl in (5.7.5) is given by (5.7.7) sitoxe XJ litl = ε EPSROX PCLM is introduced into ACLM to compensate for the error caused by XJ since the junction depth XJ can not be determined very accurately Drain-Induced Barrier Lowering (DIBL) The Early voltage ADIBLC due to DIBL is defined as (5.7.8) ADIBL = I dsat I ds 1 (, ) gs th ds th d th has a linear dependence on ds. As channel length decreases, ADIBLC decreases very quickly (5.7.9) gsteff + vt = A ADIBL PAG θ rout bulk dsat ( 1+ PDIBLCB ) bseff Abulkdsat + gsteff + vt EsatLeff gsteff BSIM4.6.0 Manual Copyright 006 UC Berkeley 5-13

57 Saturation-Region Output Conductance Model where θ rout has a similar dependence on the channel length as the DIBL effect in th, but a separate set of parameters are used: θ rout PDIBLC1 DROUT Leff ( ) = cosh lt 0 + PDIBLC (5.7.10) Parameters PDIBLC1, PDIBLC, PDIBLCB and DROUT are introduced to correct the DIBL effect in the strong inversion region. The reason why DT0 is not equal to PDIBLC1 and DT1 is not equal to DROUT is because the gate voltage modulates the DIBL effect. When the threshold voltage is determined, the gate voltage is equal to the threshold voltage. But in the saturation region where the output resistance is modeled, the gate voltage is much larger than the threshold voltage. Drain induced barrier lowering may not be the same at different gate bias. PDIBLC is usually very small. If PDIBLC is put into the threshold voltage model, it will not cause any significant change. However it is an important parameter in ADIBLC for long channel devices, because PDIBLC will be dominant if the channel is long Substrate Current Induced Body Effect (SCBE) When the electrical field near the drain is very large (> 0.1M/cm), some electrons coming from the source (in the case of NMOSFETs) will be energetic (hot) enough to cause impact ionization. This will generate electron-hole pairs when these energetic electrons collide with silicon atoms. The substrate current I sub thus created during impact ionization will BSIM4.6.0 Manual Copyright 006 UC Berkeley 5-14

58 Saturation-Region Output Conductance Model increase exponentially with the drain voltage. A well known I sub model [8] is (5.7.11) I sub = Ai B i I ds i ( ) ds dsat exp ds dsat B litl Parameters A i and B i are determined from measurement. I sub affects the drain current in two ways. The total drain current will change because it is the sum of the channel current as well as the substrate current. The total drain current can now be expressed as follows (5.7.1) I ds = I ds w/ o Isub + I sub = I ds w/ o Isub 1 + Bi Ai ds exp dsat B i litl ( ) ds dsat The Early voltage due to the substrate current ASCBE can therefore be calculated by (5.7.13) ASCBE = B i Bi litl exp Ai ds dsat We can see that ASCBE is a strong function of ds. In addition, we also observe that ASCBE is small only when ds is large. This is why SCBE is important for devices with high drain voltage bias. The channel length and gate oxide dependence of ASCBE comes from dsat and litl. We replace B i with PSCBE and A i /B i with PSCBE1/L eff to get the following expression for ASCBE BSIM4.6.0 Manual Copyright 006 UC Berkeley 5-15

59 Single-Equation Channel Current Model (5.7.14) 1 ASCBE = PSCBE PSCBE1 litl exp Leff ds dsat Drain-Induced Threshold Shift (DITS) by Pocket Implant It has been shown that a long-channel device with pocket implant has a smaller R out than that of uniformly-doped device [3]. The R out degradation factor F is given in (5.7.6). In addition, the pocket implant introduces a potential barrier at the drain end of the channel. This barrier can be lowered by the drain bias even in long-channel devices. The Early voltage due to DITS is modeled by ADITS (5.7.15) [ 1+ ( 1+ PDITSL L ) ( PDITSD )] 1 = F eff exp PDITS ds 5.8 Single-Equation Channel Current Model I The final channel current equation for both linear and saturation regions now becomes (5.8.1) ds I ds0 NF 1 = 1 + RdsIds0 1+ C dseff clm ln A Asat ds 1+ ADIBL dseff ds 1+ ADITS dseff ds 1+ ASCBE dseff where NF is the number of device fingers, and BSIM4.6.0 Manual Copyright 006 UC Berkeley 5-16

60 New Current Saturation Mechanisms: elocity Overshoot and Source End (5.8.) A is written as (5.8.3) = + A Asat ACLM where Asat is Asat E = sat L eff + dsat R + R ds ds vsatc vsatc oxe W oxe eff W A eff bulk gsteff 1+ λ (5.8.4) A [ 1 ] bulk dsat ( + v ) gsteff t Asat is the Early voltage at ds = dsat. Asat is needed to have continuous drain current and output resistance expressions at the transition point between linear and saturation regions. 5.9 New Current Saturation Mechanisms: elocity Overshoot and Source End elocity Limit Model elocity Overshoot In the deep-submicron region, the velocity overshoot has been observed to be a significant effect even though the supply voltage is scaled down BSIM4.6.0 Manual Copyright 006 UC Berkeley 5-17

61 New Current Saturation Mechanisms: elocity Overshoot and Source End according to the channel length. An approximate non-local velocity field expression has proven to provide a good description of this effect (5.9.1) l v = vd ( 1+ E E x me ) = 1+ E / E c l ( 1+ E E x ) This relationship is then substituted into (5.8.1) and the new current expression including the velocity overshoot effect is obtained: (5.9.) I DS,HD = I DS dseff 1 + Leff E dseff 1 + L E eff O sat sat where (5.9.3) E O sat = E sat ds dseff 1+ LAMBDA Esat litl + Leff meff ds dseff 1+ Esat litl LAMBDA is the velocity overshoot coefficient. BSIM4.6.0 Manual Copyright 006 UC Berkeley 5-18

62 New Current Saturation Mechanisms: elocity Overshoot and Source End 5.9. Source End elocity Limit Model When MOSFETs come to nanoscale, because of the high electric field and strong velocity overshoot, carrier transport through the drain end of the channel is rapid. As a result, the dc current is controlled by how rapidly carriers are transported across a short low-field region near the beginning of the channel. This is known as injection velocity limits at the source end of the channel. A compact model is firstly developed to account for this current saturation mechanism. Hydro-dynamic transportation gives the source end velocity as : (5.9.4) I v = shd DS,HD Wq s where qs is the source end inversion charge density. Source end velocity limit gives the highest possible velocity which can be given through ballistic transport as: 1 r v sbt = TL 1 + r (5.9.5) where TL: thermal velocity, r is the back scattering coefficient which is given: (5.9.6) r = L XN L eff eff + LC XN 3.0 BSIM4.6.0 Manual Copyright 006 UC Berkeley 5-19

63 New Current Saturation Mechanisms: elocity Overshoot and Source End The real source end velocity should be the lower of the two, so a final Unified current expression with velocity saturation, velocity overshoot and source velocity limit can be expressed as : I DS = I DS,HD MM 1/ MM [ 1+ ( vshd / vsbt ) ] (5.9.7) where MM=.0. BSIM4.6.0 Manual Copyright 006 UC Berkeley 5-0

64 Chapter 6: Body Current Models In addition to the junction diode current and gate-to-body tunneling current, the substrate terminal current consists of the substrate current due to impact ionization (I ii ), and gateinduced drain leakage and source leakage currents (I GIDL and I GISL ). 6.1 I ii Model The impact ionization current model in BSIM4 is the same as that in BSIM3v3., and is modeled by (6.1.1) I ii = ALPHA0 + ALPHA1 L L eff eff BETA ( ds dseff ) 0 exp I dsnoscbe ds dseff where parameters ALPHA0 and BETA0 are impact ionization coefficients; parameter ALPHA1 is introduced to improves the I ii scalability, and (6.1.) I dsnoscbe I ds0 NF 1 = 1 + RdsIds 0 1+ C dseff clm ln A Asat ds 1+ ADIBL dseff ds 1+ ADITS dseff BSIM4.6.0 Manual Copyright 006 UC Berkeley 6-1

65 IGIDL and IGISL Model 6. I GIDL and I GISL Model The GIDL/GISL current and its body bias effect are modeled by [9]-[10] (6..1) I GIDL = AGIDL W effcj Nf ds EGIDL 3 T BGIDL 3 gse oxe db exp 3 3 T oxe ds gse EGIDL CGIDL + db I GISL = AGISL W effcj Nf ds EGISL 3 T (6..) BGISL 3 gde oxe sb exp 3 3 T oxe ds gde EGISL CGISL+ sb where AGIDL, BGIDL, CGIDL and EGIDL are model parameters for the drain side and AGISL, BGISL, CGISL and EGISL are the model parameters for the source side. They are explained in Appendix A. CGIDL and CGISL account for the body-bias dependence of I GIDL and I GISL respectively. W effcj and Nf are the effective width of the source/drain diffusions and the number of fingers. Further explanation of W effcj and Nf can be found in the chapter of the layout-dependence model. 6- BSIM4.6.0 Manual Copyright 006 UC Berkeley

66 Chapter 7: Capacitance Model Accurate modeling of MOSFET capacitance plays equally important role as that of the DC model. This chapter describes the methodology and device physics considered in both intrinsic and extrinsic capacitance modeling in BSIM Complete model parameters can be found in Appendix A. 7.1 General Description BSIM4.0.0 provides three options for selecting intrinsic and overlap/fringing capacitance models. These capacitance models come from BSIM3v3., and the BSIM3v3. capacitance model parameters are used without change in BSIM4. except that separate CKAPPA parameters are introduced for the source-side and drain-side overlap capacitances. The BSIM3v3. capmod = 1 is no longer supported in BSIM4. The following table maps the BSIM4 capacitance models to those of BSIM3v3.. BSIM4.6.0 Manual Copyright 006 UC Berkeley 7-1

67 General Description BSIM4 capacitance models capmod = 0 (simple and piecewise model) capmod = 1 (single-equation model) capmod = (default model; singel-equation and chargethickness model Matched capmod in BSIM3v3.. Intrinsic capmod = 0 + overlap/fringing capmod = 0 Intrinsic capmod = + overlap/fringing capmod = Intrinsic capmod = 3 + overlap/fringing capmod = Table 7-1. BSIM4 capacitance model options. BSIM4 capacitance models have the following features: Separate effective channel length and width are used for capacitance models. capmod = 0 uses piece-wise equations. capmod = 1 and are smooth and single equation models; therefore both charge and capacitance are continous and smooth over all regions. Threshold voltage is consistent with DC part except for capmod = 0, where a longchannel th is used. Therefore, those effects such as body bias, short/narrow channel and DIBL effects are explicitly considered in capmod = 1 and. Overlap capacitance comprises two parts: (1) a bias-independent component which models the effective overlap capacitance between the gate and the heavily doped source/drain; () a gate-bias dependent component between the gate and the lightly doped source/drain region. Bias-independent fringing capacitances are added between the gate and source as well as the gate and drain. 7- BSIM4.6.0 Manual Copyright 006 UC Berkeley

68 Methodology for Intrinsic Capacitance Modeling 7. Methodology for Intrinsic Capacitance Modeling 7..1 Basic Formulation To ensure charge conservation, terminal charges instead of terminal voltages are used as state variables. The terminal charges Q g, Q b, Q s, and Q d are the charges associated with the gate, bulk, source, and drain termianls, respectively. The gate charge is comprised of mirror charges from these components: the channel charge (Q inv ), accumulation charge (Q acc ) and substrate depletion charge (Q sub ). The accumulation charge and the substrate charge are associated with the substrate while the channel charge comes from the source and drain terminals ( ) Q = Q + Q + Q Qb = Qacc + Qsub Qinv = Qs + Qd g sub inv acc (7..1) The substrate charge can be divided into two components: the substrate charge at zero source-drain bias (Q sub0 ), which is a function of gate to substrate bias, and the additional non-uniform substrate charge in the presence of a drain bias (δq sub ). Q g now becomes ( ) Q = Q + Q + Q + Q g inv acc sub0 δ sub (7..) BSIM4.6.0 Manual Copyright 006 UC Berkeley 7-3

69 Methodology for Intrinsic Capacitance Modeling The total charge is computed by integrating the charge along the channel. The threshold voltage along the channel is modified due to the nonuniform substrate charge by th ( y) = th ( 0) + ( A bulk ) y 1 (7..3) Q Q Q c g b = W = W = W active active active Lactive Lactive Lactive q dy = W c active oxe 0 0 q dy = W g active oxe 0 0 q dy = W C C C b active oxe 0 0 L L active ( gt Abulky ) (7..4) active ( gt + th FB Φ s y ) active ( th FB Φ s + ( Abulk 1) y ) L dy dy dy where gt = gse - th and d dy = E y y where E y is expressed in (7..5) I ds W µ C A active eff oxe bulk = gt ds ds = W active µ eff Lactive C oxe ( gt A bulk y ) E y All capacitances are derived from the charges to ensure charge conservation. Since there are four terminals, there are altogether 16 components. For each component 7-4 BSIM4.6.0 Manual Copyright 006 UC Berkeley

70 Methodology for Intrinsic Capacitance Modeling C ij Qi = j (7..6) where i and j denote the transistor terminals. C ij satisfies ij = Cij = i C 0 j 7.. Short Channel Model The long-channel charge model assume a constant mobility with no velocity saturation. Since no channel length modulation is considered, the channel charge remains constant in saturation region. Conventional longchannel charge models assume dsat,c = gt / A bulk and therefore is independent of channel length. If we define a drain bias, dsat,c, for capacitance modeling, at which the channel charge becomes constant, we will find that dsat,c in general is larger than dsat for I- but smaller than the long-channel dsat = gt / A bulk. In other words, (7..7) dsat, I < dsat, C < dsat, I Lactive = gsteff, C A bulk and dsat,c is modeled by dsat, C = A bulk 1 + gsteff, C CLC L active CLE (7..8) BSIM4.6.0 Manual Copyright 006 UC Berkeley 7-5

71 Methodology for Intrinsic Capacitance Modeling (7..9) gsteff, C = NOFF nv + t ln 1 exp gse th OFFC NOFF nvt Model parameters CLC and CLE are introduced to consider the effect of channel-length modulation. A bulk for the capacitance model is modeled by (7..10) A bulk 1 + F doping L = eff A0 L + eff XJ X dep B0 1 + Weff ' + B1 1+ KETA bseff where F doping = 1+ LPEB Φ s L eff bseff K 1ox + K ox TOXE K3B Φ W ' + W 0 eff s 7..3 Single Equation Formulation Traditional MOSFET SPICE capacitance models use piece-wise equations. This can result in discontinuities and non-smoothness at transition regions. The following describes single-equation formulation for charge, capacitance and voltage modeling in capmod = 1 and. (a) Transition from depletion to inversion region The biggest discontinuity is at threshold voltage where the inversion capacitance changes abruptly from zero to C oxe. Concurrently, since the substrate charge is a constant, the substrate capacitance drops abruptly to 7-6 BSIM4.6.0 Manual Copyright 006 UC Berkeley

72 Methodology for Intrinsic Capacitance Modeling zero at threshold voltage. The BSIM4 charge and capacitance models are formulated by substituting gst with gsteff,c as ( ) = Q( ) Q gst gsteff, C (7..11) For capacitance modeling ( ) = C( ) C gst gsteff, C gsteff, C g, d, s, b (7..1) (b) Transition from accumulation to depletion region An effective smooth flatband voltage FBeff is used for the accumulation and depletion regions. (7..13) ( ) + ( ) fbzb gb 0.0 fbzb gb FBeff fbzb = fbzb where (7..14) fbzb = Φ K1 th zero bs and ds s Φ s A bias-independent th is used to calculate fbzb for capmod = 1 and. For capmod = 0, FBC is used instead (refer to Appendix A). BSIM4.6.0 Manual Copyright 006 UC Berkeley 7-7

73 Methodology for Intrinsic Capacitance Modeling (c) Transition from linear to saturation region An effective ds, cveff, is used to smooth out the transition between linear and saturation regions. (7..15) { δ 4dsat, C } where4 = dsat, C ds δ4; 0. cveff = dsat, C 0.5 δ 4 = Charge partitioning The inversion charges are partitioned into Q inv = Q s + Q d. The ratio of Q d to Q s is the charge partitioning ratio. Existing charge partitioning schemes are 0/100, 50/50 and 40/60 (XPART = 1, 0.5 and 0). 50/50 charge partition This is the simplest of all partitioning schemes in which the inversion charges are assumed to be contributed equally from the source and drain terminals. 40/60 charge partition This is the most physical model of the three partitioning schemes in which the channel charges are allocated to the source and drain terminals by assuming a linear dependence on channel position y. 7-8 BSIM4.6.0 Manual Copyright 006 UC Berkeley

74 Charge-Thickness Capacitance Model (CTM) Lactive Qs = Wactive q c 1 0 Lactive y Qd = Wactive qc L 0 active y L active dy dy (7..16) 0/100 charge partition In fast transient simulations, the use of a quasi-static model may result in a large unrealistic drain current spike. This partitioning scheme is developed to artificially suppress the drain current spike by assigning all inversion charges in the saturation region to the source electrode. Notice that this charge partitioning scheme will still give drain current spikes in the linear region and aggravate the source current spike problem. 7.3 Charge-Thickness Capacitance Model (CTM) Current MOSFET models in SPICE generally overestimate the intrinsic capacitance and usually are not smooth at fb and th. The discrepancy is more pronounced in thinner T ox devices due to the assumption of inversion and accumulation charge being located at the interface. Numerical quantum simulation results in Figure 7-1 indicate the significant charge thickness in all regions of operation. BSIM4.6.0 Manual Copyright 006 UC Berkeley 7-9

75 Charge-Thickness Capacitance Model (CTM) Normalized Charge Distribution E D Cgg (µf/cm ) A 0.6 B E D C C gs () A Tox=30A Nsub=5e17cm -3 B Depth (A) Figure 7-1. Charge distribution from numerical quantum simulations show significant charge thickness at various bias conditions shown in the inset. CTM is a charge-based model and therefore starts with the DC charge thicknss, X DC. The charge thicknss introduces a capacitance in series with C ox as illustrated in Figure 7-, resulting in an effective C oxeff. Based on numerical self-consistent solution of Shrodinger, Poisson and Fermi-Dirac equations, universal and analytical X DC models have been developed. C oxeff can be expressed as (7.3.1) C oxeff C = C oxp oxp C + C cen cen where ε C si cen = X DC 7-10 BSIM4.6.0 Manual Copyright 006 UC Berkeley

76 Charge-Thickness Capacitance Model (CTM) gs gse Φs Cox Poly depl. Cacc Cdep Cinv B Figure 7-. Charge-thickness capacitance concept in CTM. gse accounts for the poly depletion effect. (i) X DC for accumulation and depletion The DC charge thickness in the accumulation and depletion regions can be expressed by (7.3.) X DC = 1 3 L debye NDEP exp ACDE gse bseff TOXP FBeff where L debye is Debye length, and X DC is in the unit of cm and ( gse - bseff - FBeff ) / TOXP is in units of M/cm. For numerical statbility, (7.3.) is replaced by (7.3.3) X DC = X 1 ( X 0 + X 0 + δ x X max ) max 4 (7.3.3) BSIM4.6.0 Manual Copyright 006 UC Berkeley 7-11

77 Charge-Thickness Capacitance Model (CTM) where X 0 X = max X DC δ x and X max = L debye / 3; δ x = 10-3 TOXE. (ii) X DC of inversion charge The inversion charge layer thichness can be formulated as (7.3.4) X DC = 1+ gsteff ( TH 0 FB Φ ) TOXP m s 0.7 Through the FB term, equation (7.3.4) is found to be applicable to N + or P + poly- Si gates and even other future gate materials. (iii) Body charge thickness in inversion In inversion region, the body charge thickness effect is modeled by including the deviation of the surface potential (bias-dependence) from [] Φ s Φ B (7.3.5) gsteffc ( gsteffc + K ϕ δ = Φ s Φ B = ν t ln 1+ MOIN K1 ox ν 1ox t Φ B The channel charge density is therefore derived as (7.3.6) q inv = -Coxeff, ( gsteff C - ϕδ ) eff 7-1 BSIM4.6.0 Manual Copyright 006 UC Berkeley

78 Intrinsic Capacitance Model Equations where (7.3.7) ( ) ( ) ( ) gsteff, C ϕδ = 0.5 gsteff, C ϕ gsteff, C gsteff, C eff δ ϕδ 7.4 Intrinsic Capacitance Model Equations capmod = 0 Accumulation region Q g = W active L active Q C oxe ( FBC ) gs = sub Q g bs Q inv = 0 Q Subthreshold region sub0 ( FBC ) K 4 1ox = gs WactiveLactiveCoxe K1 ox Q = g Q sub0 Q inv = 0 bs BSIM4.6.0 Manual Copyright 006 UC Berkeley 7-13

79 Intrinsic Capacitance Model Equations Strong inversion region dsat, cv gs = A ' bulk th CLC A bulk ' = Abulk 1+ Leff CLE th = FBC + Φ s + K1 ox Φ s bseff Linear region Q g = C oxe W active L active gs FBC Φ s ds + 1 gs A bulk th ' ds A bulk ' ds Q b = C oxe W active L active FBC th Φ s + ( 1 A ') ( 1 A ') bulk ds 1 gs bulk th Abulk ' ds Abulk ' ds Q inv = C 50/50 partitioning: oxe W active L active gs th Φ s A bulk ' Q = Q = 0. 5Q s d inv ds + 1 gs A bulk th ' ds A bulk ' ds 7-14 BSIM4.6.0 Manual Copyright 006 UC Berkeley

80 Intrinsic Capacitance Model Equations Q d = C oxe W 40/60 partitioning: active L active gs th A s bulk ' ds A + bulk ' ds ( Q + Q Q ) Q = + g b d ( ) ' ( ) gs th Abulk ds gs th ( Abulk ' ds ) [ + ] A ' bulk ds 1 ( ) gs th 0/100 partitioning: Q d = C oxe W active L active s gs th A + bulk ' 4 ( Q + Q Q ) Q = + g b d ds ( A ' ) bulk 4 ds Saturation region Q b Q g = C = C oxe W oxe W active active L L active active gs FBC + Φ FBC Φ s th + s 3 dsat ( A ') 1 bulk dsat 3 50/50 partitioning: Q s = Q d 1 = C 3 oxe W active L active ( ) gs th 40/60 partitioning: Q d 4 = 15 s C oxe W active L active ( ) gs ( Q + Q Q ) Q = + g b d th BSIM4.6.0 Manual Copyright 006 UC Berkeley 7-15

81 Intrinsic Capacitance Model Equations 0/100 partitioning: s Q d = 0 ( Q Q ) Q = + g b 7.4. capmod = 1 Q g ( Q + Q + Q + δq ) = inv acc sub0 sub Q b ( Q + Q + δq ) = acc sub0 sub Q = Q + Q inv s d Q sub0 = W active L Q active acc C = W oxe K1 active ox L active -1+ C oxe dsat, cv = A 4 1+ gsteffcv bulk ( ) ' FBeff fbzb ( ) gse FBeff gsteff K1 ox bseff 7-16 BSIM4.6.0 Manual Copyright 006 UC Berkeley

82 Intrinsic Capacitance Model Equations BSIM4.6.0 Manual Copyright 006 UC Berkeley /50 charge partitioning: 40/60 charge partitioning: + = ' 1 ' ' 1,, cveff bulk cv gsteff cveff bulk cveff bulk cv gsteff oxe active active inv A A A C L W Q ( ) = ' 1 ' ' 1 ' 1, cveff bulk cv gsteff cveff bulk bulk cveff bulk oxe active active sub A A A A C L W δq + = = ' 1 ' ' 1,, cveff bulk cv gsteff cveff bulk cveff bulk cv gsteff oxe active active D S A A A C L W Q Q ( ) ( ) + = 3,, 3,, ' 15 ' 3 ' 3 4 ' cveff bulk cveff bulk cv gsteff cveff bulk cv gsteff cv gsteff cveff bulk cv gsteff oxe active active S A A A A C L W Q ( ) ( ) + = 3,, 3,, ' 5 1 ' ' 3 5 ' cveff bulk cveff bulk cv gsteff cveff bulk cv gsteff cv gsteff cveff bulk cv gsteff oxe active active D A A A A C L W Q

83 Intrinsic Capacitance Model Equations 0/100 charge partitioning: Q S W = active L active C oxe gsteff, cv + 1 A bulk ' cveff 1 A gsteff, cv ' bulk A cveff bulk ' cveff Q D W = active L active C oxe gsteff, cv 3 A bulk ' cveff + 4 A gsteff, cv ' bulk A cveff bulk ' dveff capmod = Q acc = W active L active C oxeff gbacc [ ] 1 gbacc = fbzb 08 0 = fbzb + bseff gs 0.0 ( dsat ) 1 cveff = dsat 08 1 = dsat ds 0.0 dsat = gsteff, cv A bulk ϕ δ ' gsteffc ( gsteffc + K ϕ δ = Φ s Φ B = ν t ln 1+ MOIN K1 ox ν 1ox t Φ B BSIM4.6.0 Manual Copyright 006 UC Berkeley 7-18

84 Intrinsic Capacitance Model Equations ( ) ( ) ( ) gsteff, C ϕδ = 0.5 gsteff, C ϕ gsteff, C gsteff, C eff δ ϕδ Q sub0 = W active L active C oxeff K1 ox ( ) gse FBeff K bseffs 1ox gsteff, cv Q inv = -W active L active C oxeff Ø Œ Œ Œ Œ º ( -j ) gsteff, cv d eff 1 - A bulk ' cveff + 1 Ł bulk cveff ø œ A ( - ) - œ œœ bulk' cveff j gsteff, cv A d ' eff łß δq sub = W active L active C oxeff 1 A bulk ' cveff 1 ( 1 A ') gsteff, cv bulk ϕ δ A bulk A ' bulk cveff ' cveff 50/50 partitioning: Q S = Q D W = - active L active C oxeff Ø Œ Œ Œ Œ º gsteff, cv -j d 1 - A bulk ' cveff + 1 Ł cveff ø œ A ( - ) - œ œœ bulk' cveff j gsteff, cv A bulk d ' eff łß BSIM4.6.0 Manual Copyright 006 UC Berkeley 7-19

85 Fringing/Overlap Capacitance Models Q S = 40/60 partitioning: 3 4 ( ϕ ) ( ϕ ) gsteff, cv δ gsteff, cv δ Abulk ' WactiveLactiveCoxeff 3 A ' bulk cveff +, gsteff, cv bulk cveff bulk ' cv ϕδ δ 3 15 ( )( ) ( ) 3 ϕ A ' A gsteff cveff cveff Q D = 3 5 ( gsteff, cv ϕδ ) ( gsteff, cv ϕδ ) Abulk ' cveff 3 ( )( ) ( ) ϕ A ' A W activelactivecoxeff Abulk ' cveff, gsteff, cv bulk cveff bulk ' cv ϕδ δ 5 gsteff cveff 0/100 partitioning: Q S W = active L active C oxeff gsteff, cv ϕ δ + 1 A bulk ' cveff 1 A gsteff, cv ' bulk ϕ δ cveff A bulk ' cveff Q D W = - active L active C oxeff Ø Œ Œ Œ Œ º ( -j ) gsteff, cv d eff 3 - A bulk ' cveff + 4 Ł bulk cveff ø œ A ( - ) - œ œœ bulk' dveff j gsteff, cv A d ' eff łß 7.5 Fringing/Overlap Capacitance Models Fringing capacitance model The fringing capacitance consists of a bias-independent outer fringing capacitance and a bias-dependent inner fringing capacitance. Only the biasindependent outer fringing capacitance (CF) is modeled. If CF is not given, it is calculated by BSIM4.6.0 Manual Copyright 006 UC Berkeley 7-0

86 Fringing/Overlap Capacitance Models (7.5.1) EPSROX ε CF π 1 4.0e 7 = log TOXE 7.5. Overlap capacitance model An accurate overlap capacitance model is essential. This is especially true for the drain side where the effect of the capacitance is amplified by the transistor gain. In old capacitance models this capacitance is assumed to be bias independent. However, experimental data show that the overlap capacitance changes with gate to source and gate to drain biases. In a single drain structure or the heavily doped S/D to gate overlap region in a LDD structure the bias dependence is the result of depleting the surface of the source and drain regions. Since the modulation is expected to be very small, we can model this region with a constant capacitance. However in LDD MOSFETs a substantial portion of the LDD region can be depleted, both in the vertical and lateral directions. This can lead to a large reduction of the overlap capacitance. This LDD region can be in accumulation or depletion. We use a single equation for both regions by using such smoothing parameters as gs,overlap and gd,overlap for the source and drain side, respectively. Unlike the case with the intrinsic capacitance, the overlap capacitances are reciprocal. In other words, C gs,overlap = C sg,overlap and C gd,overlap = C dg,overlap. If capmod is non-zero, BSIM4 uses the bias-dependent overlap capacitance model; otherwise, a simple bias-independent model will be used. BSIM4.6.0 Manual Copyright 006 UC Berkeley 7-1

87 Fringing/Overlap Capacitance Models Bias-dependent overlap capacitance model (i) Source side Q W + CGSL CKAPPAS 1+ (7.5.) gs overlap 1 CKAPPAS overlap s = CGSO gs gs gs, overlap 4, active Q W (7.5.3) ( + δ ) 4δ, 0. 1 gs, overlap = gs + δ1 gs = 0 + δ (ii) Drain side (7.5.4) + CGDL CKAPPAD 1+ gd overlap 1 CKAPPAD overlap d = CGDO gd gd gd, overlap 4, active (iii) Gate Overlap Charge (7.5.5) ( + δ ) 4δ, 0. 1 gd, overlap = gd + δ 1 gd = 0 + δ Q overlap, g (7.5.6) ( Q + Q + ( CGBO L ) ) = overlap, d overlap, s active gb where CGBO is a model parameter, which represents the gate-to-body overlap capacitance per unit channel length. BSIM4.6.0 Manual Copyright 006 UC Berkeley 7-

88 Fringing/Overlap Capacitance Models Bias-independent overlap capacitance model If capmod = 0, a bias-independent overlap capacitance model will be used. In this case, model parameters CGSL, CGDL, CKAPPAS and CKAPPD all have no effect. The gate-to-source overlap charge is expressed by Q overlap, s = W active CGSO gs The gate-to-drain overlap charge is calculated by Q overlap, d = W active CGDO gd The gate-to-substrate overlap charge is computed by Q overlap, b = L active CGBO gb Default CGSO and CGDO If CGSO and CGDO (the overlap capacitances between the gate and the heavily doped source/drain regions, respectively) are not given, they will be calculated. Appendix A gives the information on how CGSO, CGDO and CGBO are calculated. BSIM4.6.0 Manual Copyright 006 UC Berkeley 7-3

89 Chapter 8: High-Speed/RF Models As circuit speed and operating frequency rise, the need for accurate prediction of circuit performance near cut-off frequency or under very rapid transient operation becomes critical. BSIM4.0.0 provides a set of accurate and efficient high-speed/rf (radio frequency) models which consist of three modules: charge-deficit non-quasi-static (NQS) model, intrinsic-input resistance (IIR) model (bias-dependent gate resistance model), and substrate resistance network model. The charge-deficit NQS model comes from BSIM3v3. NQS model [11] but many improvements are added in BSIM4. The IIR model considers the effect of channel-reflected gate resistance and therefore accounts for the first-order NQS effect [1]. Thus, the charge-deficit NQS model and the IIR model should not be turned on simultaneously. These two models both work with multi-finger configuration. The substrate resistance model does not include any geometry dependence. 8.1 Charge-Deficit Non-Quasi-Static (NQS) Model BSIM4 uses two separate model selectors to turn on or off the charge-deficit NQS model in transient simulation (using trnqsmod) and AC simulation (using acnqsmod). The AC NQS model does not require the internal NQS charge node that is needed for the transient NQS model. The transient and AC NQS models are developed from the same fundamental physics: the channel/gate charge response to the external signal are relaxation-time (τ) dependent and the transcapacitances BSIM4.6.0 Manual Copyright 006 UC Berkeley 8-1

90 Charge-Deficit Non-Quasi-Static (NQS) Model and transconductances (such as G m ) for AC analysis can therefore be expressed as functions of jωτ. MOSFET channel region is analogous to a bias-dependent RC distributed transmission line (Figure 8-1a). In the Quasi-Static (QS) approach, the gate capacitor node is lumped with the external source and drain nodes (Figure 8-1b). This ignores the finite time for the channel charge to build-up. One way to capture the NQS effect is to represent the channel with n transistors in series (Figure 8-1c), but it comes at the expense of simulation time. The BSIM4 charge-deficit NQS model uses Elmore equivalent circuit to model channel charge build-up, as illustrated in Figure 8-1d.. Figure 8-1. Quasi-Static and Non-Quasi-Static models for SPICE analysis. 8- BSIM4.6.0 Manual Copyright 006 UC Berkeley

91 Charge-Deficit Non-Quasi-Static (NQS) Model The Transient Model The transient charge-deficit NQS model can be turned on by setting trnqsmod = 1 and off by setting trnqsmod = 0. Figure 8- shows the RC sub-circuit of charge deficit NQS model for transient simulation [13]. An internal node, Q def (t), is created to keep track of the amount of deficit/surplus channel charge necessary to reach equilibrium. The resistance R is determined from the RC time constant (τ). The current source i cheq (t) represents the equilibrium channel charging effect. The capacitor C is to be the value of C fact (with a typical value of Farad [11]) to improve simulation accuracy. Q def now becomes def ( t) = def C fact Q (8.1.1) Q def i cheq (t) C def R Figure 8-. Charge deficit NQS sub-circuit for transient analysis. BSIM4.6.0 Manual Copyright 006 UC Berkeley 8-3

92 Charge-Deficit Non-Quasi-Static (NQS) Model Considering both the transport and charging component, the total current related to the terminals D, G and S can be written as Qd, g, s id, G, S ( t) = I D, G, S ( DC) + t ( t) (8.1.) Based on the relaxation time approach, the terminal charge and corresponding charging current are modeled by Q def ( t) = Q ( t) Q ( t) cheq ch (8.1.3) and Q Q def t d, g, s t ( t) Q ( t) Q ( t) = cheq t def τ ( t) Q ( t) = D, G, S xpart def τ (8.1.4a) (8.1.4b) where D,G,S xpart are charge deficit NQS channel charge partitioning number for terminals D, G and S, respectively; D xpart + S xpart = 1 and G xpart = -1. The transit time τ is equal to the product of R ii and W eff L eff C oxe, where R ii is the intrinsic-input resistance [1] given by 8-4 BSIM4.6.0 Manual Copyright 006 UC Berkeley

93 Charge-Deficit Non-Quasi-Static (NQS) Model 1 R ii I = XRCRG1 ds dseff W + XRCRG eff µ eff C ql oxeff eff (8.1.5) k BT where C oxeff is the effective gate dielectric capacitance calculated from the DC model. Note that R ii in (8.1.5) considers both the drift and diffusion componets of the channel conduction, each of which dominates in inversion and subthreshold regions, respectively The AC Model Similarly, the small-signal AC charge-deficit NQS model can be turned on by setting acnqsmod = 1 and off by setting acnqsmod = 0. For small signals, by substituting (8.1.3) into (8.1.4b), it is easy to show that in the frequency domain, Q ch (t) can be transformed into Q ch ( t) ( t) Qcheq = 1+ jωτ (8.1.6) where ω is the angular frequency. Based on (8.1.6), it can be shown that the transcapacitances C gi, C si, and C di (i stands for any of the G, D, S and B terminals of the device) and the channel transconductances G m, G ds, and G mbs all become complex quantities. For example, now G m have the form of BSIM4.6.0 Manual Copyright 006 UC Berkeley 8-5

94 Gate Electrode Electrode and Intrinsic-Input Resistance (IIR) Model (8.1.7) G m Gm G 0 m0 ωτ + j 1+ ω τ 1+ ω τ = and (8.1.8) C dg Cdg 0 Cdg 0 ωτ + j 1+ ω τ 1+ ω τ = Those quantities with sub 0 in the above two equations are known from OP (operating point) analysis. 8. Gate Electrode Electrode and Intrinsic- Input Resistance (IIR) Model 8..1 General Description BSIM4 provides four options for modeling gate electrode resistance (biasindependent) and intrinsic-input resistance (IIR, bias-dependent). The IIR model considers the relaxation-time effect due to the distributive RC nature of the channel region, and therefore describes the first-order non-quasistatic effect. Thus, the IIR model should not be used together with the charge-deficit NQS model at the same time. The model selector rgatemod is used to choose different options. BSIM4.6.0 Manual Copyright 006 UC Berkeley 8-6

95 Gate Electrode Electrode and Intrinsic-Input Resistance (IIR) Model 8.. Model Option and Schematic rgatemod = 0 (zero-resistance): In this case, no gate resistance is generated. rgatemod = 1 (constant-resistance): Rgeltd In this case, only the electode gate resistance (bias-independent) is generated by adding an internal gate node. Rgeltd is give by (8.1.9) Rgeltd RSHG NGCON W ( XGW + effcj ) 3 NGCON = ( L XGL) NF drawn Refer to Chapter 7 for the layout parameters in the above equation. rgatemod = (IIR model with variable resistance): Rgeltd+R ii BSIM4.6.0 Manual Copyright 006 UC Berkeley 8-7

96 Substrate Resistance Network In this case, the gate resistance is the sum of the electrode gate resistance (8.1.9) and the intrinsic-input resistance R ii as given by (8.1.5). An internal gate node will be generated. trnqsmod = 0 (default) and acnqsmod = 0 (default) should be selected for this case. rgatemod = 3 (IIR model with two nodes): Rgeltd Cgso R ii Cgdo In this case, the gate electrode resistance given by (8.1.9) is in series with the intrinsic-input resistance R ii as given by (8.1.5) through two internal gate nodes, so that the overlap capacitance current will not pass through the intrinsic-input resistance. trnqsmod = 0 (default) and acnqsmod = 0 (default) should be selected for this case. 8.3 Substrate Resistance Network General Description For CMOS RF circuit simulation, it is essential to consider the high frequency coupling through the substrate. BSIM4 offers a flexible built-in substrate resistance network. This network is constructed such that little simulation efficiency penalty will result. Note that the substrate resistance parameters as listed in Appendix A should be extracted for the total device, not on a per-finger basis. BSIM4.6.0 Manual Copyright 006 UC Berkeley 8-8

97 Substrate Resistance Network 8.3. Model Selector and Topology The model selector rbodymod can be used to turn on or turn off the resistance network. rbodymod = 0 (Off): No substrate resistance network is generated at all. rbodymod = 1 (On): All five resistances in the substrate network as shown schematically below are present simultaneously. A minimum conductance, GBMIN, is introduced in parallel with each resistance and therefore to prevent infinite resistance values, which would otherwise cause poor convergence. In Figure 8-3, GBMIN is merged into each resistance to simplify the representation of the model topology. Note that the intrinsic model substrate reference point in this case is the internal body node bnodeprime, into which the impact ionization current I ii and the GIDL current I GIDL flow. rbodymod = (On : Scalable Substrate Network): The schematic is similar to rbodymod = 1 but all the five resistors in the substrate network are now scalable with a possibility of chosing either five resistors, three resistors or one resistor as the substrate network. The resistors of the substrate network are scalable with respect to channel length (L), channel width (W) and number of fingers (NF). The scalable model allows to account for both horizontal and vertical contacts. The scalable resistors RBPS and RBPD are evaluated through BSIM4.6.0 Manual Copyright 006 UC Berkeley 8-9

98 Substrate Resistance Network RBPS L RBPS 0 10 RBPSL W 10 = 6 6 RBPSW (8.1.10) NF (8.1.11) RBPSNF RBPD L RBPD 0 10 RBPDL W 10 = 6 6 RBPDW NF RBPDNF The resistor RBPB consists of two parallel resistor paths, one to the horizontal contacts and other to the vertical contacts. These two resistances are scalable and RBPB is given by a parallel combination of these two resistances. (8.1.1) RBPBX L RBPBX 0 10 RBPBXL W 10 = 6 6 RBPBXW NF RBPBNF RBPBY L RBPBY 0 10 RBPBYL W 10 = 6 6 RBPBYW NF RBPBYNF RBPB = RBPBX RBPBX RBPBY + RBPBY The resistors RBSB and RBDB share the same scaling parameters but have different scaling prefactors. These resistors are modeled in the same way as RBPB. The equations for RBSB are shown below. The calculation for RBDB follows RBSB. BSIM4.6.0 Manual Copyright 006 UC Berkeley 8-10

99 Substrate Resistance Network (8.1.13) RBSBX RBSBX L 0 10 RBSDBXL W 10 = 6 6 RBSDBXW NF RBSDBXNF RBSBX L RBSBX 0 10 RBSDBXL W 10 = 6 6 RBSDBXW NF RBSDBXNF RBSB = RBSBX RBSBX + RBSBY RBSBY The implementation of rbodymod = allows the user to chose between the 5-R network (with all five resistors), 3-R network (with RBPS, RBPD and RBPB) and 1-R network (with only RBPB). If the user doesn t provide both the scaling parameters RBSBX0 and RBSBY0 for RBSB OR both the scaling parameters RBDBX0 and RBDBY0 for RBDB, then the conductances for both RBSB and RBDB are set to GBMIN. This converts the 5-R schematic to 3-R schematic where the substrate network consists of the resistors RBPS, RBPD and RBPB. RBPS, RBPD and RBPB are then calculated using (8.1.10), (8.1.11) and (8.1.1). If the user chooses not to provide either of RBPS0 or RBPD0, then the 5-R schematic is converted to 1-R network with only one resistor RBPB. The conductances for RBSB and RBDB are set to GBMIN. The resistances RBPS and RBPD are set to 1e-3 Ohm. The resistor RBPB is then calculated using (8.1.1). In all other situations, 5-R network is used with the resistor values calculated from the equations aforementioned. BSIM4.6.0 Manual Copyright 006 UC Berkeley 8-11

100 Substrate Resistance Network I DS sbnode RBPS bnodeprime I ii + I GIDL RBPD dbnode RBSB RBPB RBDB bnode Figure 8-3. Topology with the substrate resistance network turned on. BSIM4.6.0 Manual Copyright 006 UC Berkeley 8-1

101 Chapter 9: Noise Modeling The following noise sources in MOSFETs are modeled in BSIM4 for SPICE noise ananlysis: flicker noise (also known as 1/f noise), channel thermal noise and induced gate noise and their correlation, thermal noise due to physical resistances such as the source/ drain, gate electrode, and substrate resistances, and shot noise due to the gate dielectric tunneling current. A complete list of the noise model parameters and explanations are given in Appendix A. 9.1 Flicker Noise Models General Description BSIM4 provides two flicker noise models. When the model selector fnoimod is set to 0, a simple flicker noise model which is convenient for hand calculations is invoked. A unified physical flicker noise model, which is the default model, will be used if fnoimod = 1. These two modes come from BSIM3v3, but the unified model has many improvements. For instance, it is now smooth over all bias regions and considers the bulk charge effect Equations fnoimod = 0 (simple model) BSIM4.6.0 Manual Copyright 006 UC Berkeley 9-1

102 Flicker Noise Models The noise density is (9.1.1) KF I ds ( f ) = EF Sid CoxeLeff AF f where f is device operating frequency. S id,inv ( f ) = C + W fnoimod = 1 (unified model) The physical mechanism for the flicker noise is trapping/detrapping-related charge fluctuation in oxide traps, which results in fluctuations of both mobile carrier numbers and mobilities in the channel. The unified flicker noise model captures this physical process. In the inversion region, the noise density is expressed as [14] eff oxe ( L eff eff LINTNOI) A B B k TI k Tq m ds L eff clm ds ( L LINTNOI) f I bulk ef f ef * N0 + N NOIA log + NOIB * Nl N + NOIA+ NOIB N l + NOIC N * ( N + N ) l l (9.1.) NOIC ( N N ) + ( N N ) 0 l 0 l where µ eff is the effective mobility at the given bias condition, and L eff and W eff are the effective channel length and width, respectively. The parameter N 0 is the charge density at the source side given by 9- BSIM4.6.0 Manual Copyright 006 UC Berkeley

103 Flicker Noise Models (9.1.3) N 0 = C oxe gsteff q The parameter N l is the charge density at the drain end given by (9.1.4) N l = C oxe gsteff A 1 bulk gsteff dseff + ν t q N * is given by N * ( C + C CIT ) kb T oxe d + = q (9.1.5) where CIT is a model parameter from DC I and C d is the depletion capacitance. L clm is the channel length reduction due to channel length modulation and given by (9.1.6) Lclm = Litl log SAT E sat = µ eff ds dseff Litl E sat + EM In the subthreshold region, the noise density is written as BSIM4.6.0 Manual Copyright 006 UC Berkeley 9-3

104 Channel Thermal Noise (9.1.7) S id, subt ( f ) NOIA kbt = EF W L f N eff eff Ids * The total flicker noise density is S id ( f ) S = S id, inv id, subvt ( f ) Sid, subvt ( f ) ( f ) + S ( f ) id, inv (9.1.8) 9. Channel Thermal Noise There are two channel thermal noise models in BSIM4. One is a chargebased model (default model) similar to that used in BSIM3v3.. The other is the holistic model. These two models can be selected through the model selector tnoimod. tnoimod = 0 (charge based) The noise current is given by i d = R ds 4k T f B ( ) + µ eff eff L Q inv NTNOI (9..1) where R ds () is the bias-dependent LDD source/drain resistance, and the parameter NTNOI is introduced for more accurate fitting of short-channel devices. Q inv is modeled by 9-4 BSIM4.6.0 Manual Copyright 006 UC Berkeley

105 Channel Thermal Noise (9..) Q inv = W active L active C oxeff NF gsteff A bulk dseff A ( ) bulk dseff + A 1 bulk gsteff dseff Figure 9-1a shows the noise source connection for tnoimod = 0. v d i d Source side i d (a) tnoimod = 0 (b) tnoimod = 1 Figure 9-1. Schematic for BSIM4 channel thermal noise modeling. tnoimod = 1 (holistic) In this thermal noise model, all the short-channel effects and velocity saturation effect incorporated in the I model are automatically included, hency the name holistic thermal noise model. In addition, the amplification of the channel thermal noise through G m and G mbs as well as the induced-gate noise with partial correlation to the channel thermal noise are all captured in the new noise partition model. Figure 9-1b shows schematically that part of the channel thermal noise source is partitioned to the source side. The noise voltage source partitioned to the source side is given by BSIM4.6.0 Manual Copyright 006 UC Berkeley 9-5

106 Channel Thermal Noise (9..3) v d = 4k T θ B tnoi dseff I ds f and the noise current source put in the channel region with gate and body amplication is given by d i dseff f = 4kBT ds β I v d ds [ G + ( G + G )] ( G + G + G ) m ds mbs tnoi m mbs (9..4) where (9..5) θ tnoi = RNOIB 1 + TNOIB L eff EsatL gsteff eff and (9..6) β tnoi = RNOIA 1 + TNOIA L eff EsatL gsteff eff where RNOIB and RNOIA are model parameters with default values 0.37 and respectively. BSIM4.6.0 Manual Copyright 006 UC Berkeley 9-6

107 Other Noise Sources Modeled 9.3 Other Noise Sources Modeled BSIM4 also models the thermal noise due to the substrate, electrode gate, and source/drain resistances. Shot noise due to various gate tunneling components is modeled as well. BSIM4.6.0 Manual Copyright 006 UC Berkeley 9-7

108 Chapter 10: Asymmetric MOS Junction Diode Models 10.1 Junction Diode I Model In BSIM4, there are three junction diode I models. When the I model selector diomod is set to 0 ("resistance-free"), the diode I is modeled as resistance-free with or without breakdown depending on the parameter values of XJBS or XJBD. When diomod is set to 1 ("breakdown-free"), the diode is modeled exactly the same way as in BSIM3v3. with current-limiting feature in the forward-bias region through the limiting current parameters IJTHSFWD or IJTHDFWD; diode breakdown is not modeled for diomod = 1 and XJBS, XJBD, BS, and BD parameters all have no effect. When diomod is set to ("resistance-and-breakdown"), BSIM4 models the diode breakdown with current limiting in both forward and reverse operations. In general, setting diomod to 1 produces fast convergence Source/Body Junction Diode In the following, the equations for the source-side diode are given. The model parameters are shown in Appendix A. BSIM4.6.0 Manual Copyright 006 UC Berkeley 10-1

109 Junction Diode I Model diomod = 0 (resistance-free) (10.1.1) I bs = I sbs q bs exp 1 f NJS kbtnom breakdown + bs G min where I sbs is the total saturation current consisting of the components through the gate-edge (J sswgs ) and isolation-edge sidewalls (J ssws ) and the bottom junction (J ss ), I sbs = A seff J ss ( T ) + P J ( T ) + W NF J ( T ) seff ssws effcj sswgs (10.1.) where the calculation of the junction area and perimeter is discussed in Chapter 11, and the temperature-dependent current density model is given in Chapter 1. In (10.1.1), f breakdown is given by f breakdown ( BS + ) q bs = 1+ XJBS exp NJS kbtnom (10.1.3) In the above equation, when XJBS = 0, no breakdown will be modeled. If XJBS < 0.0, it is reset to 1.0. diomod = 1 (breakdown-free) No breakdown is modeled. The exponential I term in (10.1.4) is linearized at the limiting current IJTHSFWD in the forward-bias model only. 10- BSIM4.6.0 Manual Copyright 006 UC Berkeley

110 Junction Diode I Model I bs = I sbs qbs exp NJS kbtnom 1 + bs G min (10.1.4) diomod = (resistance-and-breakdown): Diode breakdown is always modeled. The exponential term (10.1.5) is linearized at both the limiting current IJTHSFWD in the forward-bias mode and the limiting current IJTHSRE in the reverse-bias mode. (10.1.5) I bs = I sbs q bs exp 1 f NJS kbtnom breakdown + bs G min For diomod =, if XJBS <= 0.0, it is reset to Drain/Body Junction Diode The drain-side diode has the same system of equations as those for the source-side diode, but with a separate set of model parameters as explained in detail in Appendix A. diomod = 0 (resistance-free) I bd = I sbd qbd exp NJD kbtnom 1 f breakdown + bd (10.1.6) G min where I sbd is the total saturation current consisting of the components through the gate-edge (J sswgd ) and isolation-edge sidewalls (J sswd ) and the bottom junction (J sd ), BSIM4.6.0 Manual Copyright 006 UC Berkeley 10-3

111 Junction Diode I Model I sbd = A deff J sd (10.1.7) ( T ) + P J ( T ) + W NF J ( T ) deff sswd effcj sswgd where the calculation of the junction area and perimeter is discussed in Chapter 11, and the temperature-dependent current density model is given in Chapter 1. In (10.1.6), f breakdown is given by f breakdown q = 1+ XJBD exp NJD k ( BD + ) B bd TNOM (10.1.8) In the above equation, when XJBD = 0, no breakdown will be modeled. If XJBD < 0.0, it is reset to 1.0. diomod = 1 (breakdown-free) No breakdown is modeled. The exponential I term in (10.1.9) is linearized at the limiting current IJTHSFWD in the forward-bias model only. I bd = I sbd q bd exp 1 + NJD kbtnom bd G min (10.1.9) diomod = (resistance-and-breakdown): Diode breakdown is always modeled. The exponential term ( ) is linearized at both the limiting current IJTHSFWD in the forward-bias mode and the limiting current IJTHSRE in the reverse-bias mode. BSIM4.6.0 Manual Copyright 006 UC Berkeley 10-4

112 Junction Diode I Model I bd = I sbd qbd exp NJD kbtnom 1 f breakdown + bd ( ) G min For diomod =, if XJBD <= 0.0, it is reset to Total Junction Source/Drain Diode Including Tunneling Total diode current including the carrier recombination and trap-assisted tunneling current in the space-charge region is modeled by: ( ) I bs _ total = I W P A bs effcj s, deff s, deff NF J J J tssws tss tsswgs bs TSSWGS ( T ) exp NJTSSWG ( T ) tm 0 TSSWGS bs TSSWS ( T ) exp NJTSSW ( T ) tm 0 TSSWS bs TSS ( T ) exp NJTS ( T ) tm 0 TSS bs bs 1 + g 1 `min bs bs 1 (10.1.1) I bd _ total = I W P A bd effcj d, deff d, deff NF J J J tsswd tsd tsswgd bd TSSWGD ( T ) exp NJTSSWGD ( T ) tm 0 TSSWGD bd TSSWD ( T ) exp NJTSSWD ( T ) tm 0 TSSWD bd TSD ( T ) exp NJTSD ( T ) tm 0 TSD bd bd 1 + g 1 `min bd bd 1 BSIM4.6.0 Manual Copyright 006 UC Berkeley 10-5

113 Junction Diode C Model 10. Junction Diode C Model Source and drain junction capacitances consist of three components: the bottom junction capacitance, sidewall junction capacitance along the isolation edge, and sidewall junction capacitance along the gate edge. An analogous set of equations are used for both sides but each side has a separate set of model parameters Source/Body Junction Diode The source-side junction capacitance can be calculated by (10..1) C bs = A seff C jbs + P seff C jbssw + W effcj NF C jbsswg where C jbs is the unit-area bottom S/B junciton capacitance, C jbssw is the unit-length S/B junction sidewall capacitance along the isolation edge, and C jbsswg is the unit-length S/B junction sidewall capacitance along the gate edge. The effective area and perimeters in (10..1) are given in Chapter 11. C jbs is calculated by if bs < 0 (10..) C jbs = CJS( T ) 1 PBS bs ( T ) MJS otherwise 10-6 BSIM4.6.0 Manual Copyright 006 UC Berkeley

114 Junction Diode C Model (10..3) bs C jbs = CJS( T ) 1+ MJS PBS ( T ) C jbssw is calculated by if bs < 0 (10..4) C jbssw = bs CJSWS( T ) 1 PBSWS ( T ) MJSWS otherwise bs C jbssw = CJSWS( T ) 1+ MJSWS PBSWS ( T ) (10..5) C jbsswg is calculated by if bs < 0 (10..6) C jbsswg = bs CJSWGS( T ) 1 PBSWGS ( T ) MJSWGS otherwise BSIM4.6.0 Manual Copyright 006 UC Berkeley 10-7

115 Junction Diode C Model (10..7) C jbsswg = bs CJSWGS( T ) 1 PBSWGS ( T ) MJSWGS 10.. Drain/Body Junction Diode The drain-side junction capacitance can be calculated by (10..8) C bd = A deff C jbd + P deff C jbdsw + W effcj NF C jbdswg where C jbd is the unit-area bottom D/B junciton capacitance, C jbdsw is the unit-length D/B junction sidewall capacitance along the isolation edge, and C jbdswg is the unit-length D/B junction sidewall capacitance along the gate edge. The effective area and perimeters in (10..8) are given in Chapter 11. C jbd is calculated by if bd < 0 (10..9) C jbd = bd CJD( T ) 1 PBD T ( ) MJD otherwise (10..10) C ( ) = CJD T jbd 1 bd + MJD PBD T ( ) 10-8 BSIM4.6.0 Manual Copyright 006 UC Berkeley

116 Junction Diode C Model C jbdsw is calculated by if bd < 0 (10..11) C jbdsw = bd CJSWD( T ) 1 PBSWD T ( ) MJSWD otherwise bd C jbdsw = CJSWD( T ) 1+ MJSWD PBSWD T ( ) (10..1) C jbdswg is calculated by if bd < 0 (10..13) C jbdswg = bd CJSWGD( T ) 1 PBSWGD T ( ) MJSWGD otherwise C ( ) = CJSWGD T jbdswg 1 bd + MJSWGD PBSWGD T (10..14) ( ) BSIM4.6.0 Manual Copyright 006 UC Berkeley 10-9

117 Chapter 11: Layout-Dependent Parasitics Model BSIM4 provides a comprehensive and versatile geometry/layout-dependent parasitcs model [15]. It supports modeling of series (such as isolated, shared, or merged source/ drain) and multi-finger device layout, or a combination of these two configurations. This model have impact on every BSIM4 sub-models except the substrate resistance network model. Note that the narrow-width effect in the per-finger device with multi-finger configuration is accounted for by this model. A complete list of model parameters and selectors can be found in Appendix A Geometry Definition Figure 11-1 schematically shows the geometry definition for various source/drain connections and source/drain/gate contacts. The layout parameters shown in this figure will be used to calculate resistances and source/drain perimeters and areas. BSIM4.6.0 Manual Copyright 006 UC Berkeley 11-1

118 Geometry Definition DMCI of Point contact, isolated DMCG of Wide contact, shared L drawn -XGL DMDG No contact, merged XGW DMCI of Wide contact Figure Definition for layout parameters. 11- BSIM4.6.0 Manual Copyright 006 UC Berkeley

119 Model Formulation and Options 11. Model Formulation and Options Effective Junction Perimeter and Area In the following, only the source-side case is illustrated. The same approach is used for the drain side. The effective junction perimeter on the source side is calculated by If (PS is given) if (permod == 0) P seff = PS else P seff = PS W effcj NF Else P seff computed from NF, DWJ, geomod, DMCG, DMCI, DMDG, DMCGT, and MIN. The effective junction area on the source side is calculated by If (AS is given) A seff = AS Else A seff computed from NF, DWJ, geomod, DMCG, DMCI, DMDG, DMCGT, and MIN. In the above, P seff and A seff will be used to calculate junction diode I and C. P seff does not include the gate-edge perimeter. BSIM4.6.0 Manual Copyright 006 UC Berkeley 11-3

120 Model Formulation and Options 11.. Source/Drain Diffusion Resistance The source diffusion resistance is calculated by If (number of source squares NRS is given) R sdiff = NRS RSH Else if (rgeomod == 0) Source diffusion resistance R sdiff is not generated. Else R sdiff computed from NF, DWJ, geomod, DMCG, DMCI, DMDG, DMCGT, RSH, and MIN. where the number of source squares NRS is an instance parameter. Similarly, the drain diffusion resistance is calculated by If (number of source squares NRD is given) = NRD RSH R ddiff Else if (rgeomod == 0) Drain diffusion resistance R ddiff is not generated. Else R ddiff computed from NF, DWJ, geomod, DMCG, DMCI, DMDG, DMCGT, RSH, and MIN Gate Electrode Resistance The gate electrode resistance with multi-finger configuration is modeled by Rgeltd RSHG NGCON W ( XGW + effcj ) 3 NGCON = ( L XGL) NF drawn (11..1) BSIM4.6.0 Manual Copyright 006 UC Berkeley 11-4

121 Model Formulation and Options Option for Source/Drain Connections Table 11-1 lists the options for source/drain connections through the model selector geomod. geomod End source End drain Note 0 isolated isolated NF=Odd 1 isolated shared NF=Odd, Even shared isolated NF=Odd, Even 3 shared shared NF=Odd, Even 4 isolated merged NF=Odd 5 shared merged NF=Odd, Even 6 merged isolated NF=Odd 7 merged shared NF=Odd, Even 8 merged merged NF=Odd 9 sha/iso shared NF=Even 10 shared sha/iso NF=Even Table geomod options. For multi-finger devices, all inside S/D diffusions are assumed shared Option for Source/Drain Contacts Talbe 11- lists the options for source/drain contacts through the model selector rgeomod. BSIM4.6.0 Manual Copyright 006 UC Berkeley 11-5

122 Model Formulation and Options rgeomod End-source contact End-drain contact 0 No R sdiff No R ddiff 1 wide wide wide point 3 point wide 4 point point 5 wide merged 6 point merged 7 merged wide 8 merged point Table 11-. rgeomod options. BSIM4.6.0 Manual Copyright 006 UC Berkeley 11-6

123 Chapter 1: Temperature Dependence Model Accurate modeling of the temperature effects on MOSFET characteristics is important to predict circuit behavior over a range of operating temperatures (T). The operating temperature might be different from the nominal temperature (TNOM) at which the BSIM4 model parameters are extracted. This chapter presents the BSIM4 temperature dependence models for threshold voltage, mobility, saturation velocity, source/drain resistance, and junction diode I and C. 1.1 Temperature Dependence of Threshold oltage The temperature dependence of th is modeled by th KT1L L (1.1.1) T TNOM ( T ) = ( TNOM ) + KT1+ + KT 1 th eff bseff fb T 1 TNOM ( T ) = ( TNOM ) KT 1 fb (1.1.) OFF ( T ) = OFF ( TNOM ) [ 1 + TOFF ( T TNOM )] (1.1.3) BSIM4.6.0 Manual Copyright 006 UC Berkeley 1-1

124 Temperature Dependence of Mobility FBSDOFF ( T ) = FBSDOFF ( TNOM ) [ 1 + TFBSDOFF ( T TNOM )] (1.1.4) 1. Temperature Dependence of Mobility The BSIM4 mobility model parameters have the following temperature dependences depending on the model selected through TEMPMOD. If TEMPMOD = 0, (1..1) U 0 ( T ) = U 0( TNOM ) ( T TNOM ) UTE UA T ( ) = UA( TNOM ) + UA1 ( T TNOM 1) (1..) UB T ( ) = UB( TNOM ) + UB1 ( T TNOM 1) (1..3) UC T ( ) = UC( TNOM ) + UC1 ( T TNOM 1) (1..4) and UD T ( ) = UD( TNOM ) + UD1 ( T TNOM 1) (1..5) 1- BSIM4.6.0 Manual Copyright 006 UC Berkeley

125 Temperature Dependence of Saturation elocity If TEMPMOD = 1, (1..6) U 0 ( T ) = U 0( TNOM ) ( T TNOM ) UTE UA ( T ) = UA( TNOM )[ 1+ UA1 ( T TNOM )] (1..7) UB ( T ) = UB( TNOM )[ 1+ UB1 ( T TNOM )] (1..8) UC ( T ) = UC( TNOM )[ 1+ UC1 ( T TNOM )] (1..9) and UD ( T ) = UD( TNOM) [ 1+ UD1 ( T TNOM)] (1..10) 1.3 Temperature Dependence of Saturation elocity If TEMPMOD = 0, the temperature dependence of SAT is modeled by BSIM4.6.0 Manual Copyright 006 UC Berkeley 1-3

126 Temperature Dependence of LDD Resistance SAT ( T ) = SAT ( TNOM ) AT ( T TNOM 1) (1.3.1) If TEMPMOD = 1, the temperature dependence of SAT is modeled by SAT ( T ) = SAT( TNOM )[ 1 AT ( T TNOM )] (1.3.) 1.4 Temperature Dependence of LDD Resistance If TEMPMOD = 0, rdsmod = 0 (internal source/drain LDD resistance) (1.4.1) RDSW T ( ) = RDSW ( TNOM ) + PRT ( T TNOM 1) RDSWMIN (1.4.) ( T ) = RDSWMIN ( TNOM ) + PRT ( T TNOM 1) rdsmod = 1 (external source/drain LDD resistance) (1.4.3) RDW T ( ) = RDW ( TNOM ) + PRT ( T TNOM 1) RDWMIN (1.4.4) ( T ) = RDWMIN ( TNOM ) + PRT ( T TNOM 1) 1-4 BSIM4.6.0 Manual Copyright 006 UC Berkeley

127 Temperature Dependence of LDD Resistance RSW T ( ) = RSW ( TNOM ) + PRT ( T TNOM 1) (1.4.5) and RSWMIN (1.4.6) ( T ) = RSWMIN ( TNOM ) + PRT ( T TNOM 1) If TEMPMOD = 1, rdsmod = 0 (internal source/drain LDD resistance) (1.4.7) RDSW ( T ) = RDSW( TNOM )[ 1+ PRT ( T TNOM )] RDSWMIN (1.4.8) ( T ) = RDSWMIN( TNOM )[ 1+ PRT ( T TNOM )] rdsmod = 1 (external source/drain LDD resistance) (1.4.9) RDW ( T ) = RDW( TNOM )[ 1+ PRT ( T TNOM )] RDWMIN (1.4.10) ( T ) = RDWMIN( TNOM )[ 1+ PRT ( T TNOM )] RSW ( T ) = RSW( TNOM )[ 1+ PRT ( T TNOM )] (1.4.11) BSIM4.6.0 Manual Copyright 006 UC Berkeley 1-5

128 Temperature Dependence of Junction Diode I and (1.4.1) RSWMIN ( T ) = RSWMIN( TNOM )[ 1+ PRT ( T TNOM )] 1.5 Temperature Dependence of Junction Diode I Source-side diode The source-side saturation current is given by I sbs = A seff J ss ( T ) + P J ( T ) + W NF J ( T ) seff ssws effcj sswgs (1.5.1) where J ss ( T ) = JSS( TNOM ) E vt exp ( TNOM ) ( TNOM ) g E v t ( T ) ( T ) g (1.5.) + XTIS ln NJS T TNOM J ssws ( T ) = JSSWS ( TNOM ) E vt exp ( TNOM ) ( TNOM ) g E v ( T ) ( T ) g t (1.5.3) + XTIS ln NJS T TNOM and 1-6 BSIM4.6.0 Manual Copyright 006 UC Berkeley

129 Temperature Dependence of Junction Diode I J sswgs ( T ) = JSSWGS ( TNOM ) E k exp g b ( TNOM ) E ( T ) TNOM k g b (1.5.4) + XTIS ln T NJS T TNOM where E g is given in Section 1.7. Drain-side diode The drain-side saturation current is given by I sbd = A deff J sd (1.5.5) ( T ) + P J ( T ) + W NF J ( T ) deff sswd effcj sswgd where J sd ( T ) = JSD( TNOM ) E k exp g b ( TNOM ) E ( T ) TNOM k g b + XTID ln T NJD (1.5.6) T TNOM J sswd ( T ) = JSSWD( TNOM ) E k exp g b ( TNOM ) E ( T ) TNOM k g b (1.5.7) + XTID ln T NJD T TNOM and BSIM4.6.0 Manual Copyright 006 UC Berkeley 1-7

130 Temperature Dependence of Junction Diode I J sswgd ( T ) = JSSWGD( TNOM ) E k exp g b ( TNOM ) E ( T ) TNOM k g b (1.5.8) + XTID ln T NJD T TNOM trap-assisted tunneling and recombination current (1.5.9) Eg( TNOM) J tsswgs( T) = Jtsswgs( TNOM) exp X tsswgs 1 kbt J ( T ) = J Eg( TNOM ) ( TNOM ) exp X kbt tssws tssws tssws 1 T TNOM (1.5.10) T TNOM (1.5.11) J ( T ) = J Eg ( TNOM ( TNOM ) exp k BT ) X tss tss tss 1 T TNOM J ( T) = J Eg( TNOM) ( TNOM) exp X kbt tsswgd tsswgd tsswgd 1 (1.5.1) T TNOM (1.5.13) Eg( TNOM ) J tsswd ( T ) = J tsswd ( TNOM ) exp X tsswd 1 k BT T TNOM BSIM4.6.0 Manual Copyright 006 UC Berkeley 1-8

131 Temperature Dependence of Junction Diode I (1.5.14) Eg( TNOM ) T J tsd ( T ) = J tsd ( TNOM ) exp X tsd 1 k BT TNOM (1.5.15) T NJTSSWG( T) = NJTSSWG( TNOM) 1 + TNJTSSWG 1 TNOM (1.5.16) T NJTSSW ( T ) = NJTSSW ( TNOM ) 1 + TNJTSSW 1 TNOM (1.5.17) T NJTS ( T ) = NJTS ( TNOM ) 1 + TNTJS 1 TNOM (1.5.18) T NJTSSWGD( T) = NJTSSWGD( TNOM) 1 + TNJTSSWGD 1 TNOM (1.5.19) T NJTSSWD( T) = NJTSSWD( TNOM) 1 + TNJTSSWD 1 TNOM (1.5.0) T NJTSD( T ) = NJTSD( TNOM ) 1 + TNTJSD 1 TNOM BSIM4.6.0 Manual Copyright 006 UC Berkeley 1-9

132 Temperature Dependence of Junction Diode C 1.6 Temperature Dependence of Junction Diode C Source-side diode The temperature dependences of zero-bias unit-length/area junction capacitances on the source side are modeled by CJS ( T ) = CJS ( TNOM ) + TCJ ( T TNOM ) (1.6.1) CJSWS (1.6.) ( T ) = CJSWS ( TNOM ) + TCJSW ( T TNOM ) and (1.6.3) CJSWGS ( T ) = CJSWGS( TNOM ) [ 1+ TCJSWG ( T TNOM )] The temperature dependences of the built-in potentials on the source side are modeled by (1.6.4) PBS ( T ) = PBS( TNOM ) TPB ( T TNOM ) PBSWS (1.6.5) ( T ) = PBSWS ( TNOM ) TPBSW ( T TNOM ) and BSIM4.6.0 Manual Copyright 006 UC Berkeley 1-10

133 Temperature Dependence of Junction Diode C PBSWGS (1.6.6) ( T ) = PBSWGS( TNOM ) TPBSWG ( T TNOM ) Drain-side diode The temperature dependences of zero-bias unit-length/area junction capacitances on the drain side are modeled by CJD ( T ) = CJD( TNOM ) [ 1+ TCJ ( T TNOM )] (1.6.7) CJSWD (1.6.8) ( T ) = CJSWD( TNOM ) + TCJSW ( T TNOM ) and (1.6.9) CJSWGD ( T ) = CJSWGD( TNOM ) [ 1+ TCJSWG ( T TNOM )] The temperature dependences of the built-in potentials on the drain side are modeled by (1.6.10) PBD ( T ) = PBD( TNOM ) TPB ( T TNOM ) PBSWD (1.6.11) ( T ) = PBSWD( TNOM ) TPBSW ( T TNOM ) and BSIM4.6.0 Manual Copyright 006 UC Berkeley 1-11

134 Temperature Dependences of Eg and ni PBSWGD (1.6.1) ( T ) = PBSWGD( TNOM ) TPBSWG ( T TNOM ) 1.7 Temperature Dependences of E g and n i Energy-band gap of Si (E g ) The temperature dependence of E g is modeled by E g ( TNOM ) TNOM = 1.16 TNOM (1.7.1) and (1.7.) E g ( T ) T = 1.16 T Intrinsic carrier concentration of Si (n i ) The temperature dependence of n i is modeled by (1.7.3) n i TNOM = 1.45e TNOM ( TNOM ) qeg exp kbt BSIM4.6.0 Manual Copyright 006 UC Berkeley 1-1

135 Chapter 13: Stress Effect Model CMOS feature size aggressively scaling makes shallow trench isolation(sti) very popular active area isolatiohn process in advanced technologies. Recent years, strain channel materials have been employed to achieve high device performance. The mechanical stress effect induced by these process causes MOSFET performance function of the active area size(od: oxide definition) and the location of the device in the active area. And the necessity of new models to describe the layout dependence of MOS parameters due to stress effect becomes very urgent in advance CMOS technologies. Influence of stress on mobility has been well known since the 0.13um technology. The stress influence on saturation velocity is also experimentally demonstrated. Stress-induced enhancement or suppression of dopant diffusion during the processing is reported. Since the doping profile may be changed due to different STI sizes and stress, the threshold voltage shift and changes of other second-order effects, such as DIBL and body effect, were shown in process integration. BSIM4 considers the influence of stress on mobility, velocity saturation, threshold voltage, body effect, and DIBL effect. BSIM4.6.0 Manual Copyright 006 UC Berkeley 13-1

136 Stress Effect Model Development 13.1Stress Effect Model Development Experimental analysis show that there exist at least two different mechanisms within the influence of stress effect on device characteristics. The first one is mobilityrelated and is induced by the band structure modification. The second one is threlated as a result of doping profile variation. Both of them follow the same 1/LOD trend but reveal different L and W scaling. We have derived a phenomenological model based on these findings by modifying some parameters in the BSIM model. Note that the following equations have no impact on the iteration time because there are no voltage-controlled components in them Mobility-related Equations This model introduces the first mechanism by adjusting the U0 and sat according to different W, L and OD shapes. Define mobility relative change due to stress effect as : (13.1.1) r m eff = m eff / m effo = ( m eff m effo ) / m effo = m m eff effo 1 So, (13.1.) m m eff effo = 1 + r m eff Figure(13.1) shows the typical layout of a MOSFET on active layout surrounded by STI isolation. SA, SB are the distances between isolation edge to Poly from one and 13- BSIM4.6.0 Manual Copyright 006 UC Berkeley

137 Stress Effect Model Development the other side, respectively. D simulation shows that stress distribution can be expressed by a simple function of SA and SB. Trench isolation edge SA L SB W LOD SA + SB + L LOD = OD: gate Oxide Definition Fig. (13.1) shows the typical layout of a MOSFET Fig. (13.) Stress distribution within MOSFET channel using D simulation BSIM4.6.0 Manual Copyright 006 UC Berkeley 13-3

138 Stress Effect Model Development Assuming that mobility relative change is propotional to stress distribution. It can be described as function of SA, SB(LOD effect), L, W, and T dependence: KU0 Kstress _u0 ( Inv _ sa Inv _ sb) r = + m eff (13.1.3) Where: 1 Inv _ sa = SA L drawn 1 Inv _ sb = SB L drawn LKU0 WKU0 Kstress _u0 = 1+ + LLODKU0 WLODKU0 ( Ldrawn + XL ) (Wdrawn + XW + WLOD ) + PKU0 Temperature 1+ TKU TNOM 1 LLODKU0 WLODKU0 ( Ldrawn XL ) (Wdrawn XW WLOD ) So that: (13.1.4) m eff 1+ r = 1 + r meff meff ( SA,SB ) ( SA ref,sb ref m ) effo (13.1.5) u sattemp 1+ KSAT r = 1+ KSAT r meff meff ( SA,SB ) ( SA ref,sb ref u ) sattempo Where µ effo, u sato are low field mobility, saturation velocity at SA ref, SB ref and SAref, SBref are reference distances between OD edge to poly from one and the other side. BSIM4.6.0 Manual Copyright 006 UC Berkeley 13-4

139 Stress Effect Model Development 13.1.th-related Equations th0, K and ETA0 are modified to cover the doping profile change in the devices with different LOD. They use the same 1/LOD formulas as shown in section(13.1.1), but different equations for W and L scaling: TH0 = TH0 K = K original ETA0 = ETA0 original original KTH0 + Kstress_vth0 STK + Kstress_vth0 LODK STETA0 + Kstress_vth0 ( Inv _ sa + Inv _ sb Inv _ sa Inv _ sb ) ( Inv _ sa + Inv _ sb Inv _ sa Inv _ sb ) LODETA0 ref ref (13.1.6) (13.1.7) ( Inv _ sa + Inv _ sb Inv _ sa Inv _ sb ) (13.1.8) ref ref ref ref Where: Inv _ sa ref = SA ref L drawn Inv _ sb ref = SB ref L drawn Kstress _ vth0 = 1+ ( L + ( L drawn drawn LKTH0 + XL ) + XL ) LLODKTH LLODKTH + (W PKTH0 (W drawn drawn WKTH0 + XW + WLOD + XW + WLOD ) ) WLODKTH WLODKTH Multiple Finger Device For multiple finger device, the total LOD effect is the average of LOD effect to every finger. That is(see Fig.(13.3) for the layout for multiple finger device): BSIM4.6.0 Manual Copyright 006 UC Berkeley 13-5

140 Effective SA and SB for Irregular LOD Inv _ sa = Inv _ sb = 1 NF 1 NF NF 1 i= 0 NF 1 i= 0 SA L SB L drawn drawn 1 + i ( SD + L 1 + i ( SD + L drawn drawn ) ) Trench isolation edge L SA SB W LOD SD Fig. (13.3) Layout of multiple finger MOSFET 13. Effective SA and SB for Irregular LOD General MOSFET has an irregular shape of active area shown in Fig.(13.4). To fully describe the shape of OD region will require additional instance parameters. However, this will result in too many parameters in the net lists and would massively increase the read-in time and degrade the readability of parameters. One way to overcome this difficulty is the concept of effective SA and SB similar to ref. [16]. BSIM4.6.0 Manual Copyright 006 UC Berkeley 13-6

141 Effective SA and SB for Irregular LOD Stress effect model described in Section(13.1) allows an accurate and efficient layout extraction of effective SA and SB while keeping fully compatibility of the LOD model. They are expressed as: SA SB eff eff L L drawn drawn = = n i= 1 n i= 1 sw W i drawn sw W i drawn sa i sb i L L drawn drawn (13..1) (13..) Fig.(13.4) A typical layout of MOS devices with more instance parameters (swi, sai and sbi) in addition to the traditional L and W BSIM4.6.0 Manual Copyright 006 UC Berkeley 13-7