BSIM4.6.4 MOSFET Model

Transcription

1 BSIM4.6.4 MOSFET Model -User s Manual Tanvir Hasan Morshed, Wenwei (Morgan) Yang, Mohan V. Dunga, Xuemei (Jane) Xi, Jin He, Weidong Liu, Kanyu, M. Cao, Xiaodong Jin, Jeff J. Ou, Mansun Chan, Ali M. Niknejad, Chenming Hu Department of Electrical Engineering and Computer Sciences University of California, Berkeley, CA 9470 BSIM4.6.4 Manual Copyright 009 UC Berkeley

2 Developers: BSIM4.6.4 Developers: Professor Chenming Hu (project director), UC Berkeley Professor Ali M. Niknejad(project director), UC Berkeley Wenwei Yang, UC Berkeley Darsen Lu, UC Berkeley Developers of BSIM4 Previous Versions: Dr. Weidong Liu, Synopsys Dr. Xiaodong Jin, Marvell Dr. Kanyu (Mark) Cao, UC Berkeley Dr. Jeff J. Ou, Intel Dr. Jin He, UC Berkeley Dr. Xuemei (Jane) Xi, UC Berkeley Mohan V. Dunga, UC Berkeley Professor Ali M. Niknejad, UC Berkeley Professor Chenming Hu, UC Berkeley Web Sites: BSIM4 web site with BSIM source code and documents: Compact Model Council: Technical Support: Tanvir Hasan Morshed: BSIM4.6.4 Manual Copyright 009 UC Berkeley

3 Acknowledgement: The development of BSIM4.6.4 benefited from the input of many BSIM users, especially the Compact Model Council (CMC) member companies. The developers would like to thank Xingming Liu and Jushan Xie at Cadence, Joddy Wang, Robin Tan, Jane Xi and Weidong Liu at Synopsys, Ben Gu at Freescale, James Ma at ProPlus Design, Joe Watts at IBM, Geoffrey Coram at Analog Device, Wei-hung Chen at UC Berkeley, for their valuable assistance in identifying the desirable modifications and testing of the new model. The BSIM project is partially supported by SRC and CMC. BSIM4.6.4 Manual Copyright 009 UC Berkeley

4 Contents Chapter 1: Effective Oxide Thickness, Channel Length and Channel Width Gate Dielectric Model Poly-Silicon Gate Depletion Effective Channel Length and Width... 7 Chapter : Threshold Voltage Model Long-Channel Model With Uniform Doping Non-Uniform Vertical Doping Non-Uniform Lateral Doping: Pocket (Halo) Implant Short-Channel and DIBL Effects Narrow-Width Effect Chapter 3: Channel Charge and Subthreshold Swing Models Channel Charge Model Subthreshold Swing n... Chapter 4: Gate Direct Tunneling Current Model Model Selectors Voltage Across Oxide V ox Equations for Tunneling Currents Gate-to-Substrate Current (I gb = I gbacc + I gbinv ) Gate-to-Channel Current (I gc0 ) and Gate-to-S/D (I gs and I gd ) Partition of I gc... 8 Chapter 5: Drain Current Model Bulk Charge Effect Unified Mobility Model Asymmetric and Bias-Dependent Source/ Drain Resistance Model Drain Current for Triode Region Velocity Saturation Saturation Voltage V dsat Intrinsic case Extrinsic Case BSIM4.6.4 Manual Copyright 009 UC Berkeley

5 5.6.3V dseff Formulation Saturation-Region Output Conductance Model Channel Length Modulation (CLM) Drain-Induced Barrier Lowering (DIBL) Substrate Current Induced Body Effect (SCBE) Drain-Induced Threshold Shift (DITS) by Pocket Implant Single-Equation Channel Current Model New Current Saturation Mechanisms: Velocity Overshoot and Source End Velocity Limit Model Velocity Overshoot Source End Velocity Limit Model Chapter 6: Body Current Models I ii Model I GIDL and I GISL Model Chapter 7: Capacitance Model General Description Methodology for Intrinsic Capacitance Modeling Basic Formulation Short Channel Model Single Equation Formulation Charge partitioning Charge-Thickness Capacitance Model (CTM) Intrinsic Capacitance Model Equations capmod = capmod = capmod = Fringing/Overlap Capacitance Models Fringing capacitance model Overlap capacitance model Chapter 8: New Material Models Model Selector BSIM4.6.4 Manual Copyright 009 UC Berkeley

6 8. Non-Silicon Channel Non-SiO Gate insulator Non-Poly Silicon Gate Dielectric... 7 Chapter 9: High-Speed/RF Models Charge-Deficit Non-Quasi-Static (NQS) Model Transient Model AC Model Gate Electrode Electrode and Intrinsic-Input Resistance (IIR) Model General Description Model Option and Schematic Substrate Resistance Network General Description Model Selector and Topology Chapter 10: Noise Modeling Flicker Noise Models General Description Equations Channel Thermal Noise Other Noise Sources Modeled Chapter 11: Asymmetric MOS Junction Diode Models Junction Diode IV Model Source/Body Junction Diode Drain/Body Junction Diode Total Junction Source/Drain Diode Including Tunneling Junction Diode CV Model Source/Body Junction Diode Drain/Body Junction Diode Chapter 1: Layout-Dependent Parasitics Models Geometry Definition Model Formulation and Options Effective Junction Perimeter and Area BSIM4.6.4 Manual Copyright 009 UC Berkeley

7 1.. Source/Drain Diffusion Resistance Gate Electrode Resistance Option for Source/Drain Connections Option for Source/Drain Contacts Chapter 13: Temperature Dependence Model Temperature Dependence of Threshold Temperature Dependence of Mobility Temperature Dependence of Saturation Velocity Temperature Dependence of LDD Temperature Dependence of Junction Temperature Dependence of Junction Diode CV Temperature Dependences of E g and n i Chapter 14: Stress Effect Model Stress Effect Model Development Mobility-related Equations Vth-related Equations Multiple Finger Device Effective SA and SB for Irregular LOD Chapter 15: Well Proximity Effect Model Well Proximity Effect Model Chapter 16: Parameter Extraction Methodology Optimization strategy Extraction Strategy Extraction Procedure Extraction Requirements Optimization Extraction Routine Appendix A: Complete Parameter List A.1 BSIM4.6.1 Model Selectors/Controller A. Process Parameters A.3 Basic Model Parameters BSIM4.6.4 Manual Copyright 009 UC Berkeley

8 A.4 Parameters for Asymmetric and Bias-Dependent R ds Model A.5 Impact Ionization Current Model Parameters A.6 Gate-Induced Drain Leakage Model Parameters A.7 Gate Dielectric Tunneling Current Model Parameters A.8 Charge and Capacitance Model Parameters A.9 High-Speed/RF Model Parameters A.10 Flicker and Thermal Noise Model Parameters A.11 Layout-Dependent Parasitic Model Parameters A.1 Asymmetric Source/Drain Junction Diode Model Parameters A.13 Temperature Dependence Parameters A.14 Stress Effect Model Parameters A.15 Well-Proximity Effect Model Parameters A.16 dw and dl Parameters A.17 Range Parameters for Model Application A.18 Notes Appendix B: Core Parameters Appendix C: References BSIM4.6.4 Manual Copyright 009 UC Berkeley

9 Effective Oxide Thickness, Channel Length and Channel Width Chapter 1: Effective Oxide Thickness, Channel Length and Channel Width BSIM4, as the extension of BSIM3 model, addresses the MOSFET physical effects into sub-100nm regime. The continuous scaling of minimum feature size brought challenges to compact modeling in two ways: One is that to push the barriers in making transistors with shorter gate length, advanced process technologies are used such as non-uniform substrate doping. The second is its opportunities to RF applications. To meet these challenges, BSIM4 has the following major improvements and additions over BSIM3v3: (1) an accurate new model of the intrinsic input resistance for both RF, high-frequency analog and high-speed digital applications; () flexible substrate resistance network for RF modeling; (3) a new accurate channel thermal noise model and a noise partition model for the induced gate noise; (4) a non-quasi-static (NQS) model that is consistent with the Rg-based RF model and a consistent AC model that accounts for the NQS effect in both transconductances and capacitances. (5) an accurate gate direct tunneling model for multiple layer gate dielectrics; (6) a comprehensive and versatile geometry-dependent parasitics model for various source/drain connections and multi-finger devices; (7) improved model for steep vertical retrograde doping profiles; (8) better model for pocket-implanted devices in V th, bulk charge effect model, and Rout; (9) asymmetrical and bias-dependent source/drain resistance, either internal or external to the intrinsic MOSFET at the user's discretion; (10) acceptance of BSIM4.6.4 Manual Copyright 009 UC Berkeley 1

10 Effective Oxide Thickness, Channel Length and Channel Width anyone of the electrical, physical gate oxide thickness or equivalent oxide thickness as the model input at the user's choice in a physically accurate manner; (11) the quantum mechanical charge-layer-thickness model for both IV and CV; (1) a more accurate mobility model for predictive modeling; (13) a improved gate-induced drain/source leakage (GIDL/GISL) current model considering the work function difference between drain/source and gate; (14) an improved unified flicker (1/f) noise model, which is smooth over all bias regions and considers the bulk charge effect; (15) different diode IV and CV chrematistics for source and drain junctions; (16) junction diode breakdown with or without current limiting; (17) dielectric constant of the gate dielectric as a model parameter; (18) A new scalable stress effect model for process induced stress effect; device performance becoming thus a function of the active area geometry and the location of the device in the active area; (19) A unified current-saturation model that includes all mechanisms of current saturation- velocity saturation, velocity overshoot and source end velocity limit; (0) A new temperature model format that allows convenient prediction of temperature effects on saturation velocity, mobility, and S/D resistances; (1) A improved material model that is suitable to describe non-sio gate insulator, non-poly-si gate and non-si channel; () A new threshold voltage definition is introduced into C-V model to improve sub-threshold fitting; (3) an improved model predicts well the mobility behavior in high k/metal gate structure; (4) a width dependent trap-assistant tunneling model is introduced to describe the current density enhancement in narrow device. BSIM4.6.4 Manual Copyright 009 UC Berkeley

11 Effective Oxide Thickness, Channel Length and Channel Width 1.1 Gate Dielectric Model As the gate oxide thickness is vigorously scaled down, the finite chargelayer thickness can t be ignored [1]. BSIM4 models this effect in both IV and CV. For this purpose, BSM4 accepts two of the following methods as the model inputs: mrtlmod=0, the electrical gate oxide thickness TOXE 1, the physical gate oxide thickness TOXP, and their difference DTOX = TOXE TOXP are the input parameters. Based on these parameters, the effect of effective gate oxide capacitance C oxeff on IV and CV is modeled []. mrtlmod=1, for the high-k gate dielectric, the equivalent SiO thickness (EOT) is the input parameter. Based on EOT, TOXP could be calculated as following: 3.9 (1.1) TOXP = EOT X DC Vgs = VDDEOT, Vds = Vbs = 0 EPSRSUB In this case, TOXE is equal to EOT. It is worth pointing out that the new model parameters: the effective width (Weffeot), length (Leffeot), temperature (Tempeot) and bias condition (Vddeot) for EOT extraction are also needed in this calculation. Here, mrtlmod is a global selector which is used to turn on or off the new material models. This selector will be discussed in detail in Chapter 8. Figure 1.1 illustrates the algorithm and options for specifying the gate dielectric thickness and calculation of the gate dielectric capacitance for BSIM4 model evaluation. 1 Capital and italic alphanumericals in this manual are model parameters. BSIM4.6.4 Manual Copyright 009 UC Berkeley 3

12 Effective Oxide Thickness, Channel Length and Channel Width Figure 1.1 Algorithm for BSIM4 gate dielectric model. 1. Poly-Silicon Gate Depletion When a gate voltage is applied to the poly-silicon gate, e.g. NMOS with n + poly-silicon gate, a thin depletion layer will be formed at the interface between the poly-silicon and the gate oxide. Although this depletion layer is very thin due to the high doping concentration of the poly-silicon gate, its effect cannot be ignored since the gate oxide thickness is small. BSIM4.6.4 Manual Copyright 009 UC Berkeley 4

13 Effective Oxide Thickness, Channel Length and Channel Width Figure 1. shows an NMOSFET with a depletion region in the n + polysilicon gate. The doping concentration in the n + poly-silicon gate is NGATE and the doping concentration in the substrate is NSUB. The depletion width in the poly gate is X p. The depletion width in the substrate is X d. The positive charge near the interface of the poly-silicon gate and the gate oxide is distributed over a finite depletion region with thickness X p. In the presence of the depletion region, the voltage drop across the gate oxide and the substrate will be reduced, because part of the gate voltage will be dropped across the depletion region in the gate. That means the effective gate voltage will be reduced. NGATE Figure 1.. Charge distribution in a MOSFET with the poly gate depletion effect. The device is in the strong inversion region. The effective gate voltage can be calculated in the following manner. Assume the doping concentration in the poly gate is uniform. The voltage drop in the poly gate V poly can be calculated as qngate X Vpoly = 0.5X polyepoly = ε si poly (1.) BSIM4.6.4 Manual Copyright 009 UC Berkeley 5

14 Effective Oxide Thickness, Channel Length and Channel Width where E poly is the maximum electrical field in the poly gate. The boundary condition at the interface of poly gate and the gate oxide is EPSROX E ε E qε NGATE V = = (1.3) ox si poly si poly where E ox is the electric field in the gate oxide. The gate voltage satisfies Vgs VFB Φ s = Vpoly + Vox (1.4) where V ox is the voltage drop across the gate oxide and satisfies V ox = E ox TOXE. From (1.) and (1.3), we can obtain where ( ) gs FB s poly poly 0 av V Φ V V = (1.5) a = qε si EPSROX NGATE TOXE (1.6) By solving (1.5), we get the effective gate voltage V gse which is equal to V ( gs Φs ) qε singate TOXE EPSROX V VFB gse = VFB+Φ s EPSROX qε singate TOXE (1.7) The above discussion is only suitable when mrtlmod=0. Considering the non-silicon channel or high-k gate insulator, V gse is modified as follows: V gse ( gs Φs ) qε gatengate coxe V VFB = VFB+Φ s coxe qε gatengate (1.8) Note: Here ε si = EPSRGATE EPS0. EPSRGATE =0 means the metal gate, and there is no depletion effect. BSIM4.6.4 Manual Copyright 009 UC Berkeley 6

15 Effective Oxide Thickness, Channel Length and Channel Width 1.3 Effective Channel Length and Width The effective channel length and width used in the drain current model are given below where XL and XW are parameters to account the channel length/width offset due to mask/etch effect L L XL dl eff = + (1.9) drawn Wdrawn (1.10) Weff = + XW dw NF Wdrawn (1.11) Weff ' = + XW dw' NF The difference between (1.10) and (1.11) is that the former includes bias dependencies. NF is the number of device fingers. dw and dl are modeled by ( ) dw = dw ' + DWG V + DWB Φ V Φ gsteff s bseff s WL WW WWL dw ' = WINT L W L W WLN WWN WLN WWN LL LW LWL dl = LINT L W L W LLN LWN LLN LWN (1.1) WINT represents the traditional manner from which "delta W" is extracted (from the intercept of straight lines on a 1/R ds ~W drawn plot). The parameters DWG and DWB are used to account for the contribution of both gate and substrate bias effects. For dl, LINT represents the traditional manner from which "delta L" is extracted from the intercept of lines on a R ds ~L drawn plot). The remaining terms in dw and dl are provided for the convenience of the user. They are meant to allow the user to model each parameter as a function of W drawn, L drawn and their product term. By default, the above geometrical dependencies for dw and dl are turned off. BSIM4.6.4 Manual Copyright 009 UC Berkeley 7

16 Effective Oxide Thickness, Channel Length and Channel Width MOSFET capacitances can be divided into intrinsic and extrinsic components. The intrinsic capacitance is associated with the region between the metallurgical source and drain junction, which is defined by the effective length (L active ) and width (W active ) when the gate to source/drain regions are under flat-band condition. L active and W active are defined as L = L + XL dl (1.13) active drawn Wdrawn Wactive = + XW dw NF LLC LWC LWLC dl = DLC L W L W LLN LWN LLN LWN WLC WWC WWLC dw = DWC L W L W WLN WWN WLN WWN (1.14) (1.15) (1.16) The meanings of DWC and DLC are different from those of WINT and LINT in the I-V model. Unlike the case of I-V, we assume that these dimensions are bias- dependent. The parameter δl eff is equal to the source/drain to gate overlap length plus the difference between drawn and actual POLY CD due to processing (gate patterning, etching and oxidation) on one side. The effective channel length L eff for the I-V model does not necessarily carry a physical meaning. It is just a parameter used in the I-V formulation. This L eff is therefore very sensitive to the I-V equations and also to the conduction characteristics of the LDD region relative to the channel region. A device with a large L eff and a small parasitic resistance can have a similar current drive as another with a smaller L eff but larger R ds. The L active parameter extracted from capacitance is a closer representation of the metallurgical junction length (physical length). Due to the graded source/drain junction profile, the source to drain length can have a very BSIM4.6.4 Manual Copyright 009 UC Berkeley 8

17 Effective Oxide Thickness, Channel Length and Channel Width strong bias dependence. We therefore define L active to be that measured at flat-band voltage between gate to source/drain. If DWC, DLC and the length/width dependence parameters (LLC, LWC, LWLC, WLC, WWC and WWLC) are not specified in technology files, BSIM4 assumes that the DC bias-independent L eff and W eff will be used for the capacitance models, and DWC, DLC, LLC, LWC, LWLC, WLC, WWC and WWLC will be set to the values of their DC counterparts. BSIM4 uses the effective source/drain diffusion width W effcj for modeling parasitics, such as source/drain resistance, gate electrode resistance, and gate-induced drain leakage (GIDL) current. W effcj is defined as Wdrawn WLC WWC WWLC W = + XW DWJ NF L W L W effcj WLN WWN WLN WWN (1.17) Note: Any compact model has its validation limitation, so does BSIM4. BSIM4 is its own valid designation limit which is larger than the warning limit, shown in following table. For users reference, the fatal limitation in BSIM4 is also shown. Parameter name Designed Limitation(m) Warning Limitation(m) Fatal Limitation(m) Leff 1e-8 1e-9 0 LeffCV 1e-8 1e-9 0 Weff 1e-7 1e-9 0 WeffCV 1e-7 1e-9 0 Toxe 5e-10 1e-10 0 Toxp 5e-10 1e-10 0 Toxm 5e-10 1e-10 0 BSIM4.6.4 Manual Copyright 009 UC Berkeley 9

18 Threshold Voltage Model Chapter : Threshold Voltage Model.1 Long-Channel Model With Uniform Doping Accurate modeling of threshold voltage V th is important for precise description of device electrical characteristics. V th for long and wide MOSFETs with uniform substrate doping is given by ( ) V = VFB+Φ + γ Φ V = VTH0 + γ Φ V Φ (.1) th s s bs s bs s where VFB is the flat band voltage, VTH0 is the threshold voltage of the long channel device at zero substrate bias, and γ is the body bias coefficient given by γ = qε sinsubstrate C where N substrate is the uniform substrate doping concentration. oxe (.) Equation (.1) assumes that the channel doping is constant and the channel length and width are large enough. Modifications have to be made when the substrate doping concentration is not constant and/or when the channel is short, or narrow. Consider process variation, a new instance parameter DELVTO is added to VTH0 as: If VTH0 is given, If VTH0 isn t given, VTH 0= VTH0+ DELVTO (.3) BSIM4.6.4 Manual Copyright 009 UC Berkeley 10

19 Threshold Voltage Model VFB = VFB + DELVTO VTH = VFB +Φ + γ Φ 0 s s (.4). Non-Uniform Vertical Doping The substrate doping profile is not uniform in the vertical direction and therefore γ in (.) is a function of both the depth from the interface and the substrate bias. If N substrate is defined to be the doping concentration (NDEP) at X dep0 (the depletion edge at V bs = 0), V th for non-uniform vertical doping is V = V qd + + K V qd V 0 1 th th, NDEP 1NDEP s bs s bs C ϕ ϕ oxe ε si where K1 NDEP is the body-bias coefficient for N substrate = NDEP, (.5) with a definition of ( ϕ ϕ ) Vth, NDEP = VTH0+ K1NDEP s Vbs (.6) s kt B NDEP ϕs = ln q ni (.7) where n i is the intrinsic carrier concentration in the channel region. The zero-th and 1st moments of the vertical doping profile in (.5) are given by (.8) and (.9), respectively, as Xdep 0 0 Xdep ( ( ) ) ( ( ) ) D = D + D = N x NDEP dx+ N x NDEP dx Xdep 0 0 X dep 0 Xdep ( ( ) ) ( ( ) ) D = D + D = N x NDEP xdx+ N x NDEP xdx X dep 0 (.8) (.9) By assuming the doping profile is a steep retrograde, it can be shown that D01 is approximately equal to -C 01 V bs and that D 10 dominates D 11 ; C 01 BSIM4.6.4 Manual Copyright 009 UC Berkeley 11

20 Threshold Voltage Model represents the profile of the retrograde. Combining (.5) through (.9), we obtain ( ) V = VTH0+ K1 Φ V Φ K V (.10) th s bs s bs where K = qc 01 / C oxe, and the surface potential is defined as where kt B NDEP Φ s = ln + PHIN q ni (.11) PHIN = qd10 ε si (.1) VTH0, K1, K, and PHIN are implemented as model parameters for model flexibility. Appendix A lists the model selectors and parameters. Detail information on the doping profile is often available for predictive modeling. Like BSIM3v3, BSIM4 allows K1 and K to be calculated based on such details as NSUB, XT, VBX, VBM, etc. (with the same meanings as in BSIM3v3): K = K = K Φ VBM (.13) 1 γ s ( γ1 γ)( Φs VBX Φs ) Φs ( Φs VBM Φ s ) + VBM (.14) where γ 1 and γ are the body bias coefficients when the substrate doping concentration are equal to NDEP and NSUB, respectively: γ = 1 γ = qε si C qε si C NDEP oxe NSUB oxe (.15) (.16) BSIM4.6.4 Manual Copyright 009 UC Berkeley 1

21 Threshold Voltage Model VBX is the body bias when the depletion width is equal to XT, and is determined by qndep XT ε si =Φ VBX s (.17).3 Non-Uniform Lateral Doping: Pocket (Halo) Implant In this case, the doping concentration near the source/drain junctions is higher than that in the middle of the channel. Therefore, as channel length becomes shorter, a V th roll-up will usually result since the effective channel doping concentration gets higher, which changes the body bias effect as well. To consider these effects, V th is written as ( ) LPEB V = VTH0+ K1 Φ V Φ 1+ K V Leff LPE0 + K Φs L eff th s bs s bs (.18) In addition, pocket implant can cause significant drain-induced threshold shift (DITS) in long-channel devices [3]: Vds / vt ( 1 e ) Leff 1 ds 0 ( 1 ) V ( DITS) = nv ln Leff + DVTP + e th t DVTP V (.19) For V ds of interest, the above equation is simplified and implemented as for tempmod = 1: Leff Vth ( DITS) = nvt ln DVTP V ds Leff + DVTP0 1+ e for tempmod = : 1 ( ) (.0) BSIM4.6.4 Manual Copyright 009 UC Berkeley 13

22 Threshold Voltage Model Leff Vth ( DITS) = nvt ln DVTP V ds Leff + DVTP0 1+ e 1 ( ) (.1) Note: when tempmod =, drain-induced threshold voltage shift (DITS) due to pocket implant has no temperature dependence, so nominal temperature (TNOM) is used as Eq.(3.). when tempmod=0 or 1, Eq.(3.1) is used. Leff Vth ( DITS) = nvtnom ln DVTP V ds Leff + DVTP0 1+ e 1 ( ) (.).4 Short-Channel and DIBL Effects As channel length becomes shorter, V th shows a greater dependence on channel length (SCE: short-channel effect) and drain bias (DIBL: drain induced barrier lowering). V th dependence on the body bias becomes weaker as channel length becomes shorter, because the body bias has weaker control of the depletion region. Based on the quasi D solution of the Poisson equation, V th change due to SCE and DIBL is modeled [4] (, ) θ ( ) ( ) V SCE DIBL = L V Φ + V th th eff bi s ds (.3) where V bi, known as the built-in voltage of the source/drain junctions, is given by V bi kt B NDEP NSD (.4) = ln q ni where NSD is the doping concentration of source/drain diffusions. The shortchannel effect coefficient θ th (L eff ) in (.3) has a strong dependence on the channel length given by BSIM4.6.4 Manual Copyright 009 UC Berkeley 14

23 Threshold Voltage Model 0.5 θ th ( Leff ) = L cosh 1 eff ( l ) t l t is referred to as the characteristic length and is given by (.5) l t = ε TOXE X si dep EPSROX η (.6) with the depletion width X dep equal to X dep = ( Φ V ) ε si s bs qndep (.7) X dep is larger near the drain due to the drain voltage. X dep /η average depletion width along the channel. represents the Note that in BSIM3v3 and [4], θ th (L eff ) is approximated with the form of θ th L Leff = + lt lt eff ( Leff ) exp exp (.8) which results in a phantom second V th roll-up when L eff becomes very small (e.g. L eff < LMIN). In BSIM4, the function form of (.5) is implemented with no approximation. To increase the model flexibility for different technologies, several parameters such as DVT0, DVT1, DVT, DSUB, ETA0, and ETAB are introduced, and SCE and DIBL are modeled separately. To model SCE, we use θ th ( SCE) 0.5 DVT 0 = cosh 1 1 Leff ( DVT l ) t ( SCE) θ ( SCE) ( V ) th th bi s (.9) V = Φ (.30) with l t changed to BSIM4.6.4 Manual Copyright 009 UC Berkeley 15

24 Threshold Voltage Model To model DIBL, we use ε TOXE X ( 1 ) si dep lt = + DVT Vbs EPSROX (.31) 0.5 θ th ( DIBL) = cosh 1 Leff ( DSUB l ) t 0 ( DIBL) θ ( DIBL) ( 0 ) th th bs ds (.3) V = ETA + ETAB V V (.33) and l t0 is calculated by with l t0 = ε TOXE X si EPSROX dep0 (.34) X dep 0 = ε si Φ s qndep (.35) DVT1 is basically equal to 1/ η. DVT and ETAB account for substrate bias effects on SCE and DIBL, respectively..5 Narrow-Width Effect The actual depletion region in the channel is always larger than what is usually assumed under the one-dimensional analysis due to the existence of fringing fields. This effect becomes very substantial as the channel width decreases and the depletion region underneath the fringing field becomes comparable to the "classical" depletion layer formed from the vertical field. The net result is an increase in V th. This increase can be modeled as π qndep X C W dep,max TOXE = 3π Φ W oxe eff eff s (.36) BSIM4.6.4 Manual Copyright 009 UC Berkeley 16

25 Threshold Voltage Model This formulation includes but is not limited to the inverse of channel width due to the fact that the overall narrow width effect is dependent on process (i.e. isolation technology). V th change is given by TOXE V ( Narrow width1) = ( K3+ K3B V ) Φ W ' + W 0 th bs s eff (.37) In addition, we must consider the narrow width effect for small channel lengths. To do this we introduce the following 0.5 DVT0W V ( Narrow width) = V Φ cosh 1 1 Leff Weff ' ( DVT W l ) tw ( ) th - bi s with l tw given by l ε TOXE X ( 1 DVTW V ) si dep tw = + EPSROX The complete V th model implemented in SPICE is bs (.38) (.39) ( ) LPEB V = VTH0+ K Φ V K1 Φ 1+ K V th 1ox s bseff s ox bseff Leff LPE0 TOXE + K 1+ 1 Φ + ( K3+ K3B V ) Φ + 1ox s bseff s Leff Weff ' W0 0.5 DVT 0W DVT 0 + cosh ' ( 1 Leff Weff ) 1 cosh ( 1 Leff ) 1 bi Φ DVT W l DVT tw l t ( V ) (.40) 0.5 Leff ETA0 + ETAB V L bseff Vds nv.ln t eff DVTP cosh ( DSUB l ) V DS Leff + DVTP + e t 0 ( ) ( ) where TOXE dependence is introduced in model parameters K1 and K to improve the scalability of V th model over TOXE as s BSIM4.6.4 Manual Copyright 009 UC Berkeley 17

26 Threshold Voltage Model TOXE K1 ox = K1 TOXM (.41) and TOXE Kox = K TOXM (.4) Note that all V bs terms are substituted with a V bseff expression as shown in (.43). This is needed in order to set a low bound for the body bias during simulations since unreasonable values can occur during SPICE iterations if this expression is not introduced. V = V ( V V δ ) + ( V V δ ) 4δ V bseff bc bs bc 1 bs bc 1 1 bc (.43) where δ 1 = 0.001V, and V bc is the maximum allowable V bs and found from dv th /dv bs = 0 to be V bc K1 = 0.9 Φs 4K (.44) For positive V bs, there is need to set an upper bound for the body bias as: ' ( ) V = Φ Φ V + Φ V + Φ ' bseff 0.95 s s bseff δ s bseff δ1 4 δ s (.45) BSIM4.6.4 Manual Copyright 009 UC Berkeley 18

27 Channel Charge and Substhreshold Swing Models Chapter 3: Channel Charge and Subthreshold Swing Models 3.1 Channel Charge Model The channel charge density in subthreshold for zero V ds is written as VOFFL Voff ' = VOFF + L eff (3.1) where VOFFL Voff ' = VOFF + L eff (3.) VOFFL is used to model the length dependence of V off on non-uniform channel doping profiles. In strong inversion region, the density is expressed by ( ) Q C V V = (3.3) chs0 oxe gse th A unified charge density model considering the charge layer thickness effect is derived for both subthreshold and inversion regions as Q C V = (3.4) ch0 oxeff gsteff where C oxeff is modeled by C oxeff C C ε = with C = C C X oxe cen si cen oxe + cen DC (3.5) BSIM4.6.4 Manual Copyright 009 UC Berkeley 19

28 Channel Charge and Substhreshold Swing Models and X DC is given as X DC 9 ADOS m = Vgsteff + 4( VTH0 VFB Φs ) 1+ TOXP 0.7 BDOS (3.6) Here, ADOS and BDOS are the parameters to describe the density of states in new materials and used to control the charge centroid. In the above equations, V gsteff the effective (V gse -V th ) used to describe the channel charge densities from subthreshold to strong inversion, is modeled by V gsteff where ( gse th ) m V V nvt ln 1 + exp nv t = ( 1 m )( Vgse Vth ) Voff ' Φ s m + ncoxe exp qndepε si nv t (3.7) m = arctan ( MINV ) (3.8) π MINV is introduced to improve the accuracy of G m, G m /I d and G m /I d in the moderate inversion region. To account for the drain bias effect, The y dependence has to be included in (3.4). Consider first the case of strong inversion ( ) ( ) = ( ) (3.9) Q y C V V A V y chs oxeff gse th bulk F VF(y) stands for the quasi-fermi potential at any given point y along the channel with respect to the source. (3.9) can also be written as ( ) = + ( ) (3.10) Q y Q Q y chs chs0 chs BSIM4.6.4 Manual Copyright 009 UC Berkeley 0

29 Channel Charge and Substhreshold Swing Models The term Q chs (y) = -C oxeff A bulk VF(y) is the incremental charge density introduced by the drain voltage at y. In subthreshold region, the channel charge density along the channel from source to drain can be written as ( ) chsubs ( ) exp AbulkVF y Q y = Qchsubs0 nvt (3.11) Taylor expansion of (3.11) yields the following (keeping the first two terms) ( ) AbulkVF y Qchsubs ( y) = Qchsubs0 1 nvt Similarly, (3.1) is transformed into (3.1) ( ) = + ( ) (3.13) Q y Q Q y chsubs chsubs0 chsubs where Q chsubs (y) is the incremental channel charge density induced by the drain voltage in the subthreshold region. It is written as t ( ) AbulkVF y Qchsubs ( y) = Qchsubs0 nv (3.14) To obtain a unified expression for the incremental channel charge density Q ch (y) induced by V ds, we assume Q ch (y) to be Qchs ( y) Qchsubs ( y) (3.15) Qch ( y) = Q ( y) + Q ( y) chs chsubs Substituting Q ch (y) of (3.13) and (3.14) into (3.15), we obtain V = ( ) ( y) F Qch y Qch 0 Vb (3.16) where V b = (V gsteff + nv t ) / A bulk. In the model implementation, n of V b is replaced by a typical constant value of. The expression for V b now becomes BSIM4.6.4 Manual Copyright 009 UC Berkeley 1

30 Channel Charge and Substhreshold Swing Models V b V = gsteff A + v bulk t (3.17) A unified expression for Q ch (y) from subthreshold to strong inversion regions is VF Qch ( y) = Coxeff Vgsteff 1 V ( y) b (3.18) 3. Subthreshold Swing n The drain current equation in the subthreshold region can be expressed as where I ds V Vgs Vth Voff ' ds = I0 1 exp exp vt nvt (3.19) I 0 W = µ L qε sindep v Φ s t (3.0) v t is the thermal voltage and equal to k B T/q. V off = VOFF + VOFFL / L eff is the offset voltage, which determines the channel current at V gs = 0. In (3.19), n is the subthreshold swing parameter. Experimental data shows that the subthreshold swing is a function of channel length and the interface state density. These two mechanisms are modeled by the following Cdep Cdsc Term + CIT n = 1+ NFACTOR + C C where Cdsc-Term, written as oxe 0.5 Cdsc Term = ( CDSC + CDSCD Vds + CDSCB Vbseff ) L cosh 1 1 oxe eff ( DVT l ) t (3.1) (3.) BSIM4.6.4 Manual Copyright 009 UC Berkeley

31 Channel Charge and Substhreshold Swing Models represents the coupling capacitance between drain/source to channel. Parameters CDSC, CDSCD and CDSCB are extracted. Parameter CIT is the capacitance due to interface states. From (3.1), it can be seen that subthreshold swing shares the same exponential dependence on channel length as the DIBL effect. Parameter NFACTOR is close to 1 and introduced to compensate for errors in the depletion width capacitance calculation. BSIM4.6.4 Manual Copyright 009 UC Berkeley 3

32 Gate Direct Tunneling Current Model Chapter 4: Gate Direct Tunneling Current Model As the gate oxide thickness is scaled down to 3nm and below, gate leakage current due to carrier direct tunneling becomes important. This tunneling happens between the gate and silicon beneath the gate oxide. To reduce the tunneling current, high-k dielectrics are being studied to replace gate oxide. In order to maintain a good interface with substrate, multi-layer dielectric stacks are being proposed. The BSIM4 gate tunneling model has been shown to work for multi-layer gate stacks as well. The tunneling carriers can be either electrons or holes, or both, either from the conduction band or valence band, depending on (the type of the gate and) the bias regime. In BSIM4, the gate tunneling current components include the tunneling current between gate and substrate (I gb ), and the current between gate and channel (I gc ), which is partitioned between the source and drain terminals by I gc = I gcs + I gcd. The third component happens between gate and source/drain diffusion regions (I gs and I gd ). Figure 4.1 shows the schematic gate tunneling current flows. BSIM4.6.4 Manual Copyright 009 UC Berkeley 4

33 Gate Direct Tunneling Current Model Figure 4.1. Shematic gate current components flowing between nmosfet terminals in version. 4.1 Model Selectors Two global selectors are provided to turn on or off the tunneling components. igcmod = 1, turns on I gc, I gs, and I gd ; igbmod = 1 turns on I gb. When the selectors are set to zero, no gate tunneling currents are modeled. When tempmod =, following V t (= kt/q) will be replaced by V tnom (=ktnom/q) 4. Voltage Across Oxide V ox The oxide voltage V ox is written as V ox = V oxacc + V oxdepinv with Voxacc = Vfbzb VFBeff (4.1) V = K Φ + V (4.) oxdepinv 1ox s gsteff (4.1) and (4.) are valid and continuous from accumulation through depletion to inversion. V fbzb is the flat-band voltage calculated from zero-bias V th by and V = V Φ K1 Φ (4.3) fbzb th zerovbs andvds s s ( ) ( ) V = V 0.5 V V V V V FBeff fbzb fbzb gb fbzb gb fbzb (4.4) BSIM4.6.4 Manual Copyright 009 UC Berkeley 5

34 Gate Direct Tunneling Current Model 4.3 Equations for Tunneling Currents Note: when tempmod =, nominal temperature (TNOM) is used to replace the operating temperature in following gate tunneling current equations. When tempmod=0, or 1, operating temperature is still used Gate-to-Substrate Current (I gb = I gbacc + I gbinv ) I gbacc, determined by ECB (Electron tunneling from Conduction Band), is significant in accumulation and given by I = W L A T V V gbacc eff eff oxratio gb aux ( ) ( ) exp B TOXE AIGBACC BIGBACC Voxacc 1+ CIGBACC V oxacc (4.5) where the physical constants A = 4.973e-7 A/V, B = e11 (g/fs ) 0.5, and V aux T oxratio NTOX TOXREF 1 = TOXE TOXE Vgb Vfbzb = NIGBACC vt log 1+ exp NIGBACC v t (4.6) (4.7) I gbinv, determined by EVB (Electron tunneling from Valence Band), is significant in inversion and given by I = W L A T V V gbinv eff eff oxratio gb aux ( oxdepinv ) ( oxdepinv ) exp B TOXE AIGBINV BIGBINV V 1+ CIGBINV V (4.8) where A = e-7 A/V, B = 9.8e11 (g/f-s ) 0.5, and BSIM4.6.4 Manual Copyright 009 UC Berkeley 6

35 Gate Direct Tunneling Current Model V aux V = NIGBINV vt log 1+ exp EIGBINV NIGBINV v t oxdepinv (4.9) 4.3. Gate-to-Channel Current (I gc0 ) and Gate-to-S/D (I gs and I gd ) I gc0, determined by ECB for NMOS and HVB (Hole tunneling from Valence Band) for PMOS at V ds =0, is formulated as Igc0 = W L A T V V eff eff oxratio gse aux ( oxdepinv ) ( oxdepinv ) exp BTOXE AIGC BIGCV 1+ CIGCV (4.10) where A = A/V for NMOS and A/V for PMOS, B = e11 (g/f-s ) 0.5 for NMOS and e1 (g/f-s ) 0.5 for PMOS, and for igcmod = 1: V for igcmod = : aux Vgse VTH0 = NIGC vt log 1+ exp NIGC v t (4.11) V aux Vgse VTH (4.1) = NIGC vt log 1+ exp NIGC v t I gs and I gd -- I gs represents the gate tunneling current between the gate and the source diffusion region, while I gd represents the gate tunneling current between the gate and the drain diffusion region. I gs and I gd are determined by ECB for NMOS and HVB for PMOS, respectively. I = W DLCIG A T V V and ' gs eff oxratioedge gs gs ' ' ( gs ) ( gs ) exp B TOXE POXEDGE AIGS BIGS V 1+ CIGS V (4.13) BSIM4.6.4 Manual Copyright 009 UC Berkeley 7

36 Gate Direct Tunneling Current Model I = W DLCIGD A T V V ' gd eff oxratioedge gd gd ' ' ( gd ) ( gd ) exp B TOXE POXEDGE AIGD BIGD V 1+ CIGD V (4.14) where A = A/V for NMOS and A/V for PMOS, B = e11 (g/f-s ) 0.5 for NMOS and e1 (g/f-s ) 0.5 for PMOS, and T oxratioedge NTOX TOXREF = TOXE POXEDGE ( ) V = V V + 1.0e 4 ' gs gs fbsd ( ) V = V V + 1.0e 4 ' gd gd fbsd 1 ( TOXE POXEDGE) (4.15) (4.16) (4.17) V fbsd is the flat-band voltage between gate and S/D diffusions calculated as If NGATE > 0.0 Else V fbsd = 0.0. V fbsd kt B NGATE = log + VFBSDOFF q NSD (4.18) Partition of I gc To consider the drain bias effect, I gc is split into two components, I gcs and I gcd, that is I gc = I gcs + I gcd, and ( PIGCD Vdseff ) PIGCD Vdseff + exp e 4 Igcs = Igc0 PIGCD V +.0e 4 dseff (4.19) and BSIM4.6.4 Manual Copyright 009 UC Berkeley 8

37 Gate Direct Tunneling Current Model ( PIGCD Vdseff ) ( PIGCD Vdseff ) exp + 1.0e 4 Igcd = Igc0 PIGCD V +.0e 4 dseff (4.0) where I gc0 is I gc at V ds =0. If the model parameter PIGCD is not specified, it is given by BTOXE Vdseff PIGCD = 1 V gsteff V gsteff (4.1) BSIM4.6.4 Manual Copyright 009 UC Berkeley 9

38 Drain Current Model Chapter 5: Drain Current Model 5.1 Bulk Charge Effect The depletion width will not be uniform along channel when a non-zero V ds is applied. This will cause V th to vary along the channel. This effect is called bulk charge effect. BSIM4 uses A bulk to model the bulk charge effect. Several model parameters are introduced to account for the channel length and width dependences and bias effects. A bulk is formulated by (5.1) A bulk A0 Leff L + XJ X 1 L 0 1 KETA V eff B + 1 AGS V gsteff + L Weff ' B1 eff + XJ X + dep eff dep = 1+ F doping bseff where the second term on the RHS is used to model the effect of nonuniform doping profiles 1+ F doping = + K K B Φ W ' W 0 LPEB Leff K1 ox TOXE ox 3 Φs V bseff eff + s (5.) Note that A bulk is close to unity if the channel length is small and increases as the channel length increases. 5. Unified Mobility Model mrtlmod=0 BSIM4.6.4 Manual Copyright 009 UC Berkeley 30

39 Drain Current Model A good mobility model is critical to the accuracy of a MOSFET model. The scattering mechanisms responsible for surface mobility basically include phonons, coulombic scattering, and surface roughness. For good quality interfaces, phonon scattering is generally the dominant scattering mechanism at room temperature. In general, mobility depends on many process parameters and bias conditions. For example, mobility depends on the gate oxide thickness, substrate doping concentration, threshold voltage, gate and substrate voltages, etc. [5] proposed an empirical unified formulation based on the concept of an effective field E eff which lumps many process parameters and bias conditions together. E eff is defined by E eff Q = B + Qn / (5.3) ε si The physical meaning of E eff can be interpreted as the average electric field experienced by the carriers in the inversion layer. The unified formulation of mobility is then given by µ 0 (5.4) µ eff = v 1 + ( Eeff / E0) For an NMOS transistor with n-type poly-silicon gate, (6.3) can be rewritten in a more useful form that explicitly relates E eff to the device parameters E eff Vgs + Vth (5.5) 6TOXE BSIM4 provides three different models of the effective mobility. The mobmod = 0 and 1 models are from BSIM3v3..; the new mobmod =, a universal mobility model, is more accurate and suitable for predictive modeling. BSIM4.6.4 Manual Copyright 009 UC Berkeley 31

40 Drain Current Model mobmod = 0 (5.6) µ eff U0 f( Leff ) = Vgsteff + Vth Vgsteff + Vth Vth TOXE 1+ ( UA+ UCV bseff ) + UB + UD TOXE TOXE Vgsteff + Vth mobmod = 1 (5.7) µ µ eff eff U0 f( Leff ) = Vgsteff + Vth Vgsteff + Vth Vth TOXE 1+ UA + UB ( 1+ UC Vbseff ) + UD TOXE TOXE Vgsteff + Vth mobmod = ( eff ) U0 f L = EU V gsteff + C0 ( VTHO VFB Φs ) Vth TOXE 1+ ( UA+ UC Vbseff ) + UD TOXE Vgsteff + Vth (5.8) where the constant C0 = for NMOS and.5 for PMOS. Leff f( Leff ) = 1 UP exp LP (5.9) mrtlmod=1 A new expression of the vertical field in channel is adopted: (5.10) BSIM4.6.4 Manual Copyright 009 UC Berkeley 3

41 Drain Current Model E eff Vgsteff + V th BSIM 4 type ( PHIG EASUB Eg /+ 0.45) 3.9 = EOT EPSRSUB Thus the mobility model is modified as following: mobmod=0 µ eff = U0 f( L ) th UA UC Vbseff Eeff UB Eeff UD V gsteff V th 1 + ( + ) + + mobmod=1 eff V EOT (5.11) µ eff = U0 f( L ) V EOT + UA E + UB E + UC V UD V gsteff + V + 1 ( eff eff )(1 bseff ) eff th th Note: There is no changes in mobmod= when mtrlmod=1. (5.1) BSIM4.6. introduces a new model to predict the mobility in high k/metal gate structure, in which Coulombic scattering is important. mobmod=3 µ eff = 1+ ( UA + UC. V ) bseff V gsteff U 0. f ( Leff ) ( VTH 0 V Φ ) + C0. 6. TOXE fb S EU [ + V / V ] UCS gsteff UD gsteff, Vth (5.13) Here, Vgsteff,Vth=Vgsteff(Vgse=Vth,Vds=Vbs=0). 5.3 Asymmetric and Bias-Dependent Source/ Drain Resistance Model BSIM4 models source/drain resistances in two components: biasindependent diffusion resistance (sheet resistance) and bias-dependent LDD resistance. Accurate modeling of the bias-dependent LDD resistances is BSIM4.6.4 Manual Copyright 009 UC Berkeley 33

42 Drain Current Model important for deep-submicron CMOS technologies. In BSIM3 models, the LDD source/drain resistance R ds (V) is modeled internally through the I-V equation and symmetry is assumed for the source and drain sides. BSIM4 keeps this option for the sake of simulation efficiency. In addition, BSIM4 allows the source LDD resistance R s (V) and the drain LDD resistance R d (V) to be external and asymmetric (i.e. R s (V) and R d (V) can be connected between the external and internal source and drain nodes, respectively; furthermore, R s (V) does not have to be equal to R d (V)). This feature makes accurate RF CMOS simulation possible. The internal R ds (V) option can be invoked by setting the model selector rdsmod = 0 (internal) and the external one for R s (V) and R d (V) by setting rdsmod = 1 (external). rdsmod = 0 (Internal R ds (V)) RDSWMIN + RDSW Rds ( V) = 1 W PRWB ( Φs Vbseff Φ s ) + 1 PRWG V + gsteff ( 1e6 effcj ) WR (5.14) rdsmod = 1 (External R d (V) and R s (V)) RDWMIN + RDW (5.15) WR Rd ( V) = 1 ( 1e6 Weffcj ) NF PRWB V bd + 1 PRWG ( Vgd V + fbsd ) RSWMIN + RSW (5.16) WR Rs ( V) = 1 ( 1e6 Weffcj ) NF PRWB V bs + 1 PRWG ( Vgs V + fbsd ) V fbsd is the calculated flat-band voltage between gate and source/drain as given in Section BSIM4.6.4 Manual Copyright 009 UC Berkeley 34

43 Drain Current Model The following figure shows the schematic of source/drain resistance connection for rdsmod = 1. The diffusion source/drain resistance R sdiff and R ddiff models are given in the chapter of layout-dependence models. 5.4 Drain Current for Triode Region R ds (V)=0 or rdsmod=1 ( intrinsic case ) Both drift and diffusion currents can be modeled by ( ) = ( ) µ ( ) I y WQ y y ds ch ne where µ ne (y) can be written as µ eff µ ne( y) = E 1+ E y sat dv F dy ( y) (5.17) (5.18) Substituting (6.17) in (6.16), we get ds ( ) I y = WQ VF ( y) µ eff dvf ( y) (5.19) V E b y dy + ch0 1 1 E sat BSIM4.6.4 Manual Copyright 009 UC Berkeley 35

44 Drain Current Model (6.18) is integrated from source to drain to get the expression for linear drain current. This expression is valid from the subthreshold regime to the strong inversion regime I ds0 V ds Wµ eff Qch0Vds 1 Vb = V ds L 1+ EsatL R ds (V) > 0 and rdsmod=0 ( Extrinsic case ) (5.0) The drain current in this case is expressed by I ds Ids0 = RdsI 1+ V ds0 ds (5.1) 5.5 Velocity Saturation Velocity saturation is modeled by [5] µ eff E v= 1+ EEsat E < E = VSAT E E sat sat (5.) where E sat corresponds to the critical electrical field at which the carrier velocity becomes saturated. In order to have a continuous velocity model at E = E sat, E sat must satisfy E sat VSAT = µ eff (5.3) BSIM4.6.4 Manual Copyright 009 UC Berkeley 36

45 Drain Current Model 5.6 Saturation Voltage V dsat Intrinsic case In this case, the LDD source/drain resistances are either zero or non zero but not modeled inside the intrinsic channel region. It is easy to obtain V dsat as [7] V dsat = E L( V + v ) sat gsteff t A E L+ V + v bulk sat gsteff t (5.4) 5.6. Extrinsic Case In this case, non-zero LDD source/drain resistance R ds (V) is modeled internally through the I-V equation and symetry is assumed for the source and drain sides. V dsat is obtained as [7] V dsat = a b b 4ac (5.5) where 1 a Abulk Weff VSATCoxeRds Abulk 1 (5.6) = + λ ( Vgsteff + vt ) 1+ Abulk EsatLeff b λ = 3Abulk ( Vgsteff vt ) WeffVSATCoxeR + + ds ( ) ( ) gsteff t sat eff gsteff t eff oxe ds (5.7) c= V + v E L + V + v W VSATC R (5.8) λ = A1V + A (5.9) gsteff λ is introduced to model the non-saturation effects which are found for PMOSFETs. BSIM4.6.4 Manual Copyright 009 UC Berkeley 37

46 Drain Current Model 5.6.3V dseff Formulation An effective V ds, V dseff, is used to ensure a smooth transition near V dsat from trode to saturation regions. V dseff is formulated as V = V 1 ( V V δ) + ( V V δ) + 4δ V dseff dsat dsat ds dsat ds dsat where δ (DELTA) is a model parameter. (5.30) 5.7 Saturation-Region Output Conductance Model A typical I-V curve and its output resistance are shown in Figure 6.1. Considering only the channel current, the I-V curve can be divided into two parts: the linear region in which the current increases quickly with the drain voltage and the saturation region in which the drain current has a weaker dependence on the drain voltage. The first order derivative reveals more detailed information about the physical mechanisms which are involved in the device operation. The output resistance curve can be divided into four regions with distinct R out ~V ds dependences. The first region is the triode (or linear) region in which carrier velocity is not saturated. The output resistance is very small because the drain current has a strong dependence on the drain voltage. The other three regions belong to the saturation region. As will be discussed later, there are several physical mechanisms which affect the output resistance in the saturation region: channel length modulation (CLM), drain-induced barrier lowering (DIBL), and the substrate current induced body effect (SCBE). These mechanisms all affect the output resistance in the saturation range, but each of them dominates in a specific region. It will be shown next that CLM dominates in the second region, DIBL in the third region, and SCBE in the fourth region. BSIM4.6.4 Manual Copyright 009 UC Berkeley 38

47 Drain Current Model Figure 5.1 General behavior of MOSFET output resistance. The channel current is a function of the gate and drain voltage. But the current depends on the drain voltage weakly in the saturation region. In the following, the Early voltage is introduced for the analysis of the output resistance in the saturation region: (, ) (, ) (, ) I V V I V V I V V dv Vds ds gs ds ds gs ds = dsat gs dsat + V d dsat Vd Vds 1 = Idsat ( Vgs, Vdsat ) 1+ dv V d dsat VA where the Early voltage V A is defined as V A (, ) Ids Vgs V ds = Idsat V d 1 (5.31) (5.3) BSIM4.6.4 Manual Copyright 009 UC Berkeley 39

48 Drain Current Model We assume in the following analysis that the contributions to the Early voltage from all mechanisms are independent and can be calculated separately Channel Length Modulation (CLM) If channel length modulation is the only physical mechanism to be taken into account, the Early voltage can be calculated by V ACLM (, ) Ids Vgs Vds L = Idsat L V d 1 (5.33) Based on quasi two-dimensional analysis and through integration, we propose V ACLM to be where = ( ) (5.34) V C V V ACLM clm ds dsat 1 V gsteff Rds I dso V dsat 1 Cclm = F 1+ PVAG 1+ Leff + PCLM EsatL eff V dseff Esat litl (5.35) and the F factor to account for the impact of pocket implant technology is 1 F = 1+ FPROUT V gsteff L eff + v t (5.36) and litl in (6.34) is given by ε sitoxe XJ (5.37) litl = EPSROX PCLM is introduced into V ACLM to compensate for the error caused by XJ since the junction depth XJ cannot be determined very accurately Drain-Induced Barrier Lowering (DIBL) The Early voltage V ADIBLC due to DIBL is defined as BSIM4.6.4 Manual Copyright 009 UC Berkeley 40

49 V ADIBL Drain Current Model (, ) I V V V = Idsat Vth V ds gs ds th d 1 (5.38) V th has a linear dependence on V ds. As channel length decreases, V ADIBLC decreases very quickly (5.39) V ADIBL Vgsteff + v t AbulkV V dsat gsteff = 1 1+ PVAG θ ( 1 ) AbulkVdsat Vgsteff v rout + PDIBLCB V + + bseff t EsatL eff where θ rout has a similar dependence on the channel length as the DIBL effect in V th, but a separate set of parameters are used: θ PDIBLC1 = + PDIBLC cosh ( lt0 ) rout DROUT L eff (5.40) Parameters PDIBLC1, PDIBLC, PDIBLCB and DROUT are introduced to correct the DIBL effect in the strong inversion region. The reason why DVT0 is not equal to PDIBLC1 and DVT1 is not equal to DROUT is because the gate voltage modulates the DIBL effect. When the threshold voltage is determined, the gate voltage is equal to the threshold voltage. But in the saturation region where the output resistance is modeled, the gate voltage is much larger than the threshold voltage. Drain induced barrier lowering may not be the same at different gate bias. PDIBLC is usually very small. If PDIBLC is put into the threshold voltage model, it will not cause any significant change. However it is an important parameter in V ADIBLC for long channel devices, because PDIBLC will be dominant if the channel is long Substrate Current Induced Body Effect (SCBE) When the electrical field near the drain is very large (> 0.1MV/cm), some electrons coming from the source (in the case of NMOSFETs) will be BSIM4.6.4 Manual Copyright 009 UC Berkeley 41

50 Drain Current Model energetic (hot) enough to cause impact ionization. This will generate electron-hole pairs when these energetic electrons collide with silicon atoms. The substrate current I sub thus created during impact ionization will increase exponentially with the drain voltage. A well known I sub model [8] is A i Bi litl Isub = Ids ( Vds Vdsat )exp B V V i ds dsat (5.41) Parameters A i and B i are determined from measurement. I sub affects the drain current in two ways. The total drain current will change because it is the sum of the channel current as well as the substrate current. The total drain current can now be expressed as follows I = I + I = I + ds dsat ds ds w/ o Isub sub ds w/ o Isub 1 Bi B litl A exp i Vds Vdsat V V i ( ) (5.4) The Early voltage due to the substrate current V ASCBE can therefore be calculated by V ASCBE B i Bi litl (5.43) = exp Ai Vds Vdsat We can see that V ASCBE is a strong function of V ds. In addition, we also observe that V ASCBE is small only when V ds is large. This is why SCBE is important for devices with high drain voltage bias. The channel length and gate oxide dependence of V ASCBE comes from V dsat and litl. We replace B i with PSCBE and A i /B i with PSCBE1/L eff to get the following expression for V ASCBE 1 PSCBE PSCBE1 litl = exp VASCBE Leff Vds Vdsat (5.44) BSIM4.6.4 Manual Copyright 009 UC Berkeley 4

51 Drain Current Model Drain-Induced Threshold Shift (DITS) by Pocket Implant It has been shown that a long-channel device with pocket implant has a smaller R out than that of uniformly-doped device [3]. The R out degradation factor F is given in (6.35). In addition, the pocket implant introduces a potential barrier at the drain end of the channel. This barrier can be lowered by the drain bias even in long-channel devices. The Early voltage due to DITS is modeled by 1 V = F + + PDITSL L PDITSD V PDITS 1 ( 1 ) exp( ) (5.45) ADITS eff ds 5.8 Single-Equation Channel Current Model The final channel current equation for both linear and saturation regions now becomes I ds Ids0 NF 1 V A = 1 ln RdsI + ds 0 1+ V C dseff clm VAsat Vds V dseff Vds V dseff Vds V dseff VADIBL VADITS VASCBE (5.46) where NF is the number of device fingers, and V A is written as where V Asat is VA = VAsat + VACLM (5.47) V Asat = E L + V + R vsatc W V 1 + AbulkVdsat ( gsteff + t ) sat eff dsat ds oxe eff gsteff V v RdsvsatCoxeWeff Abulk 1 λ (5.48) V Asat is the Early voltage at V ds = V dsat. V Asat is needed to have continuous drain current and output resistance expressions at the transition point between linear and saturation regions. BSIM4.6.4 Manual Copyright 009 UC Berkeley 43

52 Drain Current Model 5.9 New Current Saturation Mechanisms: Velocity Overshoot and Source End Velocity Limit Model Velocity Overshoot In the deep-submicron region, the velocity overshoot has been observed to be a significant effect even though the supply voltage is scaled down according to the channel length. An approximate non-local velocity field expression has proven to provide a good description of this effect λ E µ E λ E v = vd (1 + ) = (1 + ) E x 1 + E/ E E x c (5.49) This relationship is then substituted into (6.45) and the new current expression including the velocity overshoot effect is obtained: I DS, HD = I DS Vdseff 1+ Leff E Vdseff 1+ OV L E eff sat sat (5.50) where E OV sat Vds Vdseff 1+ 1 LAMBDA Esat litl = E sat 1 + Leff µ eff Vds V dseff Esat litl LAMBDA is the velocity overshoot coefficient. (5.51) 5.9. Source End Velocity Limit Model When MOSFETs come to nanoscale, because of the high electric field and strong velocity overshoot, carrier transport through the drain end of the channel is rapid. As a result, the dc current is controlled by how rapidly carriers are transported across a short low-field region near the beginning of BSIM4.6.4 Manual Copyright 009 UC Berkeley 44

53 Drain Current Model the channel. This is known as injection velocity limits at the source end of the channel. A compact model is firstly developed to account for this current saturation mechanism. Hydro-dynamic transportation gives the source end velocity as : v shd I = DS, HD Wq s (5.5) where q s is the source end inversion charge density. Source end velocity limit gives the highest possible velocity which can be given through ballistic transport as: v sbt 1 r (5.53) = VTL 1 + r where VTL: thermal velocity, r is the back scattering coefficient which is given: Leff r = XN 3.0 XN L + LC eff (5.54) The real source end velocity should be the lower of the two, so a final Unified current expression with velocity saturation, velocity overshoot and source velocity limit can be expressed as : I DS DS, HD = MM 1 + ( vshd / vsbt ) I 1/MM (5.55) where MM=.0. BSIM4.6.4 Manual Copyright 009 UC Berkeley 45

54 Body Current Models Chapter 6: Body Current Models In addition to the junction diode current and gate-to-body tunneling current, the substrate terminal current consists of the substrate current due to impact ionization (I ii ), and gate-induced drain leakage and source leakage currents (I GIDL and I GISL ). 6.1 I ii Model The impact ionization current model in BSIM4 is the same as that in BSIM3v3., and is modeled by ALPHA0+ ALPHA1 L eff BETA0 I = ( V V ) exp I L eff Vds V dseff ii ds dseff dsnoscbe (6.1) where parameters ALPHA0 and BETA0 are impact ionization coefficients; parameter ALPHA1 is introduced to improves the I ii scalability, and I dsnoscbe Ids0 NF 1 V Vds V A dseff Vds V dseff = 1 ln 1 1 RdsI ds 0 1+ V C dseff clm VAsat VADIBL VADITS (6.) 6. I GIDL and I GISL Model mtrlmod=0 The GIDL/GISL current and its body bias effect are modeled by [9]-[10] Vds Vgse EGIDL IGIDL = AGIDL WeffCJ Nf 3 T 3 T BGIDL V exp V V EGIDL CGIDL V oxe 3 oxe db 3 ds gse + db (6.3) BSIM4.6.4 Manual Copyright 009 UC Berkeley 46

55 Body Current Models Vds Vgde EGISL IGISL = AGISL WeffCJ Nf 3 T 3 T BGISL V exp V V EGISL CGISL+ V oxe 3 oxe sb 3 ds gde sb (6.4) where AGIDL, BGIDL, CGIDL and EGIDL are model parameters for the drain side and AGISL, BGISL, CGISL and EGISL are the model parameters for the source side. They are explained in Appendix A. CGIDL and CGISL account for the body-bias dependence of I GIDL and I GISL respectively. W effcj and Nf are the effective width of the source/drain diffusions and the number of fingers. Further explanation of W effcj and Nf can be found in the chapter of the layout-dependence model. mtrlmod=1 In this case, the work function difference (V fbsd ) between source/drain and channel could be modeled as follows: Eg0 Eg0 NSD Vfbsd = PHIG ( EASUB + BSIM 4 typy MIN, vt ln n i Moreover, the GIDL/GISL current should be modified as following: (6.5) Vds Vgse EGIDL+ Vfbsd IGIDL = AGIDL WeffCJ Nf EPSRSUB EOT 3.9 EPSRSUB EOT BGIDL V exp V V EGIDL V CGIDL V db 3 ds gse + fbsd + db (6.6) BSIM4.6.4 Manual Copyright 009 UC Berkeley 47

56 Body Current Models Vds Vgse EGISL+ Vfbsd IGIDS = AGISL WeffCJ Nf EPSRSUB EOT 3.9 EPSRSUB EOT BGISL V exp V V EGISL V CGISL V db 3 ds gse + fbsd + db (6.7) BSIM4.6.4 Manual Copyright 009 UC Berkeley 48

57 Capacitance Model Chapter 7: Capacitance Model Accurate modeling of MOSFET capacitance plays equally important role as that of the DC model. This chapter describes the methodology and device physics considered in both intrinsic and extrinsic capacitance modeling in BSIM Complete model parameters can be found in Appendix A. 7.1 General Description BSIM4.0.0 provides three options for selecting intrinsic and overlap/fringing capacitance models. These capacitance models come from BSIM3v3., and the BSIM3v3. capacitance model parameters are used without change in BSIM4 except that separate CKAPPA parameters are introduced for the source-side and drain-side overlap capacitances. The BSIM3v3. capmod = 1 is no longer supported in BSIM4. The following table maps the BSIM4 capacitance models to those of BSIM3v3.. BSIM4 capacitance models Matched capmod in BSIM3v3.. capmod = 0 (simple and piece- wise model) Intrinsic capmod = 0 + overlap/fringing capmod = 0 capmod = 1 (single-equation model) Intrinsic capmod = + overlap/fringing capmod = capmod = (default model; singel-equation and charge-thickness model Intrinsic capmod = 3 + overlap/fringing capmod = BSIM4 capacitance models have the following features: Separate effective channel length and width are used for capacitance models. BSIM4.6.4 Manual Copyright 009 UC Berkeley 49

58 Capacitance Model capmod = 0 uses piece-wise equations. capmod = 1 and are smooth and single equation models; therefore both charge and capacitance are continous and smooth over all regions. Threshold voltage is consistent with DC part except for capmod = 0, where a long-channel V th is used. Therefore, those effects such as body bias, short/narrow channel and DIBL effects are explicitly considered in capmod = 1 and. A new threshold voltage definition is introduced to improve the fitting in subthreshold region. Setting cvchargemod = 1 activates the new V gsteff,cv calculation which is similar to the V gsteff formulation in the I-V model. Overlap capacitance comprises two parts: (1) a bias-independent component which models the effective overlap capacitance between the gate and the heavily doped source/drain; () a gate-bias dependent component between the gate and the lightly doped source/drain region. Bias-independent fringing capacitances are added between the gate and source as well as the gate and drain. 7. Methodology for Intrinsic Capacitance Modeling 7..1 Basic Formulation To ensure charge conservation, terminal charges instead of terminal voltages are used as state variables. The terminal charges Q g, Q b, Q s, and Q d are the charges associated with the gate, bulk, source, and drain termianls, respectively. The gate charge is comprised of mirror charges from these components: the channel charge (Q inv ), accumulation charge (Q acc ) and substrate depletion charge (Q sub ). BSIM4.6.4 Manual Copyright 009 UC Berkeley 50

59 Capacitance Model The accumulation charge and the substrate charge are associated with the substrate while the channel charge comes from the source and drain terminals Qg = ( Qsub + Qinv + Qacc ) (7.1) Qb = Qacc + Qsub Qinv = Qs + Qd The substrate charge can be divided into two components: the substrate charge at zero source-drain bias (Q sub0 ), which is a function of gate to substrate bias, and the additional non-uniform substrate charge in the presence of a drain bias (δq sub ). Q g now becomes Q = ( Q + Q + Q + δq ) (7.) g inv acc sub0 sub The total charge is computed by integrating the charge along the channel. The threshold voltage along the channel is modified due to the non-uniform substrate charge by V ( y) V (0) ( A 1) V = + (7.3) th th bulk y Lactive Lactive Qc = Wactive qcdy = WactiveCoxe ( Vgt AbulkVy ) dy 0 0 Lactive Lactive Qg = Wactive qgdy = WactiveCoxe ( Vgt + Vth VFB Φs Vy ) dy 0 0 Lactive Lactive Qb = Wactive qbdy = WactiveCoxe ( Vth VFB Φ s + ( Abulk 1) Vy ) dy 0 0 (7.4) where V gt = V gse - V th and dv dy = E y y (7.5) where E y is expressed in BSIM4.6.4 Manual Copyright 009 UC Berkeley 51

60 Capacitance Model Wactiveµ eff Coxe Abulk I = V V V = W µ C ( V A V ) E L ds gt ds ds active eff oxe gt bulk y y active (7.6) All capacitances are derived from the charges to ensure charge conservation. Since there are four terminals, there are altogether 16 components. For each component C ij Qi (7.7) = V j where i and j denote the transistor terminals. C ij satisfies Cij = Cij = 0 (7.8) i j 7.. Short Channel Model cvchargemod=0 The long-channel charge model assumes a constant mobility with no velocity saturation. Since no channel length modulation is considered, the channel charge remains constant in saturation region. Conventional long- channel charge models assume V dsat,cv = V gt / A bulk and therefore is independent of channel length. If we define a drain bias, V dsat,cv, for capacitance modeling, at which the channel charge becomes constant, we will find that V dsat,cv in general is larger than V dsat for I-V but smaller than the long-channel V dsat = V gt / A bulk. In other words, V Vdsat, IV < Vdsat, CV < Vdsat, IV Lactive = A gsteff, CV bulk (7.9) and V dsat,cv is modeled by BSIM4.6.4 Manual Copyright 009 UC Berkeley 5

61 Capacitance Model V gsteff CV V dsat, CV = A bulk V gsteff, CV CLC 1 + L active Vgse Vth VOFFCV, = NOFF nvt ln 1 + exp NOFF nvt CLE (7.10) (7.11) Model parameters CLC and CLE are introduced to consider the effect of channel-length modulation. A bulk for the capacitance model is modeled by A bulk A0 Leff B0 1 = 1 + F doping + L Weff ' B1 1 KETA V eff + XJ X + + dep bseff (7.1) where 1+ F doping = + K K B Φ W ' W 0 LPEB Leff K1 ox TOXE ox 3 Φs V bseff eff + s (7.13) cvchargemod=1 In order to improve the predictive modeling in the subthreshold region, a new threshold voltage for C-V is introduced as following: V gsteffcv nv ln t 1+ exp = * φ s m + ncoxe exp qndepε Si m Voff ( gse th ) nv t m V V Voff * m V V * arctan ( MINVCV ) = ' π ( 1 )( gse th ) VOFFCVL = VOFFCV + L eff * ' nv t (7.14) (7.15) (7.16) It is clear that this new definition is similar to V gsteff in I-V model. BSIM4.6.4 Manual Copyright 009 UC Berkeley 53

62 Capacitance Model Note: The default value of cvchargemod is zero to keep the backward compatibility Single Equation Formulation Traditional MOSFET SPICE capacitance models use piece-wise equations. This can result in discontinuities and non-smoothness at transition regions. The following describes single-equation formulation for charge, capacitance and voltage modeling in capmod = 1 and. (a) Transition from depletion to inversion region The biggest discontinuity is at threshold voltage where the inversion capacitance changes abruptly from zero to C oxe. Concurrently, since the substrate charge is a constant, the substrate capacitance drops abruptly to zero at threshold voltage. The BSIM4 charge and capacitance models are formulated by substituting V gst with V gsteff,cv as ( gst ) QV ( gsteff, CV ) QV For capacitance modeling = (7.17) V, ( gst ) = CV ( gsteff, CV ) CV V gsteff CV gdsb,,, (7.18) (b) Transition from accumulation to depletion region An effective smooth flatband voltage V FBeff is used for the accumulation and depletion regions. ( ) ( ) V = V 0.5 V V V V V FBeff fbzb fbzb gb fbzb gb fbzb (7.19) where BSIM4.6.4 Manual Copyright 009 UC Berkeley 54

63 Capacitance Model V V K1 = Φ Φ (7.0) fbzb th zerovbs andvds s s A bias-independent V th is used to calculate V fbzb for capmod = 1 and. For capmod = 0, VFBCV is used instead (refer to Appendix A). (c) Transition from linear to saturation region An effective V ds, V cveff, is used to smooth out the transition between linear and saturation regions. { δ } V = V 0.5 V + V + 4 V cveff dsat, CV dsat, CV where V = V V δ ; δ = 0.0V 4 dsat, CV ds 4 4 (7.1) 7..4.Charge partitioning The inversion charges are partitioned into Q inv = Q s + Q d. The ratio of Q d to Q s is the charge partitioning ratio. Existing charge partitioning schemes are 0/100, 50/50 and 40/60 (XPART = 1, 0.5 and 0). 50/50 charge partition This is the simplest of all partitioning schemes in which the inversion charges are assumed to be contributed equally from the source and drain terminals. 40/60 charge partition This is the most physical model of the three partitioning schemes in which the channel charges are allocated to the source and drain terminals by assuming a linear dependence on channel position y. BSIM4.6.4 Manual Copyright 009 UC Berkeley 55

64 Capacitance Model Lactive y Qs = Wactive qc 1 L 0 active dy Lactive y Qd = Wactive qc dy L 0 active (7.) 0/100 charge partition In fast transient simulations, the use of a quasi-static model may result in a large unrealistic drain current spike. This partitioning scheme is developed to artificially suppress the drain current spike by assigning all inversion charges in the saturation region to the source electrode. Notice that this charge partitioning scheme will still give drain current spikes in the linear region and aggravate the source current spike problem. 7.3 Charge-Thickness Capacitance Model (CTM) mtrlmod=0 Current MOSFET models in SPICE generally overestimate the intrinsic capacitance and usually are not smooth at V fb and V th. The discrepancy is more pronounced in thinner T ox devices due to the assumption of inversion and accumulation charge being located at the interface. Numerical quantum simulation results in Figure 8.1 indicate the significant charge thickness in all regions of operation. BSIM4.6.4 Manual Copyright 009 UC Berkeley 56

65 Capacitance Model Figure 7.1 Charge distribution from numerical quantum simulations show significant charge thickness at various bias conditions shown in the inset. CTM is a charge-based model and therefore starts with the DC charge thickness, X DC. The charge thickness introduces a capacitance in series with C ox as illustrated in Figure 7., resulting in an effective C oxeff. Based on numerical self-consistent solution of Shrődinger, Poisson and Fermi-Dirac equations, universal and analytical X DC models have been developed. C oxeff can be expressed as C oxeff C = C oxp oxp C + C cen cen (7.3) where C = ε / X (7.4) cen si DC BSIM4.6.4 Manual Copyright 009 UC Berkeley 57

66 Capacitance Model Figure 7. Charge-thickness capacitance concept in CTM. V gse accounts for the poly depletion effect. (i) X DC for accumulation and depletion The DC charge thickness in the accumulation and depletion regions can be expressed by NDEP V V V XDC = Ldebye exp ACDE TOXP gse bseff FBeff (7.5) where L debye is Debye length, and X DC is in the unit of cm and (V gse - V bseff - V FBeff ) / TOXP is in units of MV/cm. For numerical stability, (8.5) is replaced by (8.6) where ( 4δ x ) 1 XDC = X X + X + X max 0 0 max (7.6) X0 = Xmax XDC δ x (7.7) and X max = L debye / 3; = 10-3 TOXE. (ii) X DC of inversion charge The inversion charge layer thickness can be formulated as BSIM4.6.4 Manual Copyright 009 UC Berkeley 58

67 X DC Capacitance Model 9 ADOS m = Vgsteff + 4( VTH0 VFB Φs ) 1+ TOXP 0.7 BDOS (7.8) Here, the density of states parameters ADOS and BDOS are introduced to control the charge centroid. Their default values are one. Through the VFB term, equation (7.8) is found to be applicable to N + or P + poly-si gates and even other future gate materials. (iii) Body charge thickness in inversion In inversion region, the body charge thickness effect is modeled by including the deviation of the surface potential Ф S (bias-dependence) from Ф B [] ϕδ V ( V + K Φ =Φs Φ B = νt ln 1+ gsteffcv gsteffcv 1ox B MOIN K1 ox ν t The channel charge density is therefore derived as (7.9) (, ϕ ) q = C V (7.30) δ inv oxeff gsteff CV eff where (7.31) mtrlmod=1 First, TOXP should be iteratively calculated by EOT as follows: 3.9 TOXP = EOT X DC V = VDDEOT V = V = EPSRSUB gs, ds bs 0 (7.3) BSIM4.6.4 Manual Copyright 009 UC Berkeley 59

68 Capacitance Model X DC 9 ADOS = Vgsteff + ( VTH0 VFB φs ) 1+ TOXP 0.7 BDOS (7.33) With the calculated TOXP, X DC could be obtained at different gate voltage. Now C cen is equal to EPSRSUB/X DC. The other calculations are as same as mtrlmod= Intrinsic Capacitance Model Equations capmod = 0 Accumulation region g active active oxe gs bs ( ) Q W L C V V VFBCV = (7.34) Q sub = Q (7.35) g Q = 0 (7.36) inv Subthreshold region K ( Vgs VFBCV Vbs ) 1ox sub0 = active active oxe K1 ox Q W L C Q g sub0 4 (7.37) = Q (7.38) Q = 0 (7.39) inv Strong inversion region A bulk V dsat, cv Vgs V = A ' bulk th CLC ' = A bulk 1+ L eff CLE th s 1ox s bseff (7.40) (7.41) V = VFBCV +Φ + K Φ V (7.4) BSIM4.6.4 Manual Copyright 009 UC Berkeley 60

69 Capacitance Model Linear region V A ' V Qg = CoxeWactiveL active Vgs VFBCV Φs + A 1 Vgs Vth ds bulk ds bulk ' V ds (7.43) (7.44) Qb = CoxeWactiveL active VFBCV Vth Φ s + 1 V ( 1 A ') V ( 1 A ') A ' V bulk ds bulk bulk ds gs V th A bulk ' V ds 50/50 partitioning: A ' V A ' V Qinv = CoxeWactiveL active Vgs Vth Φs + A 1 Vgs Vth bulk ds bulk ds bulk ' V ds (7.45) Q = Q = 0.5Q (7.46) s d inv 40/60 partitioning: (7.47) ( Vgs Vth ) Abulk ' Vds ( Vgs Vth ) ( Abulk ' Vds ) Abulk ' Vds Vgs Vth Abulk ' V ds Qd = CoxeWactiveL active + ' Abulk V ds 1( Vgs Vth ) ( ) Q Q Q Q = + + (7.48) s g b d BSIM4.6.4 Manual Copyright 009 UC Berkeley 61

70 Capacitance Model 0/100 partitioning: ( ' ) V V Abulk ' V A V ds Qd = CoxeWactiveLactive gs th bulk ds ( ) Q Q Q Q s g b d (7.49) = + + (7.50) Saturation region: V Qg = CoxeWactiveLactive Vgs VFBCV Φs 3 Qb = CoxeWactiveLactive VFBCV +Φs Vth + dsat ( 1 A ') bulk 3 V dsat (7.51) (7.5) 50/50 partitioning: 1 Q = Q = C W L V V 3 ( ) s d oxe active active gs th (7.53) 40/60 partitioning: 4 Q = C W L V V 15 ( ) d oxe active active gs th ( ) Q Q Q Q s g b d (7.54) = + + (7.55) 0/100 partitioning: Q = 0 (7.56) d ( ) Q Q Q = + (7.57) s g b 7.4. capmod = 1 = ( δ ) (7.58) Q Q Q Q Q g inv acc sub0 sub BSIM4.6.4 Manual Copyright 009 UC Berkeley 6

71 Capacitance Model ( ) Q Q Q Q = + + (7.59) s g b d Qinv = Qs + Qd (7.60) ( ) Q W L C V V = (7.61) acc active active oxe FBeff fbzb K ( gse VFBeff Vgsteff Vbseff ) 4V 1ox sub0 = active active oxe K1 ox Q W L C V dsat, cv V = A gsteffcv 1 Qinv = WactiveLactiveCoxe Vgsteff, cv Abulk ' Vcveff + 1 V bulk 1 Abulk ' δqsub = WactiveLactiveCoxe Vcveff 1 V ' A gsteff, cv ' V bulk cveff A bulk ( 1 A ') A ' V gsteff, cv ' V ' V bulk bulk cveff A bulk cveff cveff (7.6) (7.63) (7.64) (7.65) 50/50 charge partitioning: WactiveLactiveC oxe 1 QS = QD = Vgsteff, cv Abulk ' Vcveff + 1 V A gsteff, cv ' V bulk cveff A bulk ' V cveff (7.66) 40/60 charge partitioning: Q S 4 V V A ' V = 3 gsteff, cv gsteff, cv bulk cveff WactiveLactiveC 3 oxe ' 3 Abulk Vcveff V V, ( ' ) ( ' ) gsteff, cv gsteff cv Abulk Vcveff Abulk V + cveff 3 15 (7.67) BSIM4.6.4 Manual Copyright 009 UC Berkeley 63

72 Q D Capacitance Model 5 V V A ' V = 3 gsteff, cv gsteff, cv bulk cveff WactiveLactiveC 3 oxe ' 1 3 Abulk Vcveff V V, ( ' ) ( ' ) gsteff, cv gsteff cv Abulk Vcveff Abulk V + cveff 5 (7.68) 0/100 charge partitioning: WactiveLactiveC oxe 1 QS = Vgsteff, cv + Abulk ' Vcveff 1 V WactiveLactiveC oxe 3 QD = Vgsteff, cv Abulk ' Vcveff + 4 V A gsteff, cv gsteff, cv ' V bulk cveff A A ' bulk V ' V bulk cveff A bulk ' V cveff dveff (7.69) (7.70) capmod = Qacc = WactiveLactiveCoxeff Vgbacc (7.71) 1 Vgbacc = V0 + V V fbzb V0 V V V 0.0 fbzb bseff gs (7.7) = + (7.73) ( 0.08 ) V = V V + V + V cveff dsat dsat (7.74) V1 = Vdsat Vds 0.0 (7.75) V dsat V = gsteff, cv A bulk ϕ δ ( ) ( ) ( ), ϕδ 0.5, ϕδ 0.001, ϕδ V = V + V + V gsteff CV eff gsteff CV gsteff CV g ' (7.76) (7.77) K ( gse VFBeff Vbseffs Vgsteff, cv ) 4V 1ox sub0 = active active oxeff K1 ox Q W L C (7.78) BSIM4.6.4 Manual Copyright 009 UC Berkeley 64

73 Capacitance Model 1 Abulk ' δqsub = WactiveLactiveCoxeff Vcveff A 1 Vgsteff, cv ϕδ ( 1 A ') A ' V bulk bulk cveff bulk ' V cveff (7.79) (7.80) Qb = CoxeWactiveL active VFBCV Vth Φ s + 1 V ( 1 A ') V ( 1 A ') A ' V bulk ds bulk bulk ds gs V th A bulk ' V ds 50/50 partitioning: (7.81) Wactive LactiveC oxeff 1 Abulk ' Vcveff QS = QD = Vgsteff, cv ϕδ Abulk ' Vcveff + A 1 ( Vgsteff, cv ϕδ ) eff bulk ' V cveff 40/60 partitioning: (7.8) Q S 3 4 ( V, ϕ ) ( V, ) A ' V W L C δ ϕδ = gsteff cv gsteff cv bulk cveff active active oxeff 3 ' 3 Abulk Vcveff V (, )( ' ) ( ' ) gsteff, cv ϕ Vgsteff cv ϕδ Abulk Vcveff Abulk V + δ cveff 3 15 BSIM4.6.4 Manual Copyright 009 UC Berkeley 65

74 Capacitance Model (7.83) Q D 3 5 ( V, ϕ ) ( V, ) A ' V W L C δ ϕδ = gsteff cv gsteff cv bulk cveff active active oxeff 3 ' 1 3 Abulk Vcveff V (, )( ' ) ( ' ) gsteff, cv ϕ Vgsteff cv ϕδ Abulk Vcveff Abulk V + δ cveff 5 0/100 partitioning: (7.84) Q W L C V A V A ' V active active oxeff 1 bulk cveff S = gsteff, cv ϕδ + bulk ' cveff Abulk 1 Vgsteff, cv ϕδ ' V cveff (7.85) W L C A ' V Q V A V 4 ( Vgsteff, cv ϕδ ) eff active active oxeff 3 bulk cveff D = ( gsteff, cv ϕδ ) bulk ' cveff + eff Abulk ' V dveff 7.5 Fringing/Overlap Capacitance Models Fringing capacitance model The fringing capacitance consists of a bias-independent outer fringing capacitance and a bias-dependent inner fringing capacitance. Only the bias- independent outer fringing capacitance (CF) is modeled. If CF is not given, it is calculated by BSIM4.6.4 Manual Copyright 009 UC Berkeley 66

75 Capacitance Model CF EPSROX ε 4.0e 7 log 1 π TOXE 0 = + (7.86) 7.5. Overlap capacitance model An accurate overlap capacitance model is essential. This is especially true for the drain side where the effect of the capacitance is amplified by the transistor gain. In old capacitance models this capacitance is assumed to be bias independent. However, experimental data show that the overlap capacitance changes with gate to source and gate to drain biases. In a single drain structure or the heavily doped S/D to gate overlap region in a LDD structure the bias dependence is the result of depleting the surface of the source and drain regions. Since the modulation is expected to be very small, we can model this region with a constant capacitance. However in LDD MOSFETs a substantial portion of the LDD region can be depleted, both in the vertical and lateral directions. This can lead to a large reduction of the overlap capacitance. This LDD region can be in accumulation or depletion. We use a single equation for both regions by using such smoothing parameters as V gs,overlap and V gd,overlap for the source and drain side, respectively. Unlike the case with the intrinsic capacitance, the overlap capacitances are reciprocal. In other words, C gs,overlap = C sg,overlap and C gd,overlap = C dg,overlap. If capmod is non-zero, BSIM4 uses the bias-dependent overlap capacitance model; otherwise, a simple bias-independent model will be used. Bias-dependent overlap capacitance model (i) Source side BSIM4.6.4 Manual Copyright 009 UC Berkeley 67

76 Capacitance Model Q overlap, s W active = CKAPPAS 4Vgs, overlap CGSO Vgs + CGSL Vgs Vgs, overlap 1+ 1 CKAPPAS (7.87) ( ) 1 Vgs, overlap = Vgs + δ1 ( Vgs + δ1) + 4 δ1 δ1 = 0.0V (7.88) (ii) Drain side Q overlap, d W active = CGDO V gd CKAPPAD 4V gd, overlap + CGDL Vgd Vgd, overlap 1+ 1 CKAPPAD ( ) 1 Vgd, overlap = Vgd + δ1 ( Vgd + δ1) + 4 δ1 δ1 = 0.0V (7.89) (7.90) (iii) Gate Overlap Charge ( ( ) ) Q = Q + Q + CGBO L V (7.91) overlap, g overlap, d overlap, s active gb where CGBO is a model parameter, which represents the gate-to-body overlap capacitance per unit channel length. Bias-independent overlap capacitance model If capmod = 0, a bias-independent overlap capacitance model will be used. In this case, model parameters CGSL, CGDL, CKAPPAS and CKAPPD all have no effect. The gate-to-source overlap charge is expressed by BSIM4.6.4 Manual Copyright 009 UC Berkeley 68

77 Capacitance Model Q W CGSO V = (7.9) overlap, s active gs The gate-to-drain overlap charge is calculated by Q W CGDO V = (7.93) overlap, d active gd The gate-to-substrate overlap charge is computed by Q L CGBO V = (7.94) overlap, b active gb Default CGSO and CGDO If CGSO and CGDO (the overlap capacitances between the gate and the heavily doped source / drain regions, respectively) are not given, they will be calculated. Appendix A gives the information on how CGSO, CGDO and CGBO are calculated. BSIM4.6.4 Manual Copyright 009 UC Berkeley 69

78 New Material Models Chapter 8: New Material Models The enormous success of CMOS technology in the past is mainly resulted from the continuous scaling of MOSFET device. Until very recently, the evolutionary scaling (such as gate dielectric) is based on the shrinking of physical dimensions. Many fundamental problems, such as increased gate leakage and oxide breakdown, have arisen from this conventional method. One of the effective solutions is to introduce new materials to replace the conventional material (For example, the silicon oxide gate is substituted by the high-k gate insulator). Significant progress has been achieved in terms of the understanding of new material properties and their integration into CMOS technology. Considering the impacts of new materials on the electrical characteristics, BSIM introduces the new material model, which could predict well the non- SiO gate insulator, non-poly-si gate and non-si channel. 8.1 Model Selector One global selector is provided to turn on or off the new material models. When the selector (mtrlmod) is set to one, the new materials are modeled; while the default value (mtrlmod=0) maintains the backward compatibility. 8. Non-Silicon Channel With the three new parameters, the temperature-dependent band gap and intrinsic carriers in non-silicon channel are described as follow: TBGASUB Tnom Eg0= BG0SUB Tnom + TBGBSUB (8.1) BSIM4.6.4 Manual Copyright 009 UC Berkeley 70

79 New Material Models n i TBGASUB Eg(300.15) = BG0SUB TBGBSUB 3/ Tnom Eg(300.15) Eg0 = NI0SUB exp vt (8.) (8.3) TBGASUB Temp (8.4) Eg = BG0SUB Temp + TBGBSUB Here, BG0SUB is the band-gap of substrate at T=0K; TBGASUB and TBGBSUB are the first and second parameters of band-gap change due to temperature, respectively. The inversion charge layer thickness (X DC ) is also modified as follows: X DC 9 ADOS = Vgsteff + ( VTH0 VFB φs ) 1+ TOXP 0.7 BDOS (8.5) Here, the density of states parameters ADOS and BDOS are introduced to control the charge centroid. 8.3 Non-SiO Gate insulator For Non-SiO gate insulator, the equivalent SiO thickness (EOT) is a new input parameter, which is measured at VDDEOT. Given this new parameter, the physical gate oxide thickness TOXP could be calculated as follows: 3.9 TOXP = EOT X DC V = VDDEOT V = V = EPSRSUB gs, ds bs 0 Here, EPSRSUB is the dielectric constant of substrate relative to vacuum. (8.6) BSIM4.6.4 Manual Copyright 009 UC Berkeley 71

80 New Material Models 8.4 Non-Poly Silicon Gate Dielectric Two new parameters are introduced to describe the non-poly silicon gate dielectric. One is PHIG, which is the gate work function. Another is EPSRGATE, the dielectric constant of gate relative to vacuum. It is worth pointing out that EPSRGATE=0 represents the metal gate and deactivates the ploy depletion effect. When the gate dielectric and channel are different materials, the flat band voltage at Source/Drain is calculated using the following: Eg0 Eg0 NSD Vfbsd = PHIG ( EASUB + BSIM 4 typy MIN, vt ln n i (8.7) This new flat band equation improves the GIDL/GISL models as following: Vds Vgse EGIDL+ Vfbsd IGIDL = AGIDL WeffCJ Nf EPSRSUB EOT 3.9 EPSRSUB EOT BGIDL V exp V V EGIDL V CGIDL V db 3 ds gse + fbsd + db Vds Vgse EGISL+ Vfbsd IGIDS = AGISL WeffCJ Nf EPSRSUB EOT 3.9 EPSRSUB EOT BGISL V exp V V EGISL V CGISL V db 3 ds gse + fbsd + db (8.8) (8.9) Furthermore, for mtrlmod=1 the mobility degradation uses the new expression of the vertical field in channel as following: BSIM4.6.4 Manual Copyright 009 UC Berkeley 7

81 New Material Models (8.10) E eff Vgsteff + V th BSIM 4 type ( PHIG EASUB Eg / ) 3.9 = EOT EPSRSUB Consequently, when mtrlmod=1, mobmod=0 and mobmod=1 are changed, respectively: mobmod=0 µ eff = U0 f( L ) 1 + ( + ) + + th UA UC Vbseff Eeff UB Eeff UD V gsteff V th mobmod=1 eff V EOT (8.11) µ eff = U0 f( L ) V EOT UA E UB E UC V UD V gsteff + V ( eff + eff )(1 + bseff ). eff th th (8.1) BSIM4.6.4 Manual Copyright 009 UC Berkeley 73

82 High-Speed/RF Models Chapter 9: High-Speed/RF Models As circuit speed and operating frequency rise, the need for accurate prediction of circuit performance near cut-off frequency or under very rapid transient operation becomes critical. BSIM4.0.0 provides a set of accurate and efficient high-speed/rf (radio frequency) models which consist of three modules: charge-deficit non-quasi-static (NQS) model, intrinsic-input resistance (IIR) model (bias-dependent gate resistance model), and substrate resistance network model. The charge-deficit NQS model comes from BSIM3v3. NQS model [11] but many improvements are added in BSIM4. The IIR model considers the effect of channel-reflected gate resistance and therefore accounts for the first-order NQS effect [1]. Thus, the chargedeficit NQS model and the IIR model should not be turned on simultaneously. These two models both work with multi-finger configuration. The substrate resistance model does not include any geometry dependence. 9.1 Charge-Deficit Non-Quasi-Static (NQS) Model BSIM4 uses two separate model selectors to turn on or off the charge-deficit NQS model in transient simulation (using trnqsmod) and AC simulation (using acnqsmod). The AC NQS model does not require the internal NQS charge node that is needed for the transient NQS model. The transient and AC NQS models are developed from the same fundamental physics: the channel/gate charge response to the external signal are relaxation-time (τ) dependent and the transcapacitances and transconductances (such as G m ) for AC analysis can therefore be expressed as functions of jωτ. BSIM4.6.4 Manual Copyright 009 UC Berkeley 74

83 High-Speed/RF Models MOSFET channel region is analogous to a bias-dependent RC distributed transmission line (Figure 10. 1a). In the Quasi-Static (QS) approach, the gate capacitor node is lumped with the external source and drain nodes (Figure 10. 1b). This ignores the finite time for the channel charge to build-up. One way to capture the NQS effect is to represent the channel with n transistors in series (Figure 10.1c), but it comes at the expense of simulation time. The BSIM4 charge-deficit NQS model uses Elmore equivalent circuit to model channel charge build-up, as illustrated in Figure 9.1d. Figure 9.1 Quasi-Static and Non-Quasi-Static models for SPICE analysis Transient Model The transient charge-deficit NQS model can be turned on by setting trnqsmod = 1 and off by setting trnqsmod = 0. Figure 10. shows the RC sub-circuit of charge deficit NQS model for transient simulation [13]. An internal node, Q def (t), is created to keep track of the amount of deficit/surplus channel charge necessary to reach equilibrium. The resistance R is determined from the RC time constant (τ). The current BSIM4.6.4 Manual Copyright 009 UC Berkeley 75

84 High-Speed/RF Models source i cheq (t) represents the equilibrium channel charging effect. The capacitor C is to be the value of C fact (with a typical value of Farad [11]) to improve simulation accuracy. Q def now becomes () = (9.1) Q t V C def def fact Figure 9. Charge deficit NQS sub-circuit for transient analysis. Considering both the transport and charging component, the total current related to the terminals D, G and S can be written as Q idgs,,() t = IDGS,,( DC) + t dgs,, () t (9.) Based on the relaxation time approach, the terminal charge and corresponding charging current are modeled by and Q () t = Q () t Q () t (9.3) def cheq ch Qdgs,,() t Qcheq() t Qdef() t = t t τ (9.4) BSIM4.6.4 Manual Copyright 009 UC Berkeley 76

85 High-Speed/RF Models Qdgs,,() t Qdef() t (9.5) = DGS,, xpart t τ where D,G,S xpart are charge deficit NQS channel charge partitioning number for terminals D, G and S, respectively; D xpart + S xpart = 1 and G xpart = -1. The transit time τ is equal to the product of R ii and W eff L eff C oxe, where R ii is the intrinsic-input resistance [1] given by 1 I Weff µ ds eff Coxeff kbt = XRCRG1 + XRCRG R ii Vdseff ql eff (9.6) where C oxeff is the effective gate dielectric capacitance calculated from the DC model. Note that R ii in (9.6) considers both the drift and diffusion componets of the channel conduction, each of which dominates in inversion and subthreshold regions, respectively AC Model Similarly, the small-signal AC charge-deficit NQS model can be turned on by setting acnqsmod = 1 and off by setting acnqsmod = 0. For small signals, by substituting (9.3) into (9.5), it is easy to show that in the frequency domain, Q ch (t) can be transformed into ( t) Qcheq Qch () t = 1+ jωτ (9.7) where ω is the angular frequency. Based on (9.7), it can be shown that the transcapacitances C gi, C si, and C di (i stands for any of the G, D, S and B terminals of the device) and the channel transconductances G m, G ds, and G mbs all become complex quantities. For example, now G m have the form of BSIM4.6.4 Manual Copyright 009 UC Berkeley 77

86 High-Speed/RF Models and G m Gm0 Gm0 ωτ = + j 1+ ω τ 1+ ω τ (9.8) C dg Cdg 0 Cdg 0 ωτ (9.9) = + j 1+ ω τ 1+ ω τ Those quantities with sub 0 in the above two equations are known from OP (operating point) analysis. 9. Gate Electrode Electrode and Intrinsic-Input Resistance (IIR) Model 9..1 General Description BSIM4 provides four options for modeling gate electrode resistance (biasindependent) and intrinsic-input resistance (IIR, bias-dependent). The IIR model considers the relaxation-time effect due to the distributive RC nature of the channel region, and therefore describes the first-order non-quasi-static effect. Thus, the IIR model should not be used together with the chargedeficit NQS model at the same time. The model selector rgatemod is used to choose different options. 9.. Model Option and Schematic rgatemod = 0 (zero-resistance): In this case, no gate resistance is generated. BSIM4.6.4 Manual Copyright 009 UC Berkeley 78

87 High-Speed/RF Models rgatemod = 1 (constant-resistance): In this case, only the electode gate resistance (bias-independent) is generated by adding an internal gate node. Rgeltd is give by W ( XGW effcj 3 NGCON ) RSHG + Rgeltd = NGCON L XGL NF ( ) drawn Refer to Chapter 8 for the layout parameters in the above equation. (9.10) rgatemod = (IIR model with variable resistance): In this case, the gate resistance is the sum of the electrode gate resistance (9.10) and the intrinsic-input resistance R ii as given by (9.6). An internal gate node will be generated. trnqsmod = 0 (default) and acnqsmod = 0 (default) should be selected for this case. BSIM4.6.4 Manual Copyright 009 UC Berkeley 79

88 High-Speed/RF Models rgatemod = 3 (IIR model with two nodes): In this case, the gate electrode resistance given by (9.10) is in series with the intrinsic-input resistance R ii as given by (9.6) through two internal gate nodes, so that the overlap capacitance current will not pass through the intrinsic-input resistance. trnqsmod = 0 (default) and acnqsmod = 0 (default) should be selected for this case. 9.3 Substrate Resistance Network General Description For CMOS RF circuit simulation, it is essential to consider the high frequency coupling through the substrate. BSIM4 offers a flexible built-in substrate resistance network. This network is constructed such that little simulation efficiency penalty will result. Note that the substrate resistance parameters as listed in Appendix A should be extracted for the total device, not on a per-finger basis Model Selector and Topology The model selector rbodymod can be used to turn on or turn off the resistance network. rbodymod = 0 (Off): BSIM4.6.4 Manual Copyright 009 UC Berkeley 80

89 High-Speed/RF Models No substrate resistance network is generated at all. rbodymod = 1 (On): All five resistances in the substrate network as shown schematically below are present simultaneously. A minimum conductance, GBMIN, is introduced in parallel with each resistance and therefore to prevent infinite resistance values, which would otherwise cause poor convergence. In Figure 8.3, GBMIN is merged into each resistance to simplify the representation of the model topology. Note that the intrinsic model substrate reference point in this case is the internal body node bnodeprime, into which the impact ionization current I ii and the GIDL current I GIDL flow. rbodymod = (On : Scalable Substrate Network): The schematic is similar to rbodymod = 1 but all the five resistors in the substrate network are now scalable with a possibility of choosing either five resistors, three resistors or one resistor as the substrate network. The resistors of the substrate network are scalable with respect to channel length (L), channel width (W) and number of fingers (NF). The scalable model allows to account for both horizontal and vertical contacts. The scalable resistors RBPS and RBPD are evaluated through BSIM4.6.4 Manual Copyright 009 UC Berkeley 81

90 High-Speed/RF Models RBPSL RBPSW L W RBPS = RBPS0 NF RBPDL RBPDW L W RBPD = RBPD0 NF RBPSNF RBPDNF (9.11) (9.1) The resistor RBPB consists of two parallel resistor paths, one to the horizontal contacts and other to the vertical contacts. These two resistances are scalable and RBPB is given by a parallel combination of these two resistances. RBPBXL RBPBXW L W RBPBX = RBPBX 0 NF RBPBYL RBPBYW L W RBPBY = RBPBY 0 NF RBPBX RBPBY RBPB = RBPBX + RBPBY RBPBNF RBPBYNF (9.13) (9.14) (9.15) The resistors RBSB and RBDB share the same scaling parameters but have different scaling prefactors. These resistors are modeled in the same way as RBPB. The equations for RBSB are shown below. The calculation for RBDB follows RBSB. RBSDBXL RBSDBXW L W RBSBX = RBSBX 0 NF RBSDBYL RBSDBYW L W RBSBY = RBSBY 0 NF RBSBX RBSBY RBSB = RBSBX + RBSBY RBSDBXNF RBSDBYNF (9.16) (9.17) (9.18) BSIM4.6.4 Manual Copyright 009 UC Berkeley 8

91 High-Speed/RF Models The implementation of rbodymod = allows the user to chose between the 5-R network (with all five resistors), 3-R network (with RBPS, RBPD and RBPB) and 1-R network (with only RBPB). If the user doesn t provide both the scaling parameters RBSBX0 and RBSBY0 for RBSB OR both the scaling parameters RBDBX0 and RBDBY0 for RBDB, then the conductances for both RBSB and RBDB are set to GBMIN. This converts the 5-R schematic to 3-R schematic where the substrate network consists of the resistors RBPS, RBPD and RBPB. RBPS, RBPD and RBPB are then calculated using (9.10), (9.11) and (9.1). If the user chooses not to provide either of RBPS0 or RBPD0, then the 5-R schematic is converted to 1-R network with only one resistor RBPB. The conductances for RBSB and RBDB are set to GBMIN. The resistances RBPS and RBPD are set to 1e-3 Ohm. The resistor RBPB is then calculated using (9.1). In all other situations, 5-R network is used with the resistor values calculated from the equations aforementioned. Figure 9.3 Topology with the substrate resistance network turned on. BSIM4.6.4 Manual Copyright 009 UC Berkeley 83

92 Noise Modeling Chapter 10: Noise Modeling The following noise sources in MOSFETs are modeled in BSIM4 for SPICE noise ananlysis: flicker noise (also known as 1/f noise), channel thermal noise and induced gate noise and their correlation, thermal noise due to physical resistances such as the source/ drain, gate electrode, and substrate resistances, and shot noise due to the gate dielectric tunneling current. A complete list of the noise model parameters and explanations are given in Appendix A Flicker Noise Models General Description BSIM4 provides two flicker noise models. When the model selector fnoimod is set to 0, a simple flicker noise model which is convenient for hand calculations is invoked. A unified physical flicker noise model, which is the default model, will be used if fnoimod = 1. These two modes come from BSIM3v3, but the unified model has many improvements. For instance, it is now smooth over all bias regions and considers the bulk charge effect Equations fnoimod = 0 (simple model) The noise density is S id KF I C L f ( f ) = oxe AF ds EF eff (10.1) BSIM4.6.4 Manual Copyright 009 UC Berkeley 84

93 Noise Modeling where f is device operating frequency. fnoimod = 1 (unified model) The physical mechanism for the flicker noise is trapping/detrapping-related charge fluctuation in oxide traps, which results in fluctuations of both mobile carrier numbers and mobilities in the channel. The unified flicker noise model captures this physical process. In the inversion region, the noise density is expressed as [14] (10.) S id,inv ( f ) = C + W eff oxe ( L ( L eff eff B B k TI k Tq µ ds L eff clm ds LINTNOI ) A LINTNOI ) f I bulk ef f ef * N 0 + N NOIA log * N l + N NOIA + NOIB N l + NOIC N * ( N + N ) l + NOIB l NOIC ( N N ) + ( N N ) 0 l 0 l where µ eff is the effective mobility at the given bias condition, and L eff and W eff are the effective channel length and width, respectively. The parameter N 0 is the charge density at the source side given by N0 = Coxe Vgsteff q (10.3) The parameter N l is the charge density at the drain end given by N * is given by AbulkV dseff Nl = Coxe Vgsteff 1 q Vgsteff ν + t N * ( ) kt B Coxe + Cd + CIT = q (10.4) (10.5) BSIM4.6.4 Manual Copyright 009 UC Berkeley 85

94 Noise Modeling where CIT is a model parameter from DC IV and C d is the depletion capacitance. L clm is the channel length reduction due to channel length modulation and given by Vds Vdseff + EM Lclm = Litl log Litl Esat VSAT Esat = µ eff (10.6) In the subthreshold region, the noise density is written as S NOIA k T I B ds id, subvt ( f ) = EF * 10 Weff Leff f N 10 (10.7) The total flicker noise density is S id ( f ) ( ) id subvt ( ) ( ) + ( ) Si d, inv f S, f = S f S f id, subvt i d, inv (10.8) 10. Channel Thermal Noise There are two channel thermal noise models in BSIM4. One is a chargebased model (default model) similar to that used in BSIM3v3.. The other is the holistic model. These two models can be selected through the model selector tnoimod. tnoimod = 0 (charge based) The noise current is given by kt f = NTNOI 4 B id Leff Rds ( V ) + µ eff Qinv (10.9) BSIM4.6.4 Manual Copyright 009 UC Berkeley 86

95 Noise Modeling where R ds (V) is the bias-dependent LDD source/drain resistance, and the parameter NTNOI is introduced for more accurate fitting of short-channel devices. Q inv is modeled by Q W L C NF V A V A V bulk dseff bulk dseff inv = active active oxeff gsteff + A V 1 bulk dseff ( Vgsteff ) (10.10) Figure 10.1a shows the noise source connection for tnoimod = 0. Figure 10.1 Schematic for BSIM4 channel thermal noise modeling. tnoimod = 1 (holistic) In this thermal noise model, all the short-channel effects and velocity saturation effect incorporated in the IV model are automatically included, hency the name holistic thermal noise model. In addition, the amplification of the channel thermal noise through G m and G mbs as well as the induced-gate noise with partial correlation to the channel thermal noise are all captured in the new noise partition model. Figure 10.1b shows schematically that part of the channel thermal noise source is partitioned to the source side. The noise voltage source partitioned to the source side is given by BSIM4.6.4 Manual Copyright 009 UC Berkeley 87

96 Noise Modeling v V = 4k T θ I d B tnoi dseff ds f (10.11) and the noise current source put in the channel region with gate and body amplication is given by where V f i = 4k T G + β G + G ( ) ( ) dseff d B ds tnoi m mbs I ds v G + G + G d m ds mbs (10.1) and θ tnoi V gsteff = RNOIB 1 + TNOIB L eff EsatL eff (10.13) β tnoi V gsteff = RNOIA 1 + TNOIA L eff EsatL eff (10.14) where RNOIB and RNOIA are model parameters with default values 0.37 and respectively Other Noise Sources Modeled BSIM4 also models the thermal noise due to the substrate, electrode gate, and source/drain resistances. Shot noise due to various gate tunneling components is modeled as well. BSIM4.6.4 Manual Copyright 009 UC Berkeley 88

97 Asymmetric MOS Junction Diode Models Chapter 11: Asymmetric MOS Junction Diode Models 11.1 Junction Diode IV Model In BSIM4, there are three junction diode IV models. When the IV model selector diomod is set to 0 ("resistance-free"), the diode IV is modeled as resistance-free with or without breakdown depending on the parameter values of XJBVS or XJBVD. When diomod is set to 1 ("breakdown-free"), the diode is modeled exactly the same way as in BSIM3v3. with currentlimiting feature in the forward-bias region through the limiting current parameters IJTHSFWD or IJTHDFWD; diode breakdown is not modeled for diomod = 1 and XJBVS, XJBVD, BVS, and BVD parameters all have no effect. When diomod is set to ("resistance-and-breakdown"), BSIM4 models the diode breakdown with current limiting in both forward and reverse operations. In general, setting diomod to 1 produces fast convergence Source/Body Junction Diode In the following, the equations for the source-side diode are given. The model parameters are shown in Appendix A. diomod = 0 (resistance-free) qv bs Ibs = Isbs exp 1 fbreakdown + Vbs G NJS kbtnom min (11.1) BSIM4.6.4 Manual Copyright 009 UC Berkeley 89

98 Asymmetric MOS Junction Diode Models where I sbs is the total saturation current consisting of the components through the gate-edge (J sswgs ) and isolation-edge sidewalls (J ssws ) and the bottom junction (J ss ), = ( ) + ( ) + ( ) (11.) I A J T P J T W NF J T sbs seff ss seff ssws effcj sswgs where the calculation of the junction area and perimeter is discussed in Chapter 1, and the temperature-dependent current density model is given in Chapter 13. In (11.1), f breakdown is given by f breakdown ( ) q BVS+ Vbs = 1+ XJBVS exp NJS kbtnom (11.3) In the above equation, when XJBVS = 0, no breakdown will be modeled. If XJBVS < 0.0, it is reset to 1.0. diomod = 1 (breakdown-free) No breakdown is modeled. The exponential IV term in (11.5) is linearized at the limiting current IJTHSFWD in the forward-bias model only. qv bs Ibs = Isbs exp 1 + Vbs G NJS kbtnom min (11.4) diomod = (resistance-and-breakdown): Diode breakdown is always modeled. The exponential term (11.5) is linearized at both the limiting current IJTHSFWD in the forward-bias mode and the limiting current IJTHSREV in the reverse-bias mode. qv bs Ibs = Isbs exp 1 fbreakdown + Vbs G NJS kbtnom min (11.5) For diomod =, if XJBVS <= 0.0, it is reset to 1.0. BSIM4.6.4 Manual Copyright 009 UC Berkeley 90

99 Asymmetric MOS Junction Diode Models Drain/Body Junction Diode The drain-side diode has the same system of equations as those for the source-side diode, but with a separate set of model parameters as explained in detail in Appendix A. diomod = 0 (resistance-free) qv bd Ibd = Isbd exp 1 fbreakdown + Vbd G NJD kbtnom min (11.6) where I sbd is the total saturation current consisting of the components through the gate-edge (J sswgd ) and isolation-edge sidewalls (J sswd ) and the bottom junction (J sd ), = ( ) + ( ) + ( ) (11.7) I A J T P J T W NF J T sbd deff sd deff sswd effcj sswgd where the calculation of the junction area and perimeter is discussed in Chapter 11, and the temperature-dependent current density model is given in Chapter 1. In (11.6), f breakdown is given by f breakdown ( ) q BVD+ Vbd = 1+ XJBVD exp NJD kbtnom (11.8) In the above equation, when XJBVD = 0, no breakdown will be modeled. If XJBVD < 0.0, it is reset to 1.0. diomod = 1 (breakdown-free) No breakdown is modeled. The exponential IV term in (11.9) is linearized at the limiting current IJTHSFWD in the forward-bias model only. qv bd Ibd = Isbd exp 1 + Vbd G NJD kbtnom min (11.9) diomod = (resistance-and-breakdown): BSIM4.6.4 Manual Copyright 009 UC Berkeley 91

100 Asymmetric MOS Junction Diode Models Diode breakdown is always modeled. The exponential term (11.10) is linearized at both the limiting current IJTHSFWD in the forward-bias mode and the limiting current IJTHSREV in the reverse-bias mode. qv bd Ibd = Isbd exp 1 fbreakdown + Vbd G NJD kbtnom min (11.10) For diomod =, if XJBVD <= 0.0, it is reset to Total Junction Source/Drain Diode Including Tunneling Total diode current including the carrier recombination and trap-assisted tunneling current in the space-charge region is modeled by: (11.11) I = I bs _ total bs I Vbs VTSSWGS Weffcj NF Jtsswgs ( T) exp 1 NJTSSWG( T ) Vtm0 VTSSWGS Vbs Vbs VTSSWS Ps, deff Jtssws ( T) exp 1 NJTSSW ( T ) Vtm0 VTSSWS Vbs A sdeff, = I J bd _ total bd tss ddeff, Vbs VTSS ( T) exp 1 + g`min V NJTS( T) Vtm0 VTSS Vbs Vbd VTSSWGD Weffcj NF Jtsswgd ( T) exp 1 NJTSSWGD( T ) Vtm0 VTSSWGD Vbd Vbd VTSSWD Pddeff, Jtsswd( T) exp 1 NJTSSWD( T ) Vtm0 VTSSWD Vbd A J tsd Vbd VTSD ( T) exp 1 + g`min V NJTSD( T) Vtm0 VTSD Vbd bs bd (11.1) BSIM4.6.4 Manual Copyright 009 UC Berkeley 9

101 Asymmetric MOS Junction Diode Models 11. Junction Diode CV Model Source and drain junction capacitances consist of three components: the bottom junction capacitance, sidewall junction capacitance along the isolation edge, and sidewall junction capacitance along the gate edge. An analogous set of equations are used for both sides but each side has a separate set of model parameters Source/Body Junction Diode The source-side junction capacitance can be calculated by Cbs = Aseff Cjbs + Pseff Cjbssw + Weffcj NF Cjbsswg (11.13) where C jbs is the unit-area bottom S/B junciton capacitance, C jbssw is the unit-length S/B junction sidewall capacitance along the isolation edge, and C jbsswg is the unit-length S/B junction sidewall capacitance along the gate edge. The effective area and perimeters in (11.13) are given in Chapter 11. if V bs < 0 C jbs is calculated by C otherwise jbs Vbs = CJS( T) 1 PBS T ( ) MJS (11.14) = ( ) + bs C jbs CJS T 1 MJS PBS T V ( ) (11.15) if V bs < 0 C jbssw is calculated by BSIM4.6.4 Manual Copyright 009 UC Berkeley 93

102 otherwise Asymmetric MOS Junction Diode Models C jbssw Vbs = CJSWS( T) 1 PBSWS T ( ) MJSWS (11.16) C jbsswg is calculated by if V bs < 0 otherwise ( ) bs C jbssw = CJSWS T 1+ MJSWS PBSWS T C C jbsswg jbsswg Vbs = CJSWGS( T) 1 PBSWGS T V ( ) Vbs = CJSWGS( T) 1 PBSWGS T ( ) ( ) MJSWGS MJSWGS (11.17) (11.18) (11.19) 11.. Drain/Body Junction Diode The drain-side junction capacitance can be calculated by Cbd = Adeff Cjbd + Pdeff Cjbdsw + Weffcj NF Cjbdswg (11.0) where C jbd is the unit-area bottom D/B junciton capacitance, C jbdsw is the unit-length D/B junction sidewall capacitance along the isolation edge, and C jbdswg is the unit-length D/B junction sidewall capacitance along the gate edge. The effective area and perimeters in (11.0) are given in Chapter 1. if V bd < 0 C jbd is calculated by otherwise C jbd Vbd = CJD( T) 1 PBD T ( ) MJD (11.1) BSIM4.6.4 Manual Copyright 009 UC Berkeley 94

103 Asymmetric MOS Junction Diode Models ( ) C jbdsw is calculated by if V bd < 0 otherwise if V bd < 0 otherwise C bd Cjbd = CJD T 1+ MJD PBD T jbdsw Vbd = CJSWD( T) 1 PBSWD T ( ) V ( ) ( ) MJSWD bd C jbdsw = CJSWD T 1+ MJSWD PBSWD T C jbdswg is calculated by C jbdswg Vbd = CJSWGD( T) 1 PBSWGD T ( ) V ( ) ( ) MJSWGD bd C jbdswg = CJSWGD T 1+ MJSWGD PBSWGD T V ( ) (11.) (11.3) (11.4) (11.5) (11.6) BSIM4.6.4 Manual Copyright 009 UC Berkeley 95

104 Layout-Dependent Parasitics Models Chapter 1: Layout-Dependent Parasitics Models BSIM4 provides a comprehensive and versatile geometry/layout-dependent parasitcs model [15]. It supports modeling of series (such as isolated, shared, or merged source/ drain) and multi-finger device layout, or a combination of these two configurations. This model have impact on every BSIM4 submodels except the substrate resistance network model. Note that the narrowwidth effect in the per-finger device with multi-finger configuration is accounted for by this model. A complete list of model parameters and selectors can be found in Appendix A. 1.1 Geometry Definition Figure 1.1 schematically shows the geometry definition for various source/drain connections and source/drain/gate contacts. The layout parameters shown in this figure will be used to calculate resistances and source/drain perimeters and areas. BSIM4.6.4 Manual Copyright 009 UC Berkeley 96

105 Layout-Dependent Parasitics Models Figure 1.1 Definition for layout parameters. 1. Model Formulation and Options 1..1 Effective Junction Perimeter and Area In the following, only the source-side case is illustrated. The same approach is used for the drain side. The effective junction perimeter on the source side is calculated by BSIM4.6.4 Manual Copyright 009 UC Berkeley 97

106 Layout-Dependent Parasitics Models If (PS is given) if (permod == 0) P seff = PS else Pseff = PS Weffcj NF Else P seff computed from NF, DWJ, geomod, DMCG, DMCI, DMDG, DMCGT, and MIN. The effective junction area on the source side is calculated by If (AS is given) A seff = AS Else A seff computed from NF, DWJ, geomod, DMCG, DMCI, DMDG, DMCGT, and MIN. In the above, P seff and A seff will be used to calculate junction diode IV and CV. P seff does not include the gate-edge perimeter. 1.. Source/Drain Diffusion Resistance The source diffusion resistance is calculated by If (number of source squares NRS is given) = NRS RSH R sdiff Else if (rgeomod == 0) Source diffusion resistance R sdiff is not generated. Else R sdiff computed from NF, DWJ, geomod, DMCG, DMCI, DMDG, DMCGT, RSH, and MIN. where the number of source squares NRS is an instance parameter. Similarly, the drain diffusion resistance is calculated by BSIM4.6.4 Manual Copyright 009 UC Berkeley 98

107 Layout-Dependent Parasitics Models If (number of source squares NRD is given) R ddiff = NRD RSH Else if (rgeomod == 0) Drain diffusion resistance R ddiff is not generated. Else R ddiff computed from NF, DWJ, geomod, DMCG, DMCI, DMDG, DMCGT, RSH, and MIN Gate Electrode Resistance The gate electrode resistance with multi-finger configuration is modeled by Rgeltd = W ( XGW effcj 3 NGCON ) RSHG + ( ) NGCON L XGL NF drawn (1.1) 1..4 Option for Source/Drain Connections Table 1.1 lists the options for source/drain connections through the model selector geomod. geomod End source End drain Note 0 isolated isolated NF=Odd 1 isolated shared NF=Odd, Even shared isolated NF=Odd, Even 3 shared shared NF=Odd, Even 4 isolated merged NF=Odd 5 shared merged NF=Odd, Even 6 merged isolated NF=Odd 7 merged shared NF=Odd, Even 8 merged merged NF=Odd 9 sha/iso shared NF=Even 10 shared sha/iso NF=Even Table 1.1 geomod options. For multi-finger devices, all inside S/D diffusions are assumed shared. BSIM4.6.4 Manual Copyright 009 UC Berkeley 99

108 Layout-Dependent Parasitics Models 1..5 Option for Source/Drain Contacts Table 1. lists the options for source/drain contacts through the model selector rgeomod. rgeomod End-source contact End-drain contact 0 No R sdiff No R ddiff 1 wide wide wide point 3 point wide 4 point point 5 wide merged 6 point merged 7 merged wide 8 merged point Table 1. rgeomod options. BSIM4.6.4 Manual Copyright 009 UC Berkeley 100

109 Temperature Dependence Model Chapter 13: Temperature Dependence Model Accurate modeling of the temperature effects on MOSFET characteristics is important to predict circuit behavior over a range of operating temperatures (T). The operating temperature might be different from the nominal temperature (TNOM) at which the BSIM4 model parameters are extracted. This chapter presents the BSIM4 temperature dependence models for threshold voltage, mobility, saturation velocity, source/drain resistance, and junction diode IV and CV Temperature Dependence of Threshold Voltage The temperature dependence of V th is modeled by KT1L th ( ) th ( ) T V T = V TNOM + KT1+ + KT Vbseff 1 L eff TNOM fb ( ) = ( ) 1 1 V T V TNOM KT fb T TNOM (13.1) BSIM4.6.4 Manual Copyright 009 UC Berkeley 101 (13.) ( ) = ( ) [1 + ( )] (13.3) VOFF T VOFF TNOM TVOFF T TNOM VFBSDOFF T ( ) = VFBSDOFF ( TNOM ) + TVFBSDOFF ( T TNOM ) [1 ] (13.4) 13. Temperature Dependence of Mobility The BSIM4 mobility model parameters have the following temperature dependences depending on the model selected through TEMPMOD. If TEMPMOD = 0,

110 Temperature Dependence Model and UTE ( ) = ( ) ( ) (13.5) U0 T U0 TNOM T TNOM ( ) = ( ) + 1 ( 1) (13.6) UA T UA TNOM UA T TNOM ( ) = ( ) + 1 ( 1) (13.7) UB T UB TNOM UB T TNOM ( ) = ( ) + 1 ( 1) (13.8) UC T UC TNOM UC T TNOM ( ) = ( ) + 1 ( 1) (13.9) UD T UD TNOM UD T TNOM If TEMPMOD = 1 or, and UTE ( ) = ( ) ( ) (13.10) U0 T U0 TNOM T TNOM ( ) = ( )[1+ 1 ( )] (13.11) UA T UA TNOM UA T TNOM ( ) = ( ) + 1 ( 1) (13.1) UB T UB TNOM UB T TNOM ( ) = ( )[1+ 1 ( )] (13.13) UC T UC TNOM UC T TNOM ( ) = ( )[1+ 1 ( )] (13.14) UD T UD TNOM UD T TNOM If TEMPMOD = 3, and UTE ( ) = ( ) ( ) (13.15) U0 T U0 TNOM T TNOM UCS ( T ) = UCS ( TNOM ) ( T TNOM ) UCSTE (13.16) UA1 ( ) = ( ) ( / ) (13.17) UA T UA TNOM T TNOM UB1 ( ) = ( ) ( / ) (13.18) UB T UB TNOM T TNOM UC1 ( ) = ( ) ( / ) (13.19) UC T UC TNOM T TNOM BSIM4.6.4 Manual Copyright 009 UC Berkeley 10

111 Temperature Dependence Model UD1 ( ) = ( ) ( / ) (13.0) UD T UD TNOM T TNOM It is worth pointing out that tempmod=3 only affects the mobility. Other parameters such as Rs and Rd are same as those in tempmod= Temperature Dependence of Saturation Velocity If TEMPMOD = 0, the temperature dependence of VSAT is modeled by ( ) = ( ) ( 1) (13.1) VSAT T VSAT TNOM AT T TNOM If TEMPMOD = 1, the temperature dependence of VSAT is modeled by ( ) = ( )[1 ( )] (13.) VSAT T VSAT TNOM AT T TNOM 13.4 Temperature Dependence of LDD Resistance If TEMPMOD = 0, rdsmod = 0 (internal source/drain LDD resistance) ( ) = ( ) + ( 1) (13.3) RDSW T RDSW TNOM PRT T TNOM ( ) = ( ) + ( 1) (13.4) RDSWMIN T RDSWMIN TNOM PRT T TNOM rdsmod = 1 (external source/drain LDD resistance) ( ) = ( ) + ( 1) (13.5) RDW T RDW TNOM PRT T TNOM ( ) = ( ) + ( 1) (13.6) RDWMIN T RDWMIN TNOM PRT T TNOM and ( ) = ( ) + ( 1) (13.7) RSW T RSW TNOM PRT T TNOM BSIM4.6.4 Manual Copyright 009 UC Berkeley 103

112 Temperature Dependence Model ( ) = ( ) + ( 1) (13.8) RSWMIN T RSWMIN TNOM PRT T TNOM If TEMPMOD = 1, rdsmod = 0 (internal source/drain LDD resistance) RDSW ( T ) = RDSW ( TNOM )[1 + PRT ( T TNOM )] (13.9) ( ) = ( )[1 + ( )] (13.30) RDSWMIN T RDSWMIN TNOM PRT T TNOM rdsmod = 1 (external source/drain LDD resistance) RDW ( T ) = RDW ( TNOM )[1 + PRT ( T TNOM )] (13.31) ( ) = ( )[1 + ( )] (13.3) RDWMIN T RDWMIN TNOM PRT T TNOM ( ) = ( )[1 + ( )] (13.33) RSW T RSW TNOM PRT T TNOM ( ) = ( )[1 + ( )] (13.34) RSWMIN T RSWMIN TNOM PRT T TNOM 13.5 Temperature Dependence of Junction Diode IV Source-side diode The source-side saturation current is given by where = ( ) + ( ) + ( ) (13.35) I A J T P J T W NF J T sbs seff ss seff ssws effcj sswgs ( ) ( ) ( ) ( ) Eg TNOM Eg T T + XTIS ln vt TNOM vt T TNOM Jss ( T) = JSS( TNOM) exp NJS (13.36) (13.37) BSIM4.6.4 Manual Copyright 009 UC Berkeley 104

113 Temperature Dependence Model ( ) ( ) ( ) ( ) Eg TNOM Eg T T + XTIS ln vt TNOM vt T TNOM Jssws ( T) = JSSWS( TNOM) exp NJS and ( ) ( ) Eg TNOM Eg T T + XTIS ln kb TNOM kb T TNOM Jsswgs ( T) = JSSWGS( TNOM) exp NJS where E g is given in Section 1.7. (13.38) Drain-side diode The drain-side saturation current is given by = ( ) + ( ) + ( ) (13.39) I A J T P J T W NF J T sbd deff sd deff sswd effcj sswgd where (13.40) Eg ( TNOM) Eg ( T) T + XTID ln kb TNOM kb T TNOM Jsd ( T) = JSD( TNOM) exp NJD (13.41) Eg( TNOM) Eg ( T) T + XTID ln kb TNOM kb T TNOM Jsswd ( T) = JSSWD( TNOM) exp NJD and ( ) ( ) Eg TNOM Eg T T + XTID ln kb TNOM kb T TNOM J sswgd ( T ) = JSSWGD( TNOM ) exp NJD (13.4) BSIM4.6.4 Manual Copyright 009 UC Berkeley 105

114 Temperature Dependence Model trap-assisted tunneling and recombination current JTWEFF Jtsswgs ( T) = Jtsswgs ( TNOM) + 1 W effcj Eg( TNOM ) T.exp X tsswgs 1 kt B TNOM Eg( TNOM ) T Jtssws ( T) = Jtssws ( TNOM) exp Xtssws 1 kt B TNOM Eg( TNOM ) T Jtss ( T) = Jtss ( TNOM) exp Xtss 1 kt B TNOM JTWEFF Jtsswgd ( T) = Jtsswgd ( TNOM) + 1 W effcj Eg( TNOM ) T.exp X tsswgd 1 kt B TNOM Eg( TNOM ) T Jtsd ( T) = Jtsd ( TNOM) exp Xtsd 1 kt B TNOM T NJTSSWG( T ) = NJTSSWG( TNOM ) 1+ TNJTSSWG 1 TNOM T NJTSSW ( T ) = NJTSSW ( TNOM ) 1+ TNJTSSW 1 TNOM T NJTS( T ) = NJTS( TNOM ) 1+ TNTJS 1 TNOM T NJTSSWGD( T ) = NJTSSWGD( TNOM ) 1+ TNJTSSWGD 1 TNOM T NJTSSWD( T ) = NJTSSWD( TNOM ) 1+ TNJTSSWD 1 TNOM (13.43) (13.44) (13.45) (13.46) (13.47) (13.48) (13.49) (13.50) (13.51) (13.5) T NJTSSWD( T ) = NJTSSWD( TNOM ) 1+ TNJTSSWD 1 TNOM (13.53) BSIM4.6.4 Manual Copyright 009 UC Berkeley 106

115 Temperature Dependence Model T NJTSDT ( ) = NJTSDTNOM ( ) 1+ TNTJSD 1 TNOM (13.54) The original TAT current densities J tsswgs and J tsswgd (i.e., Equ and 13.46) are width independent, while in experiments narrower device shows higher TAT current per width. Here, BSIM 4.6. introduced a new parameter JTWEFF to describe this phenomenon. The backward compatibility is kept when JTWEFF is zero Temperature Dependence of Junction Diode CV Source-side diode The temperature dependences of zero-bias unit-length/area junction capacitances on the source side are modeled by and CJS ( T ) = CJS ( TNOM ) + TCJ ( T TNOM ) (13.55) CJSWS ( T ) = CJSWS ( TNOM ) + TCJSW ( T TNOM ) (13.56) ( ) = ( ) 1+ ( ) (13.57) CJSWGS T CJSWGS TNOM TCJSWG T TNOM The temperature dependences of the built-in potentials on the source side are modeled by and PBS ( T ) = PBS ( TNOM ) TPB ( T TNOM ) (13.58) PBSWS ( T ) = PBSWS ( TNOM ) TPBSW ( T TNOM ) (13.59) PBSWGS ( T ) = PBSWGS ( TNOM ) TPBSWG ( T TNOM ) (13.60) Drain-side diode The temperature dependences of zero-bias unit-length/area junction capacitances on the drain side are modeled by ( ) = ( ) 1+ ( ) (13.61) CJD T CJD TNOM TCJ T TNOM BSIM4.6.4 Manual Copyright 009 UC Berkeley 107

116 Temperature Dependence Model CJSWD ( T ) = CJSWD ( TNOM ) + TCJSW ( T TNOM ) (13.6) and ( ) = ( ) 1+ ( ) (13.63) CJSWGD T CJSWGD TNOM TCJSWG T TNOM The temperature dependences of the built-in potentials on the drain side are modeled by and PBDT ( ) = PBDTNOM ( ) TPB ( T TNOM) (13.64) PBSWD ( T ) = PBSWD ( TNOM ) TPBSW ( T TNOM ) (13.65) PBSWGD ( T ) = PBSWGD( TNOM ) TPBSWG ( T TNOM ) (13.66) 13.7 Temperature Dependences of E g and n i mrtlmod=0 Energy-band gap of Si (E g ) The temperature dependence of E g is modeled by and E g ( TNOM) E g ( T) TNOM = 1.16 TNOM T = 1.16 T Intrinsic carrier concentration of Si (n i ) (13.67) (13.68) The temperature dependence of n i is modeled by ( TNOM ) TNOM TNOM qeg ni = 1.45e10 exp kt B mrtlmod=1 (13.69) BSIM4.6.4 Manual Copyright 009 UC Berkeley 108

117 Temperature Dependence Model Energy-band gap of non-silicon channel (E g ) The temperature dependence of E g is modeled by TBGASUB Tnom Eg0= BG0SUB Tnom + TBGBSUB TBGASUB Eg(300.15) = BG0SUB TBGBSUB TBGASUB Temp Eg = BG0SUB Temp + TBGBSUB (13.70) (13.71) (13.7) Intrinsic carrier concentration of non-silicon channel (n i ) n i 3/ Tnom Eg(300.15) Eg0 = NI0SUB exp vt (13.73) BSIM4.6.4 Manual Copyright 009 UC Berkeley 109

118 Stress Effect Model Chapter 14: Stress Effect Model CMOS feature size aggressively scaling makes shallow trench isolation(sti) very popular active area isolatiohn process in advanced technologies. Recent years, strain channel materials have been employed to achieve high device performance. The mechanical stress effect induced by these process causes MOSFET performance function of the active area size(od: oxide definition) and the location of the device in the active area. And the necessity of new models to describe the layout dependence of MOS parameters due to stress effect becomes very urgent in advance CMOS technologies. Influence of stress on mobility has been well known since the 0.13um technology. The stress influence on saturation velocity is also experimentally demonstrated. Stress-induced enhancement or suppression of dopant diffusion during the processing is reported. Since the doping profile may be changed due to different STI sizes and stress, the threshold voltage shift and changes of other second-order effects, such as DIBL and body effect, were shown in process integration. BSIM4 considers the influence of stress on mobility, velocity saturation, threshold voltage, body effect, and DIBL effect Stress Effect Model Development Experimental analysis show that there exist at least two different mechanisms within the influence of stress effect on device characteristics. The first one is mobility-related and is induced by the band structure modification. The second one is Vth-related as a result of doping profile BSIM4.6.4 Manual Copyright 009 UC Berkeley 110

119 Stress Effect Model variation. Both of them follow the same 1/LOD trend but reveal different L and W scaling. We have derived a phenomenological model based on these findings by modifying some parameters in the BSIM model. Note that the following equations have no impact on the iteration time because there are no voltage-controlled components in them Mobility-related Equations This model introduces the first mechanism by adjusting the U0 and Vsat according to different W, L and OD shapes. Define mobility relative change due to stress effect as : µ eff ρ µ = µ / ( )/ 1 eff eff µ effo = µ eff µ effo µ effo = µ effo (14.1) So, µ µ eff effo = 1+ ρ µ eff (14.) Figure14.1 shows the typical layout of a MOSFET on active layout surrounded by STI isolation. SA, SB are the distances between isolation edge to Poly from one and the other side, respectively. D simulation shows that stress distribution can be expressed by a simple function of SA and SB. Figure 14.1 shows the typical layout of a MOSFET BSIM4.6.4 Manual Copyright 009 UC Berkeley 111

120 Stress Effect Model Figure 14. Stress distribution within MOSFET channel using D simulation Assuming that mobility relative change is propotional to stress distribution. It can be described as function of SA, SB(LOD effect), L, W, and T dependence: KU0 ρ µ eff = Inv sa + Inv sb Kstress _ u0 ( ) (14.3) where: BSIM4.6.4 Manual Copyright 009 UC Berkeley 11

121 Stress Effect Model 1 1 Inv _ sa = Inv _ sb = SA L SB L drawn drawn LKU 0 WKU 0 Kstress _ u0= ( Ldrawn + XL ) ( W + XW + WLOD ) LLODKU 0 WLODKU 0 drawn PKU 0 Tempera LLODKU 0 WLODKU 0 + TKU ( Ldrawn + XL) ( Wdrawn + XW + WLOD) TNOM So that: 1 + ρµ eff ( SA, SB) (14.5) µ eff = µ effo 1 + ρ ( SA, SB ) µ eff ref ref υ sattemp 1+ K VSAT ρµ eff ( SA, SB) (14.6) = υsattempo 1 + K VSAT ρ ( SA, SB ) µ eff ref ref and SA ref, SB ref are reference distances between OD edge to poly from one and the other side Vth-related Equations Vth0, K and ETA0 are modified to cover the doping profile change in the devices with different LOD. They use the same 1/LOD formulas as shown in section(14.1), but different equations for W and L scaling: KVTH0 VTH0 = VTH0 + Inv_ sa+ Inv_ sb Inv_ sa Inv_ sb Kstress_vth0 ( ) STK K = K + Inv _ sa + Inv _ sb Inv _ sa Inv _ sb Kstress_vth0 ETA0 ETA0 original ref ref ( ) original LODK ref ref STETA0 Kstress_vth0 = original + LOD ( Inv sa+ Inv sb Inv saref Inv sbref ) ETA0 (14.7) Where: BSIM4.6.4 Manual Copyright 009 UC Berkeley 113

122 Stress Effect Model (14.8) Kstress vth LKVTH0 = + + WKVTH0 _ 0 1 ( ) LLODKVTH ( ) WLODKVTH Ldrawn + XL Wdrawn + XW + WLOD + PKVTH0 L + XL W + XW + WLOD LLODKVTH WLODKVTH ( drawn ) ( drawn ) (14.9) Multiple Finger Device For multiple finger device, the total LOD effect is the average of LOD effect to every finger. That is(see Figure14.3) for the layout for multiple finger device): Inv _ sa = Inv _ sb = NF NF SA L + i ( SD + L ) i= 0 drawn drawn NF NF SB L + i ( SD + L ) i= 0 drawn drawn Figure 14.3 Layout of multiple finger MOSFET 14. Effective SA and SB for Irregular LOD General MOSFET has an irregular shape of active area shown in Figure 14.3 To fully describe the shape of OD region will require additional instance BSIM4.6.4 Manual Copyright 009 UC Berkeley 114

123 Stress Effect Model parameters. However, this will result in too many parameters in the net lists and would massively increase the read-in time and degrade the readability of parameters. One way to overcome this difficulty is the concept of effective SA and SB similar to ref. [16]. Stress effect model described in Section(14.1) allows an accurate and efficient layout extraction of effective SA and SB while keeping fully compatibility of the LOD model. They are expressed as: n 1 swi 1 = SA L W sa L eff eff drawn i= 1 drawn i drawn n 1 swi 1 = SB L W sb L drawn i= 1 drawn i drawn (14.10) Figure 14.4 A typical layout of MOS devices with more instance parameters (swi, sai and sbi) in addition to the traditional L and W BSIM4.6.4 Manual Copyright 009 UC Berkeley 115