for Submicron CMOS Digital Circuits Antoni Ferre and Joan Figueras Departament d'enginyeria Electronica Universitat Politecnica de Catalunya

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1 On Estimating eakage Power Consumption for Submicron CMOS Digital Circuits Antoni Ferre and Joan Figueras Departament d'enginyeria Electronica Universitat Politecnica de Catalunya Diagonal 647, 828 Barcelona Abstract - The estimation of leakage power consumption of CMOS digital circuits taking into account the input/memory state and process variations is examined. Based on the subthreshold leakage characterization at transistor and cell level, the leakage power consumption of a standard cell circuit is obtained. The dependence of this estimate on the channel lengths and their variation are used to nd the variability of the leakage power consumption and its distribution under dierent statistical assumptions. The model predicts that the P EAK power distribution is asymmetric around the nominal value in agreement with industrial experimental data [1]. A signicant dependence ofp EAK on the input vector has been found. This dependence becomes stronger for circuits with shorter eective channel lengths. Finally, the problem of evaluating worst-case P EAK has been addressed. 1 Introduction In recent years, the trend to increase the density and size of CMOS circuits with stringent performance specs has been driven by the ever growing demand for high speed portable electronic devices. This fact places severe restrictions on size, weight and power in order to guarantee long battery life. The high level of integration implies serious diculties in heat removal which leads, even in the case of non-portable devices, to high costs of cooling and packaging the integrated circuits. These facts have motivated a growing interest in power consumption estimation and low power design of CMOS circuits [2]. As MOSFETs dimensions enter the submicrometer region, the subthreshold currents grow due to scaled down threshold voltages and short-channel eects, such as drain-induced barrier lowering (DIB) [3]. Therefore, the leakage power consumption contribution is expected to grow as the minimum feature size is reduced [4],[]. Thus, 'event-driven' systems triggered by external events with long periods of inactivitymayhave signicant static or leakage power consumption [6],[7]. As an example, Chandrakasan et al., after analyzing traces from X-servers, have found that the processor spends more than 9% of its time in 'standby' [8]. To estimate the leakage power consumption it is necessary to characterize the process technology and its variations. The statistical process variations are due to three main factors: critical dimension variations, channel doping uctuations and lack of uniformity in oxide

2 thickness [9], and have a growing impact on the leakage power consumption. In many technologies, it is known that gate length has the largest impact on subthreshold current variability [6],[1]. The variations due to the channel width spread are negligeable because W is usually chosen to be larger than the minimum value. Of course, the use of longer channel transistors reduces both the leakage current and the eect of the variations in gate length. However, this solution is not always possible since the gain and the speed of the devices decrease. In some cases the device parameter variations are mainly due to random placement of dopant atoms in the channel transistor. These variations and its inuence in leakage current have been studied bytang et al. [11] and Sitte et al. [12] for deep-submicron MOSFET individual devices. In this paper, a model of the leakage power distribution for a CMOS digital circuit is proposed. It is assumed that the variation of subthreshold leakage current is mainly produced by the variations of the channel length through the short-channel eects. The rest of the paper is structured as follows: In Section 2, the parameters inuencing the leakage current are presented. In Section 3 we derive a model for the leakage power variation due to fabrication process. In Section 4, MonteCarlo Simulations using look up tables of library cell P EAK consumption are presented. The problem of evaluating worst-case P EAK is also discussed. Finally, the conclusions of the work will be presented. 2 eakage Power Computation et us consider a CMOS digital circuit with N cells and input vector v and internal state q. The total leakage power consumption is computed as follows: P EAK (v q)=v DD I EAK (v q) (1) where I EAK (v q) is the total leakage current produced in the given input/internal state. The estimation of this leakage current requires information on technology parameters, circuit topology, temperature, power supply, the circuit input and memory state. First of all, it is important to identify the dominant mechanism responsible for the leakage current. The leakage current has two major components: leakage currents which ow from power supply to ground through the transistors which are in 'o-state' due to subthreshold conduction, and leakage current of reverse-biased pn junctions in the circuit. In scaled down technologies the dominant component is usually the subthreshold contribution. et us now review the main characteristics of the subthreshold currents. 2.1 Subthreshold leakage currents When the gate voltage is lower than the threshold voltage and there is some voltage applied between the drain and the source of an MOS transistor, a diusion current appears due to the dierent carrier concentrations at the source and drain terminals. This current depends exponentially on V GS and V DS through the carrier concentrations (similar mechanisms are

3 responsible for current ow in the bipolar transistor). For an NMOS, the subthreshold current is given by [13]: W I N = N C ox V 2 t e V GS;V THN nvt 1 ; e ; V DS Vt where N is the electron carrier mobility, C ox is the gate capacitance per unit area, W is the channel width, is the channel length, V t is the thermal voltage, V THN is the NMOS threshold voltage and n is the subthreshold swing coecient. In a long channel device, the depth of the depletion region at source and drain regions is negligible. However, as channel length is reduced, these depletion regions occupy more space in the channel region. The depletion regions near the source and drain edges are shared with the channel. This eect produces a reduction in the threshold voltage with decreasing channel length and increasing drain-to-source voltage. Therefore, the short-channel eects are modeled by reducing the eective threshold voltage as a function of the drain-to-source voltage (Philips Model): (2) V THN = V THN 1 + u 1 ; u 2 2 (3) where u 1 accounts for the doping redistribution eects owing to oxidation. For p-channel, this eect has a negative sign. The parameter u 2 models the 2-D depletion eect. The draininduced barrier lowering (DIB) is modeled by additionally reducing the eective threshold voltage as a function of the drain to source voltage in the following amount: DIB(V DS )= N V DS = s 2 ( S + V SB ) 1=2 V DS (4) where s is a constant foragiven technology. S is two times the Fermi potential and V SB is the bulk to source voltage. The DIB and short-channel eects imply that eective gate lengths shorter than the nominal value will increase exponentially the leakage current, while larger values of the channel length will tend to lower I EAK values. 2.2 Circuit State Dependence In CMOS circuits, subthreshold currents are generally state-dependent because the conductive paths change as the input vector and/or the memory state vary [14]. To illustrate this variability, let us consider without loss of generality a full complementary CMOS circuit with N two-input NAND gates. The four dierent input cases for the two-input NAND gates are indicated in Figure 1 where the limiting subthreshold current(s) is(are) indicated by one(two) arrow(s). et us analyze these four cases: a) A=, B=. For these inputs two stacked 'o'-state NMOS transistors connect V DD to ground. This case has been analyzed using the model from Gu and Elmasry [14]. The current is given by:

4 " 2 # I = IN exp N V DD () where: IN = N C ox (W=)V 2 t exp ;(V THN 1 + u N1 ; u N2 2 )=() (6) b) A=1, B=. In this case, the current ows through an 'o'-state NMOS transistor connected between an 'on'-state NMOS transistor (which degrades the voltage in the drain of the blocking transistor to V DD ; V THN ) and ground. The I EAK current is: I1 = IN exp " # N (V DD ; V THN ) c) A=, B=1. In this case, the current ows through an 'o'-state NMOS transistor connected between V DD and ground. The I EAK current is: N V DD I1 = IN exp (8) d) A=1, B=1. In this case, the current is the sum of the subthreshold current of the two PMOS transistors: P V DD I11 =2IP exp (9) (7) where: IP = P C ox (W=)V 2 t exp ;(V THP 1 + u P1 ; u P2 2 )=() (1) VDD VDD VDD VDD IP1 IP2 ~ VDD ~ VDD ~ VDD ~ GND A A A I N1 A VDS2 ~ ηvdd VDD - VTHN ~ GND IN2 B IN2 B B B (a) A= B= (b) A=1 B= (c) A= B=1 (d) A=1 B=1 Figure 1. Conductive paths as a function of input vector in a two-input NAND gate.

5 Now let us consider again the whole circuit composed of N two input NAND gates. et N, N1, N1 and N11 denote the number of gates with inputs, 1, 1, 11 for a given input vector v and memory state q. The leakage current I EAK (v q) is expressed in terms of the subthreshold currents given by ()-(1): I EAK = IN + N1 exp " N 2 # VDD N exp N V DD + N1 exp + P V DD " #! N (V DD ; V THN ) + IP (2 N11) exp (11) As N 1, the leakage current is approximated by: I EAK = I N N + N 1 exp N V DD + N 1 exp N (V DD ; V THN ) + I P (2 N 11 ) exp P V DD (12) In a circuit with inverters, NAND, NOR, XOR gates and other library cells, the same method applies. The global circuit leakage current, I EAK (v q) for each input vector, v, and memory state, q, is expressed in terms of I EAK i, the leakage current of cell #i, i2 (1 2 ::: N), with inputs x i 1 xi 2 ::: xi ni and memory state, qi 1 qi 2 ::: qi mi : NX I EAK (v q)= i=1 h I EAKi (x i 1 ::: xi ni qi 1 ::: qi mi )i (13) A logic simulator (system HIO) has been used to obtain the input values, x i 1 xi 2 ::: xi, ni and the memory state, q1 i qi 2 ::: qi, of the cells in the circuit. To obtain the I mi EAKi consumption for each cell in the circuit we have used a set of look-up tables previously computed as for the two-input NAND gate indicated before. 3 Dependence of subthreshold currents on process variations. et us consider a well-characterized submicron technology (in our case, we use a. m technology). As mentioned above, in our statistical model we have assumed that the variation of the subthreshold leakage current is mainly produced by the variations of the channel length through the short-channel and DIB eects. Thus, small changes in the channel length cause changes in the value of the threshold voltage depending on ef f and V DS,as discussed above. This implies a variation of the leakage current in one cell depending on the state of this cell, as shown in the previous section. Tables I(a) and I(b) give thevariations of I EAK for a two-input NAND and NOR gates with a nominal eectivevalue ef f =:4m.

6 TABE I(a). IEAK currents in a two-input NOR depending on its inputs and poorly controlled eff. I EAK [ 1 pa] ef f [m] (nom.) TABE I(b). IEAK currents in a two-input NAND depending on its inputs and poorly controlled eff. I EAK [ 1pA] ef f [m] (nom.) Therefore, the eect of the input vector strongly depends on the channel length through the DIB eect and, of course, it depends on the asymmetry of NMOS and PMOS transistors. For large channel lengths, the eect of the input vector and the internal state is reduced. For reduced channel lengths, the I EAK dierences between states grow. Now let us consider a large CMOS circuit and let us x the circuit inputs and internal state, i.e., the values of the input vector and the memory registers (if any). Then, the cells are in dierent states of consumption depending on their inputs and/or their state. For example, let us consider two dierent input vectors for the ISCAS'8 C6288 CMOS circuit. This circuit has 1112 transistors. The rst vector is "Mostly s" while the other vector is "Mostly 1s". Tables II(a) and II(b) show the internal cell states for the two vectors. In order to obtain the P EAK distribution, dierent joint distributions and partial correlations between transistors are considered: local, or intra-die, variations and global, or inter-die, variations. It has been found that, for conventional power supply voltages, i.e. V DD > (3 4) V TH, only inter-die parameter variations are to be considered in digital designs [9]. The impact of intra-die variations where each device in the chip is aected dierently, is regarded to be negligible. Thus, in our statistical model, we assume that the process variations are locally correlated, i.e., inside the chip all the NMOS (PMOS) transistors have the same length deviation. Under these circumstances, the leakage current for each possible pair value of channel length ( N, P ) has been computed using Expression (13). The results are shown in Figures 2(a) and 2(b) P_EAK [uw] 1. P_EAK [uw] N [um] P [um] N [um] P [um].4.3 (a) (b) Figure 2. PEAK as a function of channel lengths (N, P ) for the two experimented vectors. (a) 'Mostly 1s', (b) 'Mostly s'.

7 TABE II(a). Circuit C6288 internal cell states for the 'Mostly 1s' vector. No Gates Input NOT NOR AND 16 x x 1 16 x x x 74 1 x 48 1 x 7 11 x TABE II(b). Circuit C6288 internal cell states for the 'Mostly s' vector. No Gates Input NOT NOR AND 16 x x 1 16 x x x x 94 1 x x The correlation between NMOS and PMOS transistors depends on the particular technology. Examining dierent technologies, we have found dierent correlation coecients ranging from.96 to nearly. We have not observed any negative correlations. To study the dierent possibilities we will analyze three dierent cases: r=, r=.6 and r=1 where r is the correlation coecient between the channel length of NMOS and PMOS transistors. 4 P EAK Distributions of CMOS circuits. et us consider again the ISCAS'8 C6288 CMOS circuit and the two already mentioned input vectors. To determine the P EAK distribution, based on typical, random uctuations of the processing parameters (in particular of the channel length) we have simulated the circuit considering dierent channel lengths generated with the parameters mentioned above. A sample of the generated distributions for r= and r=.6 is shown in Figures 3(a) and 3(b). The case r=1 corresponds to a straight line from ( NMIN, PMIN )to( NMAX, PMAX ).. r=.6. r=.. P [um].4 P [um] N [um] (a) N [um] (b) Figure 3. Generated (N, P ) pairs. (a) r=.6, (b) r=. In this way, the histograms of the P EAK for the dierent caseswere determined. The P EAK distributions are shown in Figures 4-6.

8 P_EAK [nw] (a) P_EAK [nw] (b) Figure 4. PEAK consumption histogram for the C6288 circuit for the two experimented vectors and r =1. (a) 'Mostly 1s', (b) 'Mostly s' P_EAK [nw] (a) P_EAK [nw] (b) Figure. PEAK consumption histogram for the C6288 circuit for the two experimented vectors and r =. (a) 'Mostly 1s', (b) 'Mostly s' P_EAK [nw] (a) P_EAK [nw] (b) Figure 6. PEAK consumption histogram for the C6288 circuit for the two experimented vectors and r =:6. (a) 'Mostly 1s', (b) 'Mostly s'. First of all, note that the P EAK distributions obtained are shown to be predominantly asymmetric around the mean values. This asymmetry is strongly inuenced by the degree of short-channel and DIB present in the devices. In fact, large values of the channel length will make P EAK tend to a lower constant value, while eective gate lengths shorter than the nominal value will present ap EAK consumption with an exponential tail.

9 Notice also the strong dependence of P EAK on the input vector especially when the process skews toward short channel devices. The eect of the correlation between the transistors is clear from the obtained results. As r!, the best and worst performance corners, ( NMIN, PMIN )and( NMAX, PMAX )become more unlikely and, therefore, the histogram is 'compressed'. In order to set the worst-case P EAK, let us analyze the correspondence of the P EAK consumption and channel length distributions. If we restrict ourselves to the case r = 1, which can be solved analitically, the dependence for a circuit state of P EAK consumption on channel length,, is obtained by adding the P EAK contributions of each cell as a function of one random variable. This function, P EAK = '() is indicated in Figure 7. Yield oss D ϕ() PEAK Yield oss P EAK Figure 7. P EAK - Distribution Mapping. The Gaussian distribution of channel lengths causes, due to the '() mapping, the distribution of P EAK consumption as indicated in Figure 7. Note the asymmetry of the P EAK distribution and the amplication of the region of currents mapped in the reduced channel lengths region as found in MonteCarlo simulations. An acceptable worst-case, PEAK, corresponds to a maximum acceptable value of deviation from the mean, D which can be obtained from the Gaussian distribution for. If the worst-case PEAK is set corresponding to a deviation of D equal to or larger than 3 (D 3 ) then about.1 of the fabricated batches are expected to fail because of parameter variations. The yield loss upper bounds for a set of worst-case P EAK equal to or greater than a given value are shown in Table III. TABE III. Worst-case IEAK and Yield oss. Worst-Case Yield oss % P EAK [W] "Mostly s" "Mostly 1s" If this leakage power consumption is too high for the performance requirements, there are dierent solutions. The rst is the use of multithreshold-voltage CMOS circuits, featuring

10 both low-v TH and high-v TH in a single chip []. Other possible solution is to lengthen devices in selected areas of the chip, such as cache arrays or pad drivers [16]. Summary This paper studies the variations in leakage power consumption due to fabrication process and circuit state and their inuence on P EAK current distribution. The proposed model predicts that the leakage current distribution with dominant subthreshold currents is shown to be predominantly asymmetric around the mean values. Industry data supports this fact [1]. This asymmetry is inuenced strongly by the short channel and DIB eects present in the circuit devices. The inuence of the input vector and the memory state has also been analyzed. Finally, the problem of evaluating worst-case P EAK consumption has been discussed. Acknowledgment This work has been partially supported by the CICYT project TIC and by the CIRIT Project Ref. 199 SGR 192. References [1] D. Josephson, M. Storey, and D. Dixon. "Microprocessor IDDQ Testing: A Case Study". IEEE Design & Test of Computers, 12:42{2, Summer 199. [2] A.P. Chandrakasan and R.W. Brodersen. "ow Power Digital CMOS Design". Kluwer Academic Publishers, 199. [3] C.A. Mead. "Scaling of MOS Technology to Submicrometer Feature Sizes". Analog Integrated Circuits and Signal Processing, 6(1):9{2, [4] B. Davari, R.H. Dennard, and G.G. Shahidi. "CMOS Scaling for High Performance and ow Power-The Next Ten Years". Proceedings of the IEEE, 83(4):9{66, April 199. [] D. iu and C. Svenson. Trading speed for low power by choice of supply and threshold voltages. IEEE Journal of Solid-State Circuits, 28(1):1{17, January [6] D. Dobberpuhl. "The Design of a High Performance Microprocessor". In Proceedings of the 1996 International Symposium on ow Power Electronics and Design, pages 11{16, Monterrey, [7] A.Bellaouar and M.I. Elmasry. "ow-power Digital VSI Design". Kluwer Academic Publishers, 199. [8] A. Chandrakasan, I. Yang, C. Vieri, and D. Antoniadis. "Design Considerations and Tools for ow-voltage Digital System Design". In Proceedings of the 33th ACM/ IEEE Design Automation Conference, pages 728{733, [9] A.J. Strojwas, M. Quarantelli, J. Borel, C. Guardiani, G. Nicollini, G. Crisenza, B. Franzini, and J. Wiart. "Manufacturability ofowpower CMOS Technology Solutions". In Proceedings of the 1996 International Symposium on ow Power Electronics and Design, pages 22{232, Monterrey, [1] I.C. Kizilyalli et al. "High Performance 3.3- and -V. -m CMOS Technology for ASIC's". IEEE Transactions on Semiconductor Manufacturing, 8(4):44{448, November 199. [11] X. Tang, V.K. De, and J.D. Meindl. "Eects of Random MOSFET Parameter Fluctuations on Total Power Consumption". In Proceedings of the 1996 International Symposium on ow Power Electronics and Design, pages 233{236, Monterrey, [12] R. Sitte, S. Dimitrijev, and H.B. Harrison. "Device Parameter Changes Caused by Manufacturing Fluctuations of Deep Submicron MOSFET's". IEEE Transactions on Electron Devices, 41(11):221{22, November [13] G. Massobrio and P. Antognetti. "Semiconductor Device Modeling with SPICE". McGraw-Hill, [14] R.X. Gu and M.I. Elmasry. "Power Dissipation Analysis and Optimization of Deep Submicron CMOS Digital Circuits". IEEE Journal of Solid-State Circuits, 31():77{713, May [] S. Mutoh et al. "A 1-V Multithreshold-Voltage CMOS Digital Signal Processor for Mobile Phone Application". IEEE Journal of Solid-State Circuits, 31(11):179{182, November [16] J. Monatanaro et al. "A 16-MHz, 32-b,.-W CMOS RISC MicroProcessor". IEEE Journal of Solid-State Circuits, 31(11):173{1714, November 1996.