Objectives for Energy Reduction

Transcription

1 genda Introduction, challenges and objectives Wireless (ody) Sensor Networks pplications, system requirements Generic architecture of a WSN node Processor and radio transceiver performance Examples of WSN for health-care applications Energy efficient protocols (Rx) MC layer Energy optimization of Tx power Error control (LINK layer), cooperation strategies (PHY layer) Energy Harvesting Energy/power estimation and optimization Watt is the problem? Power issues in CMOS digital chips? How to estimate and reduce power of hardware and software? Trends in energy-efficient computer architectures 1 Objectives for Energy Reduction How can we design an energy-efficient platform for wireless sensor networks? Platform = software + hardware + protocols (3) Power optimization of the hardware Dynamic power management Ultra low-power sleep modes Optimize hardware and software Co-processing Digital 2 Olivier Sentieys 1

2 Energy/power estimation and reduction 1. Why care about power? Heat dissipation Limited energy in portable systems 2. Sources of power consumption in CMOS chips? Transistors and logic gates Static and dynamic power 3. How to estimate power? ctivity, probability 4. How to reduce power? In hardware and software 5. Trends in energy-efficient computer architectures 3 nd then came the Power Wall Power Density: 100 W/chip (~25W/cm 2 ) is a limit Source: C. atten, Cornell 4 Olivier Sentieys 2

3 and the Multicore Era Source: C. atten, Cornell 5 Power Density Sun s Surface Power Density (W/cm 2 ) Nuclear Reactor Hot Plate Rocket Nozzle P6 Pentium Year ~25 W/cm 2 Source: Intelâ 6 Olivier Sentieys 3

4 Heat Dissipation Undesirable effects Decrease in performance and reliability MTF/2 every +10 C Increase in cost (cooling) 1 /W when >40W Increase in volume and weight heat-sink, fan, batteries, 7 Energy/power estimation and reduction 1. Why care about power? Heat dissipation Limited energy in portable systems 2. Sources of power consumption in CMOS chips? Transistors and logic gates Static and dynamic power 3. How to estimate power? ctivity, probability 4. How to reduce power? In hardware and software 5. Trends in energy-efficient computer architectures 8 Olivier Sentieys 4

5 Power Consumption in Silicon Chips Chips, logic gates and transistors S C i Intel s Xeon Chip P i = i.f i.c i.vdd 2 + I leaki.vdd P = X i i.f i.c i.vdd 2 + I leaki.vdd 9 MOS Transistors to Vdd Vgsn Ids D Vdd G NMOS NMOS on Vgs S Vss Threshold Voltage Vtn > 0 (0.2 to 0.4V) NMOS ON: Vgs > Vtn NMOS OFF: Vgs < Vtn Vtn Vss NMOS off Source W Gate channel Oxyde N/P Diffusion L tox Drain Vgs Si Diffusion G Gate PolySi W D S L 10 Olivier Sentieys 5

6 NMOS Parasitic Elements G NMOS Enhancement Polysilicon luminum C GS C GD S D C S C G C D 1 Drain-Source Resistance:R DS = K(Vdd Vt) = 1 L k(vdd Vt) W Gate Capacitor:C g = ε.w.l tox = W.L.C ox Drain/Source-ulkCapacitor:C sb = C db W.L.C j Delay: τ = R DS C g = L 2 µ(vdd Vt) 11 Technology Scaling Scaling factor: s etween two successive generations: s # nm 180 nm 130 nm Device dimensions : W, L, tox, junction depth Transistor area (W.L) s 2 Capacitance per unit area : Cox Capacitances : C=WLCox Vdd, Vt Gate delay Dennard s Scaling s 1/s s s s Power/gate s 2 Power.delay product s 3 Power density 1 12 Olivier Sentieys 6

7 Combinatorial Logic Cells Complementary Logic (CMOS) E Logic Cell S = f(e) CMOS Inverter Vdd Id Rp E S E = 0 S = 1 E = 1 = 0 Vss Rn CL 13 Combinatorial Logic Cells NND S S NOR S S S S 14 Olivier Sentieys 7

8 Power Equations in CMOS Dynamic power: Pdyn P = Pdyn + Psc + Ps Charge and discharge of circuit capacitance Short circuit power: Psc Short circuit path in logic cells (Vdd è Vss) during commutation Strongly depends on rising time and on Vth (NMOS/PMOS) Static power: Ps Sub-threshold leakage current (~OFF) Source/Drain-ulk junction leakage (diodes) 15 Static power (1) Sub-threshold Leakage Current Even if Vgs < Vt MOS transistors MOS are not completely off If Vdd decreases (towards Vt) leakage currents increase quickly Source/Drain-ulk junction leakage (diodes) Ioff Ps = N Negligible as Vdd >> Vt Tr I off = I 0 e. Vdd. I0. e VT n* U T VT n* U T 16 Olivier Sentieys 8

9 Static power(2) Impact of threshold voltage Recent technologies use transistors with 2 Vt Low-Leakage or High-Performance cells 17 Dynamic power Vdd Idd = Icc + Ic Vin Icc Ic Cl Icc Vout Ic Energy per transition = C L Vdd 2 Pdyn = a.f.c L.Vdd 2 (Ic) a: activity, C L : total load capacitance, f : frequency Power Data dependent ctivity dependent 18 Olivier Sentieys 9

10 Power Equations in CMOS P = α f C L V DD2 + V DD I peak (P P 1 0 ) + V DD I leak Dynamic power ( 40-70% today and decreasing relatively) Short-circuit power ( 10% today and decreasing absolutely) Leakage power ( 20-50% today and increasing) energy P = rate + static operation power 19 Energy/power estimation and reduction 1. Why care about power? Heat dissipation Limited energy in portable systems 2. Sources of power consumption in CMOS chips? Transistors and logic gates Static and dynamic power 3. How to estimate power? ctivity, probability 4. How to reduce power? In hardware and software 5. Trends in energy-efficient computer architectures 20 Olivier Sentieys 10

11 Dynamic power is data dependant Transition probability of a NOR gate P =P(=1); P =P(=1) P 1 =P(S=1)=(1-P )(1-P ) P 0 1 = P 0.P 1 =(1-(1-P )(1-P )) (1-P )(1-P ) S S S 21 Transition probabilities Probability propagation C P() = ½ P() = ½ P(C) = ½ X S P(X =1) = 1/4 P(S = 1) = 1/2. 3/4 = 3/8 ax = P(X=0). P(X=1) = (1-P(X=1)). P(X=1) = (1 1/4). 1/4 = 3/16 as = P(S=0). P(S=1) = (1 P(S=1)). P(S=1) = (1 3/8). 3/8 = 5/8.3/8 = 15/64 22 Olivier Sentieys 11

12 Transition probabilities Re-convergence: conditional probabilities C X Z P(Z=1) = P(=1) x P(X=1 =1) ecomes quickly complex! 23 Logic-Level Estimation Two techniques Statistical Estimation Quality of testbench is crucial! Input Stimuli Gate-level Simulation Input ctivity Node ctivity Monitoring ctivity Propagation verage nalysis Power Report Probabilistic Estimation 24 Olivier Sentieys 12

13 Energy/power estimation and reduction 1. Why care about power? 2. Sources of power consumption in CMOS chips? 3. How to estimate power? 4. How to reduce power? Reducing static power/leakage Reducing Vdd Reducing activity and glitches Software estimation and optimization System-level optimisation 5. Trends in energy-efficient computer architectures 25 How to reduce power? P dyn = a. Cl. Vdd 2. f Reduce (as low as possible) Vdd Minimize effective capacitance Ceff = a Cl Trade-off performance against power by playing with clock frequency f nd do not forget leakage! How? Well just need to reduce a, Cl, Vdd and f! 26 Olivier Sentieys 13

14 Leakage Power Optimization: Power Gating Objective Reduce leakage currents by inserting a switch transistor (usually high Vth) into the logic stack (usually low Vth) Switch transistors change the bias points (VS) of transistors Most effective for systems with standby operational modes 1 to 3 orders of magnitude leakage reduction possible ut switches add many complications Vdd Vdd Vdd Logic Cell sleep Switch Cell Virtual Vdd Logic Cell Virtual Ground Logic Cell sleep Switch Cell 27 Power estimation and reduction 1. Why care about power? 2. Where does power go in CMOS chips? 3. How to estimate power? 4. How to reduce power? How and at which level? Reducing static power/leakage Reducing Vdd Reducing activity and glitches 5. Software estimation and optimization 6. System-level optimisation 7. Conclusions 28 Olivier Sentieys 14

15 Reducing Vdd Relative Delay td Vdd has a quadratic effect on power Propagation delay increases if Vdd is reduced but power delay product still increases Supply voltage (VDD) Relative Pdyn Delay (t d ) and dynamic power (P dyn ) are functions of V DD P dyn =.C L.V dd 2.f t d = C L.V dd Ids C L.V dd = k W L (Vdd Vt)2 1 t d / <2 Vdd 29 Reducing Vdd Compensate for Vdd reduction, which decreases performance, by architectural optimizations Example: 16-bit architecture of a Viterbi decoder Tclk Tclk C + > < P ref = a. C ref. V ref2. F ref C ref = S C i Tclk 30 Olivier Sentieys 15

16 Parallel rchitecture 2 Tclk 2 Tclk 2 Tclk C + 2 Tclk + > < > < M U X Tclk Relative Delay td V par V ref Supply voltage (VDD) Relative Pdyn 2 Tclk C 2 Tclk P par = (2.15C ref ). V par2. (0.5F ref ) 2. V ref 2 Gain = = = 2.7 V par x x Pipelined rchitecture P pip = (1.15C ref ). V pip2. F ref Tclk Tclk C + Tclk Tclk Tclk > < V ref 2 Gain = = = 2.5 V pip x 1.15 rea advantage for pipeline! Pipelined/Parallel rchitecture Divide power by 5 at the cost of doubling area 32 Olivier Sentieys 16

17 Operator Isolation ctivate FUs only when necessary Instr. Reg. Instr. Reg. MUL DD DD Reg MUL Latch Reg The multiplier consumes energy even is unsed Multiplier inputs are latched when unused Isolate op. inputs from buses 33 Pre-computation (1) Principle: avoid use of power-hungry blocks when results can be pre-computed by a lesshungry one Comput. lock S Pre-comp 34 Olivier Sentieys 17

18 Pre-computation (2) Example: comparator > Clk D Q Reg > D Q Reg Clk D Q Reg Clk 35 Pre-computation (3) Example: comparator > If the 2 MSs are equal, then subtraction is needed Otherwise, result is MS of What is the average gain? D Q Reg > 1 0 D Q [MS] [MS] Clk Gated Cell [MS] D Q Reg D Q D Q =1 if [MS] == [MS] Clk Clk 36 Olivier Sentieys 18

19 ctivity Reduction us encoding to reduce activity e.g. bus between cache memory and processor objective: reduce number of transitions e.g. activity of binary > activity of gray Encoding Logic Decoding Logic > < Input ctivity us ctivity Output ctivity 37 Resource Sharing Resource sharing reduces area but increases activity destructs data correlation us Multiplexing Nbt: Number of bus transitions per cycle Counter 1 Counter 2 us 1 us 2 Counter 1 Counter 2 MUX us Nbt = 2(1+1/2+1/4+...) = 4 Nbt >= 4 (depends on counter skew) 38 Olivier Sentieys 19

20 Energy/power estimation and reduction 1. Why care about power? 2. Sources of power consumption in CMOS chips? 3. How to estimate power? 4. How to reduce power? Reducing static power/leakage Reducing Vdd Reducing activity and glitches Software estimation and optimization System-level optimisation 5. Trends in energy-efficient computer architectures 39 Energy Cost in a Processor Fetching operands costs more than computing 64-bit DP 20pJ 26 pj 256 pj 16 nj DRM Rd/Wr 256-bit buses 256-bit access 8 k SRM 50 pj 500 pj Efficient off-chip link 1 nj 28nm CMOS [Dally, IPDPS 11] 40 Olivier Sentieys 20

21 Reducing Energy of Software Embedded software determines power/energy consumed by the processor So why not modifying software to reduce energy? Energy, power or performance? Energy = battery life-time Power = supply voltage distribution sizing, heat dissipation NOP MOV X,CX MOV DX,[X] MOV X,CX MOV X,DX MOV DX,[X] NOP NOP NOP NOP MOV X,DX NOP Power: 1.15 W Energy: J Power: O.99 W Energy: J 14% less 158% more 41 Memory: Closer is etter Place data which are accessed frequently in internal memory or in registers Minimize memory size (for leakage) by maximizing data reuse Scratchpad Registers CPU Cache Mem ext vailable Memory Space 42 Olivier Sentieys 21

22 Reducing Energy of Software Performance = use of memory bandwidth Energy = use of registers or scratchpad memory, reduce activity LDR r3, [r2, #0] DD r3,r0,r3 MOV r0,#28 LDR r0,[r2,r0] DD r0,r3,r0 DD r2,r2,#4 DD r1,r1,#1 CMP r1,#100 LT LL cycles uj int a[1000]; c=a; for (i=1; i<100; i++) { b += *c; b += *(c+7); c+=1; } 2231 cycles uj DD r3,r0,r2 MOV r0,#28 MOV r2,r12 MOV r12,r11 MOV r11,r10 MOV r0,r9 MOV r9,r8 MOV r8,r1 LDR r1,[r4,r0] DD r0,r3,r1 DD r4,r4,#4 DD r5,r5,#1 CMP r5,#100 LT LL3 43 Energy/power estimation and reduction 1. Why care about power? 2. Sources of power consumption in CMOS chips? 3. How to estimate power? 4. How to reduce power? Reducing static power/leakage Reducing Vdd Reducing activity and glitches Software estimation and optimization System-level optimisation 5. Trends in energy-efficient computer architectures 44 Olivier Sentieys 22

23 Dynamic Power Management (DPM) Reduce speed (clock freq.) and Vdd depending on processor activity (and therefore input data) e.g. MPEG4 coder E=CV H2 +E idle Processor Speed efore IDLE E=CV L 2 fter Time 45 DPM Example: TransMeta Crusoe Crusoe processor: x86 clone running at 700 MHz max Processor activity detection by HW monitors OS adjusts F clock and Vdd Fclock MHz Vdd Power V 100% V 41% V 25% 46 Olivier Sentieys 23

24 DPM Example: TransMeta Crusoe % of max powerl consumption Typical operating region Peak performance region Mhz 0.80 V 433 Mhz 0.87 V 533 Mhz 0.95 V 667 Mhz 1.05 V Frequency (MHz) 800 Mhz 1.15 V 900 Mhz 1.25 V 1000 Mhz 1.30 V Source: Transmeta 47 DPM Example: TransMeta Crusoe Source: Transmeta 48 Olivier Sentieys 24

25 DPM Example: TransMeta Crusoe 49 Conclusions Power consumption needs to be estimated and optimized at each abstraction level Reduce supply voltage (Vdd) while keeping performance acceptable Reduce activity of internal and external signals smart design will always consume less power So design with your brain on! 50 Olivier Sentieys 25

26 Energy/power estimation and reduction 1. Why care about power? 2. Sources of power consumption in CMOS chips? 3. How to estimate power? 4. How to reduce power? Reducing static power/leakage Reducing Vdd Reducing activity and glitches Software estimation and optimization System-level optimisation 5. Trends in energy-efficient computer architectures 51 Technology Scaling Thin Silicon Channel 28 nm 20 nm 14 nm Classical (Dennard s) scaling Device count S 2 Device frequency S Capacitance, Vdd 1/S Device power 1/S 2 Utilization 1 Core i 100W@f Core i 50W@1.4.f 52 Olivier Sentieys 26

27 End of Dennard s Scaling Energy efficiency is not scaling along with integration capacity Leakage limited scaling Device count S 2 Device frequency S Device power (cap) 1/S Device power (V dd ) ~1 Utilization 1/S 2 Core i 100W@f Core i 100W@1.4.f (w/o) leakage ut voltage scaling is still possible for energy efficiency! 1 core@2ghz@1.2v@1w 2x [1 core@1ghz@0.8v@0.22w] 53 Multicore and Dark Silicon Speedup Historical Scaling ITRS Scaling Realistic Scaling [Esmaeilzadeh et al., ISC 11] 18x 7.9x 3.7x Dark Silicon 0 45nm 32nm 22nm 16nm 11nm 8nm 1% 17% 36% 40% 51% Replace dark cores with specialized cores (10-100x more energy efficient) 54 Olivier Sentieys 27

28 3D FinFET Transistors (Intel) t 22nm transistors go 3D 55 fight against FDSOI Transistors (ST) Ultra Thin ody (FD) SOI Total dielectric isolation Lower S/D capacitances & leakages Latch-up immunity Improved VT variation gate Thin Silicon Channel Thin Silicon film 28nm bulk FDSOI nm bulk FDSOI 2014 STMicro s roadmap 14nm Olivier Sentieys 28

29 Chips go 3D! HETSINK ULK Tier 4 3D Integrated Circuits Stack Multiple Dies Micro-bumps Micro-bumps Micro-bumps umps TSVs TSVs I/Os + Power TSVs METL LYERS ULK Tier 3 ULK Tier 2 METL LYERS METL LYERS Tier 1 ULK PCKGE alls Wire Length Reduction Replace long, high capacitance wires by TSVs Low latency, low energy, high bandwidth Heterogeneous Integration Image Sensors, Sensor Network Nodes Processor + Memory PRINTED CIRCUIT 57 Olivier Sentieys 29