EECE488: Analog CMOS Integrated Circuit Design. Introduction and Background

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1 EECE488: Analo CMOS Interated Circuit Desin Introduction and Backround Shahriar Mirabbasi Departent of Electrical and Coputer Enineerin University of British Colubia Technical contributions of Pedra Lajevardi in revisin the slides is reatly acknowleded.

2 Markin Assinents 0% (4 to 6) Midter 5% Project 5% Final Exa 50%

3 References Main reference: Lecture notes Recoended Textbook: Behzad Razavi, Desin of Analo CMOS Interated Circuits, McGraw- Hill, 00 Soe other useful references: T. Chan Carusone, D. Johns and K. Martin, Analo Interated Circuit Desin, nd Edition, John Wiley, 0 P. Gray, P. Hurst, S. Lewis, and R. Meyer, Analysis and Desin of Analo Interated Circuits, 5 th Edition, John Wiley, 009 D. Holber and P. Allen, CMOS Analo Circuit Desin, 3 rd Edition, Oxford University Press, 0 R. Jacob Baker, CMOS Circuit Desin, Layout, and Siulation, 3 rd Edition, Wiley-IEEE Press, 00 A. Sedra and K.C. Sith, Microelectronic Circuits, 5 th or 6 th Edition, Oxford University Press, 004, 009 Journal and conference articles includin IEEE Journal of Solid-State Circuits and International Solid-State Circuits Conference 3

4 Fun to Check Willia F. Brinkan, Doulas E. Haan, and Willia W. Troutan, A History of the Invention of the Transistor and Where It Will Lead Us, IEEE Journal of Solid-State Circuits, volue 3, no., Deceber 997, pp Boris Murann, Diitally Assisted Analo Circuits, IEEE Micro, vol. 6, no., pp , Mar Interestin CAD Tools by Dr. Michael Perrott and his roup: 4

5 Why Analo? Most of the physical sinals are analo in nature! Althouh diital is reat we need an analo interface to convert physical sinals fro analo to diital Also, in soe application after processin the sinals in diital doain, we need to convert the back to analo. Thus in any applications analo and ixed-sinal circuits are the perforance bottlenecks. Also with constant process iproveents the boundary of between hih-speed diital and analo circuits becoes ore and ore fuzzy! That is why analo and ixed-sinal desiners are still and hopefully will be in deand for the foreseeable future. 5

6 Data Converter Typical Real World Syste AFE DSP Exaple: G Filter ADC DSP 6

7 Intel s Tick-Tock Model Tick (process technoloy advanceent), Tock (new icroarchitecture) 7

8 Intel 45 n Process 8

9 Backround. Suested Readin. Structure of MOS Transistors 3. Threshold oltae 4. Lon-Channel Current Equations 5. Reions of Operation 6. Transconductance 7. Second-Order Effects 8. Short-Channel Effects 9. MOS Layout 0.Device Capacitances.Sall-sinal Models.Circuit Ipedance 3.Equivalent Transconductance 9

10 Suested Readin Most of the aterial in this set are based on Chapters, 6, and 7 of the Razavi s book: Desin of Analo CMOS Interated Circuits Many of the fiures in this set are fro Desin of Analo CMOS Interated Circuits, McGraw-Hill, 00, unless otherwise noted. 0

11 Transistor Transistor stands for Transistor are seiconductor devices that can be classified as Bipolar Junction Transistors (BJTs) Field Effect Transistors (FETs) Depletion-Mode FETs or (e.., JFETs) Enhanceent-Mode FETs (e.., MOSFETs)

12 Siplistic Model MOS transistors have three terinals: Gate, Source, and Drain The voltae of the Gate terinal deterines the type of connection between Source and Drain (Short or Open). Thus, MOS devices behave like a switch G hih G low NMOS Device is ON D is shorted to S Device is OFF D & S are disconnected PMOS Device is OFF D & S are disconnected Device is ON D is shorted to S

the. MOS devices have in fact 4 terinals: Source, Drain, Gate,

13 Physical Structure - Source and Drain terinals are identical except that Source provides chare carriers, and Drain receives the. MOS devices have in fact 4 terinals: Source, Drain, Gate, Substrate (bulk) Microelectronic Circuits, 004 Oxford University Press 3

14 Physical Structure - Chare Carriers are electrons in NMOS devices, and holes in PMOS devices. Electrons have a hiher obility than holes So, NMOS devices are faster than PMOS devices We rather to have a p-type substrate?! L D : Due to Side Diffusion Poly-silicon used instead of Metal for fabrication reasons Actual lenth of the channel (L eff ) is less than the lenth of ate 4

15 Physical Structure - 3 N-wells allow both NMOS and PMOS devices to reside on the sae piece of die. As entioned, NMOS and PMOS devices have 4 terinals: Source, Drain, Gate, Substrate (bulk) In order to have all PN junctions reverse-biased, substrate of NMOS is connected to the ost neative voltae, and substrate of PMOS is connected to the ost positive voltae. 5

16 MOS transistor Sybols: Physical Structure - 4 In NMOS Devices: electron Source Drain Current flows fro Drain to Source hole In PMOS Devices: Source Drain Current flows fro Source to Drain Current flow deterines which terinal is Source and which one is Drain. Equivalently, source and drain can be deterined based on their relative voltaes. 6

17 Threshold oltae - Consider an NMOS: as the ate voltae is increased, the surface under the ate is depleted. If the ate voltae increases ore, free electrons appear under the ate and a conductive channel is fored. (a) An NMOS driven by a ate voltae, (b) foration of depletion reion, (c) onset of inversion, and (d) channel foration As entioned before, in NMOS devices chare carriers in the channel under the ate are electrons. 7

Threshold oltae - Intuitively, the threshold voltae is the ate voltae that forces the interface (surface under the ate) to be copletely depleted of chare (in NMOS the interface is as uch n-type as

18 Threshold oltae - Intuitively, the threshold voltae is the ate voltae that forces the interface (surface under the ate) to be copletely depleted of chare (in NMOS the interface is as uch n-type as the substrate is p-type) Increasin ate voltae above this threshold (denoted by or t ) induces an inversion layer (conductive channel) under the ate. Microelectronic Circuits, 004 Oxford University Press 8

19 Threshold oltae - 3 Analytically: Where: MS F Q C dep ox MS Built - inpotential ate Silicon the difference between the work functions of the polysilico n ate and the silicon substrate F Work Function (electrostatic potential) K T q ln N n sub i Q dep Chare in the depletion reion 4 q si F N sub 9

20 Threshold oltae - 4 In practice, the native threshold value ay not be suited for circuit desin, e.., ay be zero and the device ay be on for any positive ate voltae. Typically threshold voltae is adjusted by ion iplantation into the channel surface (dopin P-type aterial will increase of NMOS devices). When DS is zero, there is no horizontal electric field present in the channel, and therefore no current between the source to the drain. When DS is ore than zero, there is soe horizontal electric field which causes a flow of electrons fro source to drain. 0

The chare density Q d (unit C/) is unifor.

21 Lon Channel Current Equations - The voltae of the surface under the ate, (x), depends on the voltaes of Source and Drain. If DS is zero, D = S =(x). The chare density Q d (unit C/) is unifor. Q d Q L C L C WL ox L Q d WC ox ( ) If DS is not zero, the channel is tapered, and (x) is not constant. The chare density depends on x. Q d ( x) WCox( ( x) )

Current : Lon Channel Current Equations - 3 dq dq dx I Q dt dx dt elocity in ters of (x): velocity E, E d d ( x) velocity ( ) dx Q d in ters of (x): Q L d I D x0 velocity d dt ( x) WCox( ( x) )

22 Current : Lon Channel Current Equations - 3 dq dq dx I Q dt dx dt elocity in ters of (x): velocity E, E d d ( x) velocity ( ) dx Q d in ters of (x): Q L d I D x0 velocity d dt ( x) WCox( ( x) ) Current in ters of (x): I D I D WC dx C n d ( x) [ ( x) ] n dx DS WC 0 ox W L ox [( [ Lon-channel current equation: ox n ( x) ) DS DS Microelectronic Circuits, 004 Oxford University Press ] ] d

23 Lon Channel Current Equations - 4 If DS - we say the device is operatin in triode (or linear) reion. Current in Triode Reion: I D n C ox W L DS DS Terinoloy: W Aspect Ratio L Overdrive oltae Effective oltae eff 3

24 Lon Channel Current Equations - 5 For very sall DS (deep Triode Reion): I D can be approxiated to be a linear function of DS. The device resistance will be independent of DS and will only depend on eff. The device will behave like a variable resistor If DS I R D ON n I C DS D ox n W L : C ox W L DS 4

25 Lon Channel Current Equations - 6 Increasin DS causes the channel to acquire a tapered shape. Eventually, as DS reaches the channel is pinched off at the drain. Increasin DS above has little effect (ideally, no effect) on the channel s shape. Microelectronic Circuits, 004 Oxford University Press When DS is ore than the channel is pinched off, and the horizontal electric field produces a current. 5

26 Lon Channel Current Equations - 7 If DS >, the transistor is in saturation (active) reion, and the channel is pinched off. L' I D x0 I D dx nc WC 0 ox ox W ( L' [ n ) ( x) ] d Let s, for now, assue that L =L. The fact that L is not equal to L is a second-order effect known as channel-lenth odulation. Since I D only depends on, MOS transistors in saturation can be used as current sources. 6

27 Lon Channel Current Equations - 8 Current Equation for NMOS: I D I DS 0 ; if n Cox n Cox n C W L W L ox W L ( ( Cut off ) ) DS DS ; if ; if DS ; if,, DS DS (, DS ) ( Deep Triode) ( Saturation ( Triode) ) 7

28 Lon Channel Current Equations - 9 Current Equation for PMOS: I D I SD 0 ; if SG ( Cut off ) W p Cox SG L W p Cox SG L W p Cox ( SG ) L SD SD ; if ; if SG SG SD ; if,, SG SD SD ( SG, SG SD SG ) ( Deep Triode) ( Saturation ( Triode) ) 8

Reions of Operation - Reions of Operation: Cut-off, triode (linear), and saturation (active or pinch-off) Microelectronic Circuits, 004 Oxford University Press Once the channel is

29 Reions of Operation - Reions of Operation: Cut-off, triode (linear), and saturation (active or pinch-off) Microelectronic Circuits, 004 Oxford University Press Once the channel is pinched off, the current throuh the channel is alost constant. As a result, the I- curves have a very sall slope in the pinch-off (saturation) reion, indicatin the lare channel resistance. 9

30 Reions of Operation - The followin illustrates the transition fro pinch-off to triode reion for NMOS and PMOS devices. For NMOS devices: If D increases ( G Const.), the device will o fro Triode to Pinch-off. If G increases ( D Const.), the device will o fro Pinch-off to Triode. ** In NMOS, as DG increases the device will o fro Triode to Pinch-off. For PMOS devices: If D decreases ( G Const.), the device will o fro Triode to Pinch-off. If G decreases ( D Const.), the device will o fro Pinch-off to Triode. ** In PMOS, as GD increases the device will o fro Pinch-off to Triode. 30

31 NMOS Reions of Operation: Reions of Operation - 3 Microelectronic Circuits, 004 Oxford University Press Relative levels of the terinal voltaes of the enhanceent-type NMOS transistor for different reions of operation. 3

32 PMOS Reions of Operation: Reions of Operation - 4 Microelectronic Circuits, 004 Oxford University Press The relative levels of the terinal voltaes of the enhanceent-type PMOS transistor for different reions of operation. 3

33 Reions of Operation - 5 Exaple: For the followin circuit assue that =0.7. When is the device on? What is the reion of operation if the device is on? Sketch the on-resistance of transistor M as a function of G. 33

34 Transconductance - The drain current of the MOSFET in saturation reion is ideally a function of ate-overdrive voltae (effective voltae). In reality, it is also a function of DS. It akes sense to define a fiure of erit that indicates how well the device converts the voltae to current. Which current are we talkin about? What voltae is in the desiner s control? What is this fiure of erit? I D DS Const. 34

35 Transconductance - Exaple: Plot the transconductance of the followin circuit as a function of DS (assue b is a constant voltae). Transconductance in triode: Transconductance in saturation: n C n n C ox C ox W L W L DS n C ) DS W ( ) ox ox W ( L L DS DS DS Const. Const. Moral: Transconductance drops if the device enters the triode reion. 35

36 Transconductance - 3 Transconductance,, in saturation: W n Cox ( ) n L C ox W L I D I If the aspect ratio is constant: depends linearly on ( - ). Also, depends on square root of I D. D If I D is constant: is inversely proportional to ( - ). Also, depends on square root of the aspect ratio. If the overdrive voltae is constant: depends linearly on I D. Also, depends linearly on the aspect ratio. 36

37 Second-Order Effects (Body Effect) Substrate oltae: So far, we assued that the bulk and source of the transistor are at the sae voltae ( B = S ). If B > s, then the bulk-source PN junction will be forward biased, and the device will not operate properly. If B < s, the bulk-source PN junction will be reverse biased. the depletion reion widens, and Q dep increases. will be increased (Body effect or Backate effect). It can be shown that (what is the unit for?: 0 F SB F where q C si ox N sub 37

38 Body Effect - Exaple: Consider the circuit below (assue the transistor is in the active reion): If body-effect is inored, will be constant, and I will only depend on = in - out. Since I is constant, in - out reains constant. in out C Const. C D Conts. in out In eneral, I depends on - = in - out - (and with body effect is not constant). Since I is constant, in - out - reains constant: in C Const. out in out C As out increases, SB increases, and as a result increases. Therefore, in - out Increases. No Body Effect With Body Effect 38

39 Body Effect - 3 Exaple: For the followin Circuit sketch the drain current of transistor M when X varies fro - to 0. Assue 0 =0.6, =0.4 /, and F =

40 Channel Lenth Modulation - When a transistor is in the saturation reion ( DS > ), the channel is pinched off. L' L W ID ncox ( ) L' L L L L L L L L The drain current is where L' L-L L DS L DS Assuin L we et: L' L The drain current is I C ( ) C D L W W n ox n ox L' As I D actually depends on both and DS, MOS transistors are not ideal current sources (why?). L L DS 40

41 Channel Lenth Modulation - represents the relative variation in effective lenth of the channel for a iven increent in DS. For loner channels is saller, i.e., /L Transconductance: I D DS Const. In Triode: C n ox W L DS In Saturation (inorin channel lenth odulation): C n ox W ( ) n C L In saturation with channel lenth odulation: ox W I L D I D C n ox W W ( ) DS n ox D L L C I The dependence of I D on DS is uch weaker than its dependence on. DS I D 4

42 Exaple: Channel Lenth Modulation - 3 Given all other paraeters constant, plot I D - DS characteristic of an NMOS for L=L and L=L In Triode Reion: W ID n Cox L ID W Therefore : DS L DS DS In Saturation Reion: W ID ncox L So we et : ID W ncox DS L Therefore : ID W W L DS L DS Chanin the lenth of the device fro L to L will flatten the I D - DS curves (slope will be divided by two in triode and by four in saturation). Increasin L will ake a transistor a better current source, while deradin its current capability. Increasin W will iprove the current capability. 4

43 Sub-threshold Conduction If <, the drain current is not zero. The MOS transistors behave siilar to BJTs. In BJT: I C I S e BE T In MOS: I D I 0 e T As shown in the fiure, in MOS transistors, the drain current drops by one decade for approxiately each 80 of drop in. In BJT devices the current drops faster (one decade for approxiately each 60v of drop in ). This current is known as sub-threshold or weak-inversion conduction. 43

44 CMOS Processin Technoloy Top and side views of a typical CMOS process 44

45 CMOS Processin Technoloy Different layers coprisin CMOS transistors 45

46 Photolithoraphy (Lithoraphy) Used to transfer circuit layout inforation to the wafer 46

47 Typical Fabrication Sequence 47

48 Self-Alined Process Why source and drain junctions are fored after the ate oxide and polysilicon layers are deposited? 48

49 Oxide spacers and silicide Back-End Processin 49

50 Back-End Processin Contact and etal layers fabrication 50

51 Back-End Processin Lare contact areas should be avoided to iniize the possibility of spikin 5

52 MOS Layout - It is beneficial to have soe insiht into the layout of the MOS devices. When layin out a desin, there are any iportant paraeters we need to pay attention to such as: drain and source areas, interconnects, and their connections to the silicon throuh contact windows. Desin rules deterine the criteria that a circuit layout ust eet for a iven technoloy. Thins like, iniu lenth of transistors, iniu area of contact windows, 5

53 MOS Layout - Exaple: Fiures below show a circuit with a suested layout. The sae circuit can be laid out in different ways, producin different electrical paraeters (such as different terinal capacitances). 53

54 Device Capacitances - The quadratic odel deterines the DC behavior of a MOS transistor. The capacitances associated with the devices are iportant when studyin the AC behavior of a device. There is a capacitance between any two terinals of a MOS transistor. So there are 6 Capacitances in total. The Capacitance between Drain and Source is neliible (C DS =0). These capacitances will depend on the reion of operation (Bias values). 54

55 Device Capacitances - The followin will be used to calculate the capacitances between terinals:. Oxide Capacitance: C W L C ox,. Depletion Capacitance: 3. Overlap Capacitance: C C 3 C C 4 dep W L C ov C ox W L t ox ox q si N 4 D C ox F sub C frine 4. Junction Capacitance: Sidewall Capacitance: C jsw Botto-plate Capacitance: C j C jun C j0 R B C 5 C 6 C j C jsw 55

56 Device Capacitances - 3 In Cut-off:. C : is equal to the overlap capacitance.. C GD : is equal to the overlap capacitance. 3. C GB : is equal to C ate-channel = C in series with C channel-bulk = C. C C GD C C ov ov C 3 C 4 4. C SB : is equal to the junction capacitance between source and bulk. 5. C DB : is equal to the junction capacitance between source and bulk. C SB C 5 C DB C 6 56

57 Device Capacitances - 4 In Triode: The channel isolates the ate fro the substrate. This eans that if G chanes, the chare of the inversion layer are supplied by the drain and source as lon as DS is close to zero. So, C is divided between ate and drain terinals, and ate and source terinals, and C is divided between bulk and drain terinals, and bulk and source terinals.. C :. C GD : 3. C GB : the channel isolates the ate fro the substrate. 4. C SB : 5. C DB : C C GD C SB C DB C C C ov ov 5 C 6 C C C C C GB 0 57

58 In Saturation: Device Capacitances - 5 The channel isolates the ate fro the substrate. The voltae across the channel varies which can be accounted for by addin two equivalent capacitances to the source. One is between source and ate, and is equal to two thirds of C. The other is between source and bulk, and is equal to two thirds of C.. C :. C GD : 3. C GB : the channel isolates the ate fro the substrate. 4. C SB : 5. C DB : C C ov CGD C ov CSB C 5 C DB C 6 C 3 C 3 C GB 0 58

59 Device Capacitances - 6 In suary: Cut-off Triode Saturation C C ov C C ov Cov C 3 C GD Cov C C ov Cov C GB C SB C C C C C 5 C GB C 0 C C5 0 C 5 C 3 C DB C 6 C C6 C 6 59

60 Iportance of Layout Exaple (Folded Structure): Calculate the ate resistance of the circuits shown below. Folded structure: Decreases the drain capacitance Decreases the ate resistance Keeps the aspect ratio the sae 60

61 Passive Devices Resistors 6

62 Passive Devices Capacitors: 6

63 Passive Devices Capacitors 63

64 Passive Devices Inductors 64

65 Latch-Up Due to parasitic bipolar transistors in a CMOS process 65

66 Sall Sinal Models - Sall sinal odel is an approxiation of the lare-sinal odel around the operation point. In analo circuits ost MOS transistors are biased in saturation reion. In eneral, I D is a function of, DS, and BS. We can use this Taylor series approxiation: Taylor Expansion : I D I D0 I D I D I D DS I DS D I D BS I BS D DS DS I D BS r o DS BS b second order ters BS 66

67 67 Sall Sinal Models - Current in Saturation: Taylor approxiation: Partial Derivatives: DS ox n ox n D L W C L W C I ) ( ' BS BS D DS DS D D D I I I I b SB F SB F DS ox n BS D BS D o D ox n DS D DS ox n D L W C I I r I L W C I L W C I ) ( ) ( ) (

68 Sall-Sinal Model: Sall Sinal Models - 3 i D v v r DS Ters, v and b v BS, can be odeled by dependent sources. These ters have the sae polarity: increasin v G, has the sae effect as increasin v B. The ter, v DS /r o can be odeled usin a resistor as shown below. o b v BS 68

69 Sall Sinal Models - 4 Coplete Sall-Sinal Model with Capacitances: Sall sinal odel includin all the capacitance akes the intuitive (qualitative) analysis of even a few-transistor circuit difficult! Typically, CAD tools are used for accurate circuit analysis For intuitive analysis we try to find a siplest odel that can represent the role of each transistor with reasonable accuracy. 69

70 Circuit Ipedance - It is often useful to deterine the ipedance of a circuit seen fro a specific pair of terinals. The followin is the recipe to do so:. Connect a voltae source, X, to the port.. Suppress all independent sources. 3. Measure or calculate I X. R X I X X 70

71 Exaple: Circuit Ipedance - Find the sall-sinal ipedance of the followin current sources. We draw the sall-sinal odel, which is the sae for both circuits, and connect a voltae source as shown below: i X R v r X X o v i X X r o v v r X o 7

72 7 Circuit Ipedance - 3 Exaple: Find the sall-sinal ipedance of the followin circuits. We draw the sall-sinal odel, which is the sae for both circuits, and connect a voltae source as shown below: b o b o X X X X b X o X BS b o X X r r i v R v v r v v v r v i

73 73 Circuit Ipedance - 4 Exaple: Find the sall-sinal ipedance of the followin circuit. This circuit is known as the diode-connected load, and is used frequently in analo circuits. We draw the sall-sinal odel and connect the voltae source as shown below: o o X X X o X X o X o X X r r i v R r v v r v v r v i If channel lenth odulation is inored (r o = ) we et: o X r R

74 74 Circuit Ipedance - 5 Exaple: Find the sall-sinal ipedance of the followin circuit. This circuit is a diode-connected load with body effect. b o b o b o X X X b o X X b X o X BS b o X X r r r i v R r v v v r v v v r v i If channel lenth odulation is inored (r o = ) we et: b b b b o X r R

75 Equivalent Transconductance - Recall that the transconductance of a transistor was a a fiure of erit that indicates how well the device converts a voltae to current. I D DS Const. It is soeties useful to define the equivalent transconductance of a circuit as follows: I OUT G Const. IN OUT The followin is a sall-sinal block diara of an arbitrary circuit with a Norton equivalent at the output port. We notice that: OUT =Constant so v OUT =0 in the sall sinal odel. G i v OUT IN v OUT 0 75

76 Exaple: Equivalent Transconductance - Find the equivalent transconductance of an NMOS transistor in saturation fro its sall-sinal odel. i OUT G i v OUT IN v v IN 76

77 77 Equivalent Transconductance - 3 Exaple: Find the equivalent transconductance of the followin circuit when the NMOS transistor in saturation. S S b S O O O O S S b S IN OUT IN O S S b S OUT O S OUT S OUT b S OUT IN O S BS b OUT S OUT S IN R R R r r r r R R R v i G v r R R R i r R i R i R i v r v v v i R i v v v v ) (

78 Short-Channel Effects Threshold Reduction Drain-induced barrier lowerin (DIBL) Mobility deradation elocity saturation Hot carrier effects Substrate current Gate current Output ipedance variation 78

Threshold oltae ariation in Short Channel Devices The Threshold of transistors fabricated on the sae chip decreases as the channel lenth decreases.

79 Threshold oltae ariation in Short Channel Devices The Threshold of transistors fabricated on the sae chip decreases as the channel lenth decreases. Intuitively, the extent of depletion reions associated with drain and source in the channel area, reduces the iobile chare that ust be iaed by the chare on the ate. 79

80 Drain-Induced Barrier Lowerin (DIBL) When the channel is short, the drain voltae increases the channel surface potential, lowerin the barrier to flow chare fro source (think of increased electric field) and therefore, decreasin the threshold. 80

81 Effects of elocity Saturation Due to drop in obility at hih electric fields (a) Preature drain current saturation and (b) reduction in 8

82 Hot Carrier Effects Short channel devices ay experience hih lateral drain-source electric field Soe carriers that ake it to drain have hih velocity (called hot carriers) Hot carriers ay hit silicon atos at hih speed and cause ipact ionization The resultin electron and holes are absorbed by the drain and substrate causin extra drain-substrate current Really hot carriers ay be injected into ate oxide and flow out of ate causin ate current! 8

83 Output Ipedance ariation Recall the definition of. 83

84 Output Ipedance ariation in Short-Channel Devices 84

EECE488: Analog CMOS Integrated Circuit Design. Set 2: Background

EECE488: Analog CMOS Integrated Circuit Design. Set 2: Background EECE488: Analo CMOS Interated Circuit esin Set : Backround Shahriar Mirabbasi epartent of Electrical and Coputer Enineerin Uniersity of British Colubia shahriar@ece.ubc.ca Technical contributions of Pedra