Unified Approach to Bulk/SOI/UTB/s-DG MOSFET Compact Modeling

Transcription

1 WCM-MSM2006 Workshop on Compact Modeling 9th International Conference on Modeling and Simulation of Microsystems Boston, Massachusetts, USA Unified Approach to Bulk/SOI/UTB/s-DG MOSFET Compact Modeling Xing Zhou 1, Karthik Chandrasekaran 1, Siau Ben Chiah 2, Wangzuo Shangguan 1, Zhaomin Zhu 1, Guan Huei See 1, Shesh Mani Pandey 2, Guan Hui Lim 1, Subhash Rustagi 3, Michael Cheng 2, Sanford Chu 2, and Liang-Choo Hsia 2 1 Nanyang Technological University 2 Chartered Semiconductor Manufacturing 3 Institute of Microelectronics Singapore (exzhou@ntu.edu.sg) May 9, 2006 X. ZHOU 1

2 Presentation Outline Introductory question: best models and approaches to various MOS structures and operations? Unified view and unification of MOS models Unified regional approach Application and results Strained-Si heterostructure channel Doped symmetric-dg Undoped DG/SOI Latest: Doped asymmetric-dg Summary and conclusions X. ZHOU 2

3 Continuum Transformation: FET to BJT Field effect Potential effect Courtesy: S. M. Sze, High-speed semiconductor devices, Wiley, Similar transformation from classical bulk-mos to non-classical SOI/MG MOSFETs? X. ZHOU 3

4 MOSFET Compact Models: History and Future Poisson + GCA Classical bulk-cmos Sah Pao (input) Voltage Equation Pao Sah (output) Current Equation Non-classical CMOS SOI Q b linearization Charge Sheet Model (Q sc =Q b +Q i ) Partially-Depleted (PD) Bulk Voltage/Current Equations, CSM BSIM V t -based Q i linearization Iterative / explicit extension ~40 yrs Q i -based -based nontrivial PSP Fully-Depleted (FD), Ultra-Thin Body (UTB) Non-Charge-Sheet MG New Voltage/Current Equations Symmetric/Asymmetric Double Gate (s-dg/a-dg) Tri-gate, GAA, Heterostructure (strained-si), X. ZHOU 4

5 Motivation: Unification of MOSFET Models After ~40 years, bulk-mos compact modeling goes back to the original ( ) formulation/solution, mainly because V t approach cannot meet the requirement of current technologies. As bulk-cmos scaling is approaching its limit (<<40yrs?) and non-classical CMOS emerges, do we want to re-start from new formulations due to non-extendable bulk formulation? Or, do we want to build non-classical models in parallel with bulk models? As a device (geometry/layer) dimensions and (physical/electrical) parameters vary, its operations change seamlessly; so should the models describing its characteristics be. Motivation: A unified MOS model with seamless transitions across device types and operations. The best of Einstein s theory is not only a brand new theory, but one that includes old (Newton s) theory as a special case. X. ZHOU 5

6 Unified View of a MOSFET with Two Gates V g V g ε oxf 0 Leff t oxf y ε oxf 0 Leff t oxf ψ x j V s (x 0 ) t Si φ 0 V d V s x 0 φ 0 (φ 0 ' = 0) V d ε oxb x x 0 t oxb ε oxb t Si (φ 0 = 0 = φ 0 ' ) t oxb V b Channel thickness (t Si ) and doping (N ch ) Front/back oxide thickness (t oxf /t oxb ) Front/back gate dielectric constant (ε oxf /ε oxb ) and flat-band (V FBf /V FBb ) Key physical parameters Others: channel length (L eff ), junction depth (x j ), over/under-lap ( L), and doping (N sd ) (x 0 ) x V b (φ 0 ' = 0) Different structures/operation Bulk: =0, φ ' b = 0 PD-SOI: =0, φ ' b 0 FD-SOI: 0, φ ' b 0 a-dg: 0, φ ' b 0 s-dg: φ 0 0, φ ' 0 =0 X. ZHOU 6

7 Seamless Transformation and Unification of MOSFETs (a) V g (b) V g 0 (c) V g φ ' b 0 ε oxf t oxf V s t Si φ 0 V d V s V d V s V d V b ε oxb t oxb t Si t oxb = t oxf a-dg (f) V b PD-SOI V g φ ' b = 0 = 0 t oxb (e) V b FD-UTB/SOI V g φ ' 0 = 0 φ 0 0 (d) V b = V g V g φ ' 0 = 0 = V s V d V s V d V s V d t Si 'Bulk-UTB' half s-dg V g s-dg V b PD-SOI FD-UTB/SOI a-dg s-dg UTB Bulk Bulk X. ZHOU 7

8 Generic Voltage Equations for DG/SOI/Bulk MOSFET Poisson Equation (First integral) Field Equation 2 d ψ 2 dx ρ ( n+ N N ) ( n p N N ) D A = = = + A D εsi εsi εsi qn A G qn A ( ψ 2φF Vc) vth vth ( 2φF Vc ) vth e e ψ + = + 1 e ε Si q p q ε Si ( ψ, V ) c E = E + F s 0 s + φs Fs( φs, φ0, Vc) =± 2 qna ε Si G( ψ, Vc) dψ φ0 Gauss Law (boundary conditions) ε ' oxf Vgf φs s = φs =, ( gf g FBf ) ε t E V V V Si oxf ε V φ E E V V V 1 2 ϕs ϕ0 ( vc 2ϕF ) ϕs ϕ0 { ( s ϕ0 ) ( ϕ 0 ) } ( p ) ( N ) ( n) ( N D ) =± 2qN ε v e e + ϕ + v e e e ϕ A Si th th s ( ) ' oxb bf b 0 = b = φb =+, bf b FBb ε Si toxb = A ' ( 0, y) = ( y), E ( 0, y) = E ( y) = ( y) ψ φ φ s x s s ( ϕ = φ ) ' ( x, y) = ( y), E ( x, y) = E ( y) = ( y) ψ φ φ 0 0 x a-dg s-dg/soi Bulk φs, φ b φ, [ φ ] φs Voltage Equations (second integral not possible for doped channel) s 0 v th 1 2 X. ZHOU 8

9 Essence of the Unified Regional Approach Surface Potential, Circle: N-R Iterative Lines: Unified Regional X adding eff φ acc ub tr 0 a φ ds X X X X X X X X X X X X X X X X X 1.0 X X a = φ acc + ub X X d /dv gb smoothing X X X X X X X X X X X X X X X X X X X X N-R eff (V ds = V bs = 0) dφ' s /dv gb V gb at V gb = V FB is not solved Xsim ("Stitched"): eff = φ acc + φ ds exactly, but two pieces are stitched (rather than glued ) to form a singlepiece (eff Gate Bulk Voltage, V gb ) seamlessly { } φcc = Vgb VFB + 2vthL w Vgb < VFB 2 2 γ γ φs φdd = + + Vgb VFB VFB < Vgb < Vt 2 4 φss = φs0 + Vcb + Vgb > V t φ { } φacc = Vgbr + 2vthL w Vgb < VFB 2 2 γ γ = φ = + + V V < V < V 2 4 φstr = φs0 + Vcb + eff Vgb > V t s, eff sub gbf FB gb t Pulled to zero no effect outside the region Glued /iterative solution requires to maintain all the terms in the equation X. ZHOU 9

10 Unified Regional Bulk-Charge Model Bulk Gate Capacitance, C bg (µf/cm 2 ) Other CSM: Right-hand side valid for V gb V FB Symbol: Medici bsub, bsub, bsub, 1 Lines: Model (Xsim) Max. Rel. Error < % Difference between C bg C bg,sa C bg,acc C bg,sub Q b,sub (C/cm 2 ) (V ds = 5 V, V bs = 0) V gs Gate Source Voltage, V gs Extending to strained-si/soi/dg Q Q = Q Q the left-hand and right-hand side of the voltage equation Vgb VFB V g b r + Vgba a = φ acc + φ u ( φ ) Q = C V V sc ox gb FB sa = C ox ( Vgbr φacc ) + ( Vgba φ sub ) Qbacc, Qbsu, b1 = Q + Q bac, c bsu, b ac C V ( φ ) b, c ox gbr acc ( ) Q C V V + γ φ s b bsub, ox gba gbf sub X. ZHOU 10

11 Unified Regional Approach Applied to Strained-Si Si 1.0 Lines: Model (Xsim) x = 30% t SiGe = 5 nm 1.0 Surface Interface t SiGe (nm) Potential N (cm 3 ) Potential Lines: Model (Xsim) Surface Interface 1x x x x10 17 x = 30% N = 3x10 15 cm Gate Bulk Voltage, V gb 0.12 Gate Bulk Voltage, V gb Gate Capacitance, C gg (pf/µm) N (cm 3 ) 4 1x x10 16 Lines: Model (Xsim) 2 1x10 17 x = 30% 5x10 17 t SiGe = 5 nm Gate Capacitance, C gg (pf/µm) t SiGe = 4 nm Lines: Model (Xsim) 2 t SiGe = 8 nm x = 30% t SiGe = 12 nm N = 1x10 15 cm Gate Bulk Voltage, V gb Gate Bulk Voltage, V gb X. ZHOU 11

12 Doped s-dg: s Explicit Unified Regional Solutions Surface/Mid-gap Potential, /φ Lines: Model (Xsim),acc,sub,vi,str,ds,acc +,ds φ 0,vi φ 0,ds PD FD N A = cm 3 t ox = 3 nm t Si = 20 nm accumulation depletion volume inv. strong inversion φ 0 Strong-inversion regional solution assuming channel full depletion Inaccuracy in mid-gap potential has minimum effect on V -2-1 FB V FD V 0 t 1 2 (See: WCM2006 poster by Karthik) Front/Back-Gate Voltage, V g /V b Modeled physically Unified regional solutions from depletion to volume inversion X. ZHOU 12

13 Doped s-dg: s Doping Scaling Doped to Undoped Surface/Mid-gap Potential, /φ Lines: Model (Xsim) t ox = 3 nm t Si = 50 nm Increasing doping φ 0 Doped s-dg Front/Back-Gate Voltage, V g = V b N A (cm 3 ) Undoped 1e13 1e14 1e15 1e16 Continuous and seamless scaling with channel doping Essential for accurate modeling for undoped channel with low unintentional doping which, if not modeled, will lead to mv error in X. ZHOU 13

14 Doped s-dg: s Channel Thickness Scaling UTB to Bulk Surface Potential, Lines: Model (Xsim) t Si = 10 nm t Si = 20 nm t Si = 30 nm Bulk Doped s-dg t ox = 3 nm N A = cm Gate Charge, Q g (µc/cm 2 ) Continuous scaling with channel thickness Unified model with seamless transition from UTB/DG to bulk MOSFETs Front/Back-Gate Voltage, V g = V b X. ZHOU 14

15 Doped s-dg: s Doping & Channel Thickness Variations Comparison for t Si (circle/triangle) and N A (triangle/square) variations Surface/Mid-gap Potential, /φ Lines: Model (Xsim) Solid Symbol/Solid Lines: Open Symbol/Dashed Lines: φ 0 t Si N A (cm 3 ) 50 nm, 5x nm, 5x nm, 1x10 18 Doped s-dg t ox = 3 nm Front/Back-Gate Voltage, V g = V b X. ZHOU 15

16 Undoped DG: Explicit Unified Regional Solutions Front/Back-Gate Surface Potential, / tr tr ub ub Error in (mv) t Si = 30 nm, t oxf = t oxb = 3 nm (V bf = 0) V gf Symbols: Implicit Lines: Explicit Front-Gate Voltage, V gf (explicit) (implicit) (explicit) (implicit) Explicit regional solutions scalable with layer/bias Implicit generic DG solutions are available Our Newton Raphson solutions need 2~6 iterations to reach femto-v accuracy Explicit regional solutions are derived with mv accuracy X. ZHOU 16

17 Undoped s-dg: Explicit Implicit Numerical Comparison of explicit solution with iterative and numerical solutions Surface Potential, = Symbols: Implicit (N R) Lines: Explicit (Xsim) Cross: Medici Undoped s-dg t ox = 3 nm Front/Back-Gate Voltage, V gf = V bf t Si = 30 nm t ox = 1 nm X. ZHOU 17

18 Undoped s-dg: Back Oxide Scaling s-dg to a-dga Front/Back-Gate Surface Potential, / Lines: Explicit (Xsim) Undoped s-dg/a-dg 10 (a-dg) Front/Back-Gate Voltage, V gf = V bf t oxf = 2 nm t oxb (nm) 2 (s-dg) 5 (a-dg) Continuous scaling and transition from symmetric to asymmetric DG Asymmetry due to back-gate oxide thickness (t oxb ) variation (V g = V b ) Comparison with numerical (Medici) solutions X. ZHOU 18

19 Undoped a-dg: Channel Thickness Scaling Front/Back-Gate Surface Potential, / Symbols: Implicit (N R) Lines: Explicit (Xsim) Cross: Medici t oxf = t oxb = 2 nm Undoped a-dg Front-Gate Voltage, V gf (V bf = 0) t Si = 40 nm t Si = 20 nm t Si = 5 nm Continuous channel thickness scaling Asymmetry due to single-gate bias (V g ) sweeping (V bf = 0) Explicit solution compared with implicit and numerical solutions X. ZHOU 19

20 Undoped a-dg: Back Oxide Thickness Scaling Front/Back-Gate Surface Potential, / Symbols: Implicit (N R) Lines: Explicit (Xsim) Cross: Medici Undoped a-dg φ t oxf = 2 nm, t Si = 20 nm b Front-Gate Voltage, V gf (V bf = 0) t oxb = 2 nm t oxb = 10 nm Continuous backgate oxide thickness scaling Asymmetry due to single-gate bias (V g ) sweeping (V bf = 0) Explicit solution compared with implicit and numerical solutions X. ZHOU 20

21 Undoped s-dg: Channel Thickness Scaling s-dg to SOI Surface/Mid-gap Potential, /φ Model (Xsim): Implicit (N R) Undoped s-dg/(soi) (SOI) t oxf = 2 nm t oxb = 200 nm t oxf = t oxb = 2 nm (s-dg) t Si = 5 nm Front/Back-Gate Voltage, V gf = V bf φ 0 t Si = 40 nm t Si = 20 nm Continuous channel thickness scaling Comparison between s-dg and SOI Implicit N R solution (difficult to converge as t oxb approaches t oxf ) X. ZHOU 21

22 Undoped a-dg: Channel Voltage Variation for MOSFETs Front/Back-Gate Surface Potential, / Lines: Explicit (Xsim) V c = 0 V c = 0.1 V Error in φ (mv) t oxf = t oxb = 2 nm, t Si = 20 nm V gf Undoped a-dg (V bf = 0) Front-Gate Voltage, V gf Undoped a-dg with non-zero channel voltage (V c 0) Accurate and solutions needed for MOSFET terminal current evaluated at the source φ(v s ) and drain φ(v d ) ends Explicit solution compared with numerical solution, showing ~mv error for application to MOSFETs X. ZHOU 22

23 Doped a-dg/utba DG/UTB-SOI: Regional Solutions Front/Back-Gate Surface Potential, / 1.0 Seamless transition from a-dg to SOI Lines: Model (Xsim) N A = 1x10 18 cm 3 t Si = 20 nm t oxf = 3 nm (V bf = 0) Doped SOI/a-DG Front-Gate Voltage, V g t oxb = 200 nm (SOI) t oxb = 3 nm (a-dg) The most challenging case: doped a-dg & UTB/SOI (known to be non-integrable!) Demonstrated physical/ regional solutions in depletion and volume inversion regions, with seamless transitions in t oxb, t Si, N A, V b variations, validated by Medici Final challenge: accurate solution in strong inversion! X. ZHOU 23

24 Seamless Transitions: Doping, Thickness, Bias Scaling DG: FD to PD Doped to undoped Front/Back-Gate Surface Potential, / Front/Back-Gate Surface Potential, / Lines: Model (Xsim) 1.0 toxf = t oxb = 3 nm t Si = 20 nm (V bf = 0) 1.0 Doped a-dg N A = 1x10 18 cm 3 N A = 1x10 17 cm 3 Undoped Front-Gate Voltage, V g Lines: Model (Xsim) (V bf = 0) Doped a-dg N A = 1x10 18 cm 3, t oxf = t oxb = 3 nm t Si = 20 nm t Si = 10 nm Front-Gate Voltage, V g Back-bias scaling Front/Back-Gate Surface Potential, / Lines: Model (Xsim) 1.0 NA = cm 3 t oxf = t oxb = 3 nm t Si = 20 nm Solid Symbol/Line: Open Symblol/Dashed Line: Doped a-dg V b = 0.15 V V b = 0 V b = 0.4 V V b = 0.85 V (V FBb ) Front-Gate Voltage, V g Latest results conclusion / vision Unified regional solution: the only solution to future generation nonclassical MOSFETs? Close to the final ultimate solution: Unification of MOS models X. ZHOU 24

25 Summary and Conclusions What is the best modeling approach? from historical bulk-mos development to future generation non-classical MOS structures/operations Classical bulk -based formulation non-extendable to DG/non-CSM Unified regional solutions feasible for constructing complete solutions for non-classical MOS with structural/operational variations and seamless transitions, which also includes bulk-mos (and converges to the simplest V t -based formulations) Model development to tackle the future problem, now; rather than restarting or getting around or doubling the efforts. Key: the approach Goals and Vision Unification of MOS models with the unified regional approach within one model infrastructure and seamless transitions across device types and operations X. ZHOU 25

26 Acknowledgment and References This work was supported in part by Semiconductor Research Corporation: Contract No VJ-1166 Nanyang Technological University: Grant RGM30/03 Institute of Microelectronics/A*STAR: ARC HN/OCL/103/0105/IME Related publications Surface-potential Solution for Generic Undoped MOSFETs with Two Gates, submitted for publication. Explicit Unified Regional Surface Potential for Asymmetric Undoped Double-Gate MOSFETs, submitted for publication. Compact Modeling of Doped Symmetric DG MOSFETs with Regional Approach, Proc. WCM-Nanotech 2006, Boston, May Effect of Substrate Doping on the Capacitance Voltage Characteristics of Strained-silicon pmosfets, IEEE Electron Device Lett., Vol. 27, No. 1, pp , Jan Extraction of physical parameters of strained-silicon MOSFETs from C V measurement, Proc. ESSDERC 2005, Grenoble, Sept. 2005, pp Physics-based single-piece charge model for strained-si MOSFETs, IEEE Trans. Electron Devices, Vol. 52, No. 7, pp , July A Compact Model for Future Generation Predictive Technology Modeling and Circuit Simulation, (Invited Paper), Proc. MIXDES 2005, Kraków, June 2005, pp Unified Regional Charge-based Versus Surface-potential-based Compact Modeling Approaches, (Invited Paper), Proc. WCM-Nanotech 2005, Anaheim, May 2005, pp Single-piece polycrystalline silicon accumulation/depletion/inversion model with implicit/explicit surface-potential solutions, Appl. Phys. Lett., Vol. 86, No. 20, , May X. ZHOU 26