Zuhui Chen, Xing Zhou, Guan Huei See, Zhaomin Zhu, and Guojun Zhu

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1 Zuhui Chen, Xing Zhou, Guan Huei See, Zhaomin Zhu, and Guojun Zhu School of EEE, Nanyang Technological University, Singapore Slide No.1/18

2 Outline Motivations. Theory of interface traps. Theory of unified regional surface potential. Theory of unified regional drain current. Effects of interface-trap density on surface potential. Effects of interface-trap density on drain current. Summary Slide No.2/18

3 Motivation Reasons for investigating interface traps The density and spatial distribution of interface traps at the SiO 2 /Si interface increasingly impacts the performance and endurance of metal-oxide-silicon capacitors and transistors in integrated circuits. Interface traps are generated in MOS transistors during program-erase cycles, which are the main mechanism that limits the endurance of non-volatile MOS memory transistors such as the floating gate and recent SONOS. Slide No.3/18

4 Interface traps in MOSFETs silicide SiO 2 Slide No.4/18

5 Theory of interface traps (1) Q (2) Q ETi HTi C (1) Q = ( Q + Q ) de cnsns + eps = qneti c n + e + c p + e (3) n = n exp[( φ φ ) / v ] s i s Fn th (4) p = n exp[( φ φ ) / v ] s i Fp s th (5) e = c n exp( + E / kt) ns ns i TI (6) e = c n exp( E / kt) ps ps i TI E IT E ETi HTi V ns s ns ps s ps cps ps + ens = qnhti c n + e + c p + e ns s ns ps s ps DET (7) R = = = DHT E ET D ET 2 (8) N ET = ( D ) ( ) ET E de = EET 2 1 D HT (9) N HT = D HT (1 E HT ) de = (1 E HT ) E HT 2 2 Slide No.5/18

6 Theory of unified regional surface potential Q IT (1) V gb = φ s + Φ M S + s g n ( φ s ) ϒ C ( ) (2 a) V = φ + Φ + v ϒ exp( φ / v ), V << Φ gb s MS th s th gb MS ( V ) (2b) V = φ + Φ + ϒ φ, < Φ gb s MS s gb MS ( ) (3 c) V = φ + Φ + ϒ φ, Φ < V < V gb s MS s MS gb t ( ) (2 d) V = φ + Φ + v ϒ exp[( φ 2 φ V ) / v ], V >> V ox φ s φ s φ s φ s (1 a) fφ = v th e e 1 e v th v th v v v th th th gb s MS th s Fp cb th gb t f φ ( 2 φ Fp V cb ) + Slide No.6/18

7 Theory of unified regional drain current ( ), (1) Ids = β qi + vth Ab Vds eff (7) V db, sat Vgt, d Leff Esat, d = V + 4A v + A L E gt, d bd, th bd, eff satd, (2) qi = Vgb Vfb φs γ φs (3) A = 1 + b 2 γ φ s (8) (9) V sb, sat Vgt, sleff Esat, s = V + 4A v + A L E gt, s bs, th bs, eff sats, sd, 2 F Vdb vth gt, d = γ φsd, + th γ φsd, V v e φ φ (4) φ s = φ ( V ) + φ ( V ) s s, eff s d, eff 2 (1) ss, 2 F Vsb vth gt, s = γ φss, + th γ φss, V v e φ φ (5) β = WuC / L ox eff (11) Vds, eff = Vdb, eff Vsb, eff (6) V =Φ Q / C fb MS I Slide No.7/18

8 Effect of interface-trap density on surface potential (1) φ s ( V) nmosfet V DS =mv =1x1 17 cm -3 =~5x1 12 cm -2 Increasing Symbol: Xsim Line: Numerical Paired-linear traps V GB (a) C gg /C OX 1..8 =.6 5x1 12 3x Symbol: Xsim 1x Line: Numerical 5x1 11 Paired-linear traps V GB (b) (a) Effect of interface-trap density on surface-potential lineshape, (b) effect of interface-trap density on normalized C-V curves. =, , , , , , and cm -2. Slide No.8/18

9 Effect of interface-trap density on surface potential (2) φ s ( V) 1..8 nmosfet V DS =mv E TI =.5eV (a).6 =5x1 17 cm -3 =1x1 12 cm -2.4 ev.2 Symbol: Xsim. Line: Numerical -.5eV V GB φ s ( V) nmosfet E 1. TI =.5eV.8 V DS =mv (b) N.6 A =5x1 17 cm -3 =1x1 12 cm -2.4 ev.2 Q IT = Q IT =. Symbol: Xsim -.5eV V GB Effect of discrete energy-level position of interface traps on the surface-potential lineshape with E TI = -.5 to +.5 ev in.1-ev steps: (a) comparison between the URSP approach and the exact iterative solution, and (b) comparison between devices with and without interface traps. Slide No.9/18

10 Effect of interface-trap density on drain current (1) I ds (A) nmost V DS =.3V =1x1 17 cm -3 (a) Increasing =~5x1 12 cm I ds (ua) G m (S) Increasing Line: Medici Symbol: Xsim (b) G m (us) V gb V gb Interface-trap effect on drain-source current curves and transverse conductance Gm as a function of neutral electron interface-trap density =, , , , , and cm -2. Slide No.1 1/18

11 Effect of interface-trap density on drain current (2) I ds (A) (a) nmost =1x1 17 cm -3 =1x1 12 cm -2 Decreasing V DS V DS =.3~1.2V V gb I ds (ua) G m (S) (b) Line: Medici Symbol: Xsim Decreasing V DS V gb G m (us) Interface-trap effect on drain-source current curves and transverse conductance Gm as a function of drain-source voltage V ds =.3,.6,.9 and 1.2V. Slide No.11 11/18

12 Effect of interface-trap density on drain current (3) I ds (A) (a) nmost =1x1 17 cm -3 =1x1 12 cm -2 Decreasing V DS V DS =.3~1.2V V gb I ds (ua) G m (S) (b) Decreasing V DS Symbol: traps Line: without traps V gb G m (us) Interface-trap effect on drain-source current curves and transverse conductance G m as a function of drain-source voltage V ds =.3,.6,.9 and 1.2V (comparisons between devices with and without interface traps, the curves are generated using Xsim.). Slide No.12 12/18

13 Effect of interface-trap density on drain current (4) I ds (ua) (a) G ds (us) Decreasing nmost V GB =1.V =1x1 17 cm -3 Line: Medici (b) Symbol: Xsim =~5x1 12 cm -2 Increasing V ds V ds Interface-trap effect on drain-source current curves and output conductance G ds as a function of neutral electron interface-trap density =, , , , , and cm -2. Slide No.13 13/18

14 Effect of interface-trap density on drain current (5) I ds (ua) nmost =1x1 17 cm -3 =1x1 12 cm -2 V GB = 1.2V.9V.6V.3V Line: Medici Symbol: Xsim (a) G ds (us) Increasing V DS nmost =1x1 17 cm -3 (b) =1x1 12 cm -2 V GB =.3~1.2V V ds V ds Interface-trap effect on drain-source current curves and output conductance G ds as a function of gate voltage V gb =.3,.6,.9 and 1.2V. Slide No.14 14/18

15 Effect of interface-trap density on drain current (6) I ds (ua) nmost =1x1 17 cm -3 =1x1 12 cm -2 V GB = 1.2V.9V (a) G ds (us) Increasing V DS nmost =1x1 17 cm -3 (b) =1x1 12 cm -2 V GB =.3~1.2V 1 5.6V.3V 2 1 Symbol: traps Line: without traps V ds V ds Interface-trap effect on drain-source current curves and output conductance G ds as a function of gate voltage V gb =.3,.6,.9 and 1.2V (comparisons between devices with and without interface traps, the curves are generated using Xsim). Slide No.15 15/18

16 Summary The device performance is significantly impacted by the presence of interface-trap charges. Drain-current characteristics are closer to the linear energy distribution of neutral electron interface traps in silicon energy gap. Extraction of device parameters from experimental measurements should consider interface-trap effect, especially for midlife transistors with high interface-trap concentration. The explicit analytic unified regional approach offers a simple way with computational efficiency and device physics to track the generation of interface traps and their properties along the surface channel region. Slide No.16 16/18

17 (1) X. Zhou, S. B. Chiah, K. Chandrasekaran, G. H. See, W. Z. Shangguan, S. M. Pandey, M. Cheng, S. Chu, and L.-C. Hsia, Comparison of unified regional charge-based versus surface-potential-based compact modeling approaches, in Proc. NSTI Nanotech, Anaheim, May 25, pp (2) X. Zhou, S. B. Chiah, K. Chandrasekaran, G. H. See, W. Z. Shangguan, C. H. Ang, M. Cheng, S. Chu, and L.-C. Hsia, Xsim: Unified regional approach to compact modeling for next generation CMOS, in Proc. ICSICT, Beijing, Oct. 24, pp (3) Chih-Tang Sah, Origin of Interface States and Oxide Charges Generated by Ionizing Radiation, Plenary IEEE Nuclear and Space Radiation Conference, San Diego, 1976; Tran. Nuclear Sciences NS23(6), , December (4) Chih-Tang Sah, Equivalent Circuit Models in Semiconductor Transport for Thermal, Optical, Auger-Impact, and Tunneling Recombination-Generation Trapping Processes, Phys. Stat. Sol. (a) 7, (1971). (5) Z. Chen, B. B. Jie, and C.-T. Sah, High concentration effects of neutral-potential-well interface traps on recombination DC current-voltage lineshape in metal-oxide-silicon transistors, J. Appl. Phys. vol. 14, 94512(28). (6) Z. Chen, B. B. Jie, and C.-T. Sah, Effects of Energy Distribution of Interface Traps on Recombination DC Current-Voltage Lineshape, J. Appl. Phys. vol.1, (26). Plus many references cited in these articles Slide No.17 17/18

18 Acknowledgments Lee Kuan Yew Postdoctoral Fellowship from Nanyang Technological University CTSAH Associates (Founded by the late Linda Su-nan Chang Sah) Slide No.18 18/18

High Concentration of Interface Traps in. Zuhui Chen Sah Pen-Tung Center, Xiamen University, China

High Concentration of Interface Tra in MO Traistor Modeling Zuhui Chen ah Pen-Tung Center, Xiamen University, China Bin B. Jie Ititute of Microelectronics, Peking Univeristy, China Chih-Tang ah University