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1 Copyright 2008 Year IEEE. Reprinted from IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 2, FEBRUARY Such permission of the IEEE does not in any way imply IEEE endorsement of any of Institute of Microelectronics products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to

2 616 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 2, FEBRUARY 2008 Rigorous Surface-Potential Solution for Undoped Symmetric Double-Gate MOSFETs Considering Both Electrons and Holes at Quasi Nonequilibrium Xing Zhou, Senior Member, IEEE, Zhaomin Zhu, Subhash C. Rustagi, Senior Member, IEEE, Guan Huei See, Student Member, IEEE, Guojun Zhu, Shihuan Lin, Chengqing Wei, and Guan Hui Lim, Student Member, IEEE Abstract This paper presents a rigorously-derived analytical solution of the Poisson equation with both electrons and holes in pure silicon, which is applied to the analysis of undoped symmetric double-gate transistors. An implicit surface-potential equation is obtained that can be solved by a second-order Newton Raphson technique along with an appropriate initial guess. Within the assumption of holes at equilibrium that is being used in the existing literature, the new results, when compared with the models based on one carrier, reveal that missing the other carrier in the formulation results in a singularity in the gate capacitance exactly at flatband, which may give trouble for high-frequency analysis, although the errors in surface potentials are below the nano-volt range for all gate voltages. However, the solution without assuming constant hole imref, as presented in this paper for the first time, further pinpoints the inadequacy in existing theories of surfacepotential solutions in double-gate MOSFETs with undoped thin bodies, although its application to transport solutions of terminal current/charge models depends highly on the type of source/drain structures and contacts. Index Terms Imref, MOSFET, nonequilibrium, Poisson solution, surface potential, symmetric double gate. I. INTRODUCTION DOUBLE-GATE DG MOSFETs have evoked huge interest due to their inherent strong immunity to shortchannel effects as the bulk-mos technology approaches the end of the road map. Analysis of DG MOSFETs dates back to 1967 [1], about the same time as bulk-mos models [2], [3]. There has been huge research interest in DG and silicon-oninsulator SOI MOS compact modeling [4] [15] in which Manuscript received May 22, 2007; revised October 15, This work was supported in part by the Institute of Microelectronics under Agreement for Research Collaboration HN/OCL/103/0105/IME through the A STAR SERC Grant , in part by Nanyang Technological University under Grant RGM30/03, and in part by Semiconductor Research Corporation under Grant 2004-VJ-1166G. The review of this paper was arranged by Editor C. McAndrew. X. Zhou, G. H. See, S. H. Lin, C. Q. Wei, G. J. Zhu, and G. H. Lim are with the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore , Singapore exzhou@ntu. edu.sg; seeg0001@ntu.edu.sg; lins0026@ntu.edu.sg; weic0002@ntu.edu.sg; zhug0002@ntu.edu.sg; limg0013@ntu.edu.sg. Z. M. Zhu was with the Institute of Microelectronics, Singapore , Singapore. He is also with the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore , Singapore ZMZhu@ntu.edu.sg. S. C. Rustagi is with the Institute of Microelectronics, Singapore , Singapore subhash@ime.a-star.edu.sg. Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TED charge- orpotential-based approaches have been followed. For transistors with undoped pure silicon body, there is no depletion region, and only diffusion-dominant volume-inversion and drift-dominant strong-inversion regions need to be analyzed. Ortiz-Conde et al. [4], [5] formulated voltage equations for generic SOI MOSFETs with two gates and doped bodies, and reported approximate [4] or iterative [5] surface-potential solutions. Their later work [6] on analytic surface-potential solutions in symmetric-dg s-dg MOSFETs with undoped bodies started off with both the electron and hole terms in the Poisson equation, but dropped the holes in the formulations. Francis et al. [7] considered only electrons in doped DG/SOI MOSFETs in his regional solutions. Sleight and Rios [8] studied partially/full-depleted SOI devices considering both carriers and channel doping but assumed depletion approximation in the solutions. Taur [9], [10] analyzed symmetric- and asymmetric-dg MOSFETs considering only the electrons in the undoped body. Ortiz-Conde et al. [11] presented a review paper on various potential/charge-based undoped DG models, all based on the one-carrier solution. Zhu et al. [12] obtained explicit surface-potential expressions and compared with iterative solutions, considering only the electrons. They also obtained analytical expressions of the drain current for undoped symmetricand asymmetric-dg MOSFETs. Shi and Wong [13] formulated generic oxide silicon oxide solutions in various regions considering both electrons and holes, but applicable only to MOS capacitors. Their later work [14] on nonequilibrium MOSFET surface-potential solutions included both carriers with the assumption of holes at equilibrium, and they obtained approximate solutions based on [15]. Although it appears to be common sense that ignoring holes in the Poisson solution for undoped DG MOSFETs can be justified for gate voltages well above flatband, as have been done in most recent literature [6], [9] [12], its inaccuracy and validity will not be known unless an exact solution with both types of carriers is obtained for comparison. The purpose of this paper is to present such a rigorously derived surface-potential solution for benchmarking as well as revealing the limitations of the models considering only one type of carriers. The surfacepotential equation for the undoped s-dg MOSFETs, resulting from the first integral of the Poisson equation together with the Gauss law applied at the gate, is solved with the second-order Newton Raphson NR method, with an initial guess that proves to be quite close to the true solution and makes the NR algorithm /$ IEEE

3 ZHOU et al.: RIGOROUS SURFACE-POTENTIAL SOLUTION FOR UNDOPED SYMMETRIC DG MOSFETS 617 computationally efficient. In addition, the new solution without assuming hole imref to be a constant is also obtained, which pinpoints the missing effects in existing literature on undoped DG voltage-equation solutions of the surface potential. II. MODEL FORMULATION AND SOLUTIONS A. Holes at Equilibrium Hole Imref =0 Under Boltzmann statistics, the electron and hole concentrations in undoped MOSFETs are given by n = n i e φ φ Fn/ = n i e φ V / 1a p = n i e φ φ Fp/ = n i e φ/ 1b respectively, in which V φ Fn φ Fp is the imref split or channel voltage that takes the value of zero at the source end and V ds at the drain end; and in the second term on the right hand side, the hole imref φ Fp is assumed to be the bulk Fermi potential zero in pure silicon, as was also done in [14]. It is worth mentioning that for studying the voltage-equation solution in a pure-body MOSFET, two types of carriers actually coexist, but the sign convention used in this section still follows the n-channel MOS convention. The assumption of holes at equilibrium has been used in all literature on undoped DG as well as bulk-mos theory. In a practical nmosfet with highly doped n + source/drain extensions to the ohmic contacts, this assumption is still correct since there are near-infinite source and sink for electrons to drift/diffuse through the channel while holes will remain at quasi-equilibrium since there are no source and sink for holes at the two contacts. We will first use this assumption in this section to formulate our rigorous surface-potential solutions also for the purpose of comparison with the one-carrier model, and later, in Section II-B, this assumption will be relaxed for the generic solution in pure-body s-dg MOSFETs. The electrostatic potential φ in the undoped silicon body obeys the Poisson equation, with ρ = qp n andφ Fp =0 d 2 φ dx 2 = qn i e φ V / e φ/ = 2qn i e V /2 sinh φ 0.5V 1c where n i is the intrinsic carrier concentration, is the permittivity of silicon, and = k B T/q is the thermal voltage. Other symbols have their usual meanings. Multiplying both sides of 1c by dφ and integrating once, we obtain 2 dφ = 4qn i e V /2 φ 0.5V cosh + C 1 2 dx where C 1 is an integration constant. Taking square root and multiplying by dx on both sides of 2, we obtain ± 4qn i dφ = dx. 3 e V /2 cosh φ 0.5V + C 1 This differential equation can be solved analytically, and the general Poisson solution is given by { } 2a φ 0.5V a C1 bf elliptic cosh, =x+c 2, a C 1 2 2a 4 where a =4qn i / e V/2,b =[ /2qn i e V/2 ] 1/2, and C 2 is an integration constant. F elliptic {z,k} is the Legendre s incomplete elliptic integral of the first kind, defined as z 1 F elliptic {z,k} = dx. 5 1 x 2 1 k 2 x2 0 The general boundary conditions for s-dg MOSFETs are φ s dφ dx = ε ox V gf φ s, φ o dφ x=0 T ox dx x=xo =T Si /2=0 6 where φ s = φ0, y is the surface potential, ε ox and T ox are the permittivity and thickness of the gate oxide, respectively, T Si is the silicon body thickness, V gf V gs V FB is the flatbandshifted gate voltage with V FB being the flatband voltage, and X o = T Si /2 is the body mid-point for s-dg. Using the aforementioned two boundary conditions for determining the two integration constants, we arrive at a single implicit equation for φ s [ { } 2a φs 0.5V a C1 b F elliptic cosh, a C 1 2 2a { }] 2a φo φ s 0.5V a C1 F elliptic cosh, a C 1 2a C 1 = εox V gf φ s T ox φs 0.5V cosh and φ o φ s is expressed as 2 T Si 2 2 4qn i φ o =0.5V + arc cosh θ, φs 0.5V θ =cosh ev /2 4qn i =0 7 e V /2, 7a ε ox V gf φ s T ox 8a 2. 8b Equation 7 is a multiroot implicit equation fφ s =0in the unknown φ s, which requires iterative solutions similar to the surface-potential solution [12] with only the electron term in 1c. We use the second-order NR algorithm [16] x i+1 =x i fx i f x i fx i f x i /2f x i=0, 1, 2,... 9

4 618 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 2, FEBRUARY 2008 to solve 7 for the surface potential φ s, by iterating 9 until fφ i+1 s ε, where ε is the error tolerance equation residue. fφ s represents the left-hand side of 7, which should vanish for an exact solution. For the NR method to work properly on the multiroot function 7, a good initial guess is very important. A helpful way to select a range of values for a physically valid solution from a multiroot function is to plot the function values against the solution variable. Observing 7, it is quite difficult to scan the function values to yield an approximate range of the solution variable. However, some constraints are helpful. The argument of the arccosh function in 8a should always be larger than zero for real solutions, i.e., θ>0. The inequality φs 0.5V cosh ev /2 ε ox V gf φ s T ox 2 > 0 4qn i 10 is solved as an equation under the condition φ s 0.5 V. Using the approximation coshz e z /2 when z 1, thesolution to 10 is obtained as an initial guess, which is given by φ 0 s = V gf 2 L + { Tox ε ox qni 2 e V gf V / 2 }, 11 where L + {w} is the Lambert W function principal branch. B. Holes at Nonequilibrium Hole Imref = V/2 However, the assumption of holes always being at equilibrium is only strictly valid for MOS capacitors or V = 0 [17], not for MOSFETs with nonzero V ds [2], [3], as recently recognized by Sah [18] for the remote deep in the bulk minority carriers near the flatband condition. As a matter of fact, in an undoped silicon especially thin body, there is no depletion i.e., large Debye screening length and the voltage-equation solution is similar to solving the Poisson equation with high-level injection [19], in which both electron and hole imrefs should depend on the applied bias V ds. Electron and hole imrefs without the hole-equilibrium assumption have been derived [18], [20] in the general case with doping, as shown in the Appendix, and they are given for undoped pure silicon with nonzero V ds by φ Fp = V/2 and φ Fn = V/2. This would be the basis for the exact surface-potential solution of the voltage equation, and it can be interpreted for an ideal paper model of the body or base region in which the contacts to the two ends of the silicon body are assumed to have infinite recombination/generation or reflecting boundaries for infinite sources/sinks of both carriers. It is shown that with a simple variable transformation, the solution obtained in Section II-A can be applied to the case without assuming φ Fp = φ F =0. The first equal signs in 1a and 1b should be used in the Poisson Equation 1c, together with φ Fp = V/2 and φ Fn = V/2, which gives d 2 ψ dx 2 = d2 φ dx 2 = qn i e φ 0.5V / e φ+0.5v / = 2qn i e V /2 ψ 0.5V sinh 12 in which a new variable ψ φ + V/2 is defined where V V y is the channel voltage always assumed independent of x. Substituting ψ into the boundary conditions, 6 becomes ψ s dψ dx = ε ox U gf ψ s,ψ o dψ x=0 T ox dx =0 x=xo =T S i /2 13 in which another new variable U gf V gf + V/2 is defined. Since 12 with 13 is exactly the same boundary-value problem as 1c with 6, the φ s V gf solution will be the same as the ψ s U gf solution for any nonzero V. The physical explanation for this variable transformation is simple. When the hole imref is assumed zero equilibrium, the imref split is all apportioned to the electron imref variation, and hence, a surface-potential shift at any nonzero V y due to an applied V ds will only happen for positive gate voltages above the onset of electron drift-dominant region equivalent to strong inversion at 2φ F in doped bulk-nmos. The onset of electron drift-dominant region and φ s will both be shifted exactly by V. However, when holes are not assumed at equilibrium, in pure silicon, hole imref φ Fp = V/2 and electron imref φ Fn = +V/2, as shown in the Appendix. Based on the same reasoning, now at any given Vy, the onset of electron drift-dominant region and φ s will both be shifted by +V/2 for positive V gf. At the same time, the onset of hole drift-dominant region and φ s will both be shifted by V/2 for negative V gf since holes are not at equilibrium. The aforementioned analysis is equivalent to shifting the φ s V gf solution in Section II-A by V/2 downward, and then by V/2 leftward, which is equivalent to plotting the ψ s U gf solution on the φ s V gf plane. The leftshifting by V/2 operation can be interpreted as being due to the V -dependent flatband voltage or work function in silicon when the hole imref is not constant along y, i.e., U gf V gs U FB, in which U FB is defined as U FB = φ MS Q ox /C ox = φ M χ + E g 2q + φ Fp Q ox /C ox. By substituting φ Fp = φ F V 2,wehave U FB = φ M χ + E g /2q + φ F Q ox /C ox V/2 14a = V FB V/2. 14b This interpretation explains the relation U gf V gf + V/2 in which U gf is the flatband-shifted gate voltage with φ Fp = V/2 and V gf V gs V FB is the flatband-shifted gate voltage with φ Fp = φ F =0. In this conceptual one-dimensional model of the silicon body for the x-dependent voltage equation at any y along the channel, there would be, in principle, two channels for both electrons and holes in diffusion-dominant low-voltage and drift-dominant high-voltage regions. III. RESULTS AND DISCUSSION Fig. 1 shows the convergence properties of 7 using the NR algorithm 9 with the proposed initial guess 11. For gate

5 ZHOU et al.: RIGOROUS SURFACE-POTENTIAL SOLUTION FOR UNDOPED SYMMETRIC DG MOSFETS 619 Fig. 1. Equation residue for the NR φ s solutions during the first 10 iterations. voltages near the flatband, it requires eight to ten iterations to reach an equation residue of V, depending on the value of T ox ; while for higher gate voltages, the iteration count could be as few as two. For the subsequent results, the error tolerance is set to V unless otherwise stated, from which φ s can be regarded as an exact solution. Fig. 2 shows the error in φ s values from the one-carrier electron second-order NR solution [12] compared to the twocarrier solution in this paper, as a function of gate voltage for different body and oxide thicknesses. As expected, when the gate voltage is larger than a few thermal voltages, the error of one-carrier φ s solution is less than nanovolt and decreases exponentially, indicating that ignoring holes can be acceptable at these biases. This result validates the assumptions made in those one-carrier models [6], [9] [12]. A finite maximum error of a few nano-volts at V gf =0, depending on the thickness of the silicon body and gate oxides, for the one-carrier φ s solutions is observed, simply due to the violation of charge neutrality when the missing hole concentration becomes comparable to that of the electrons. For a drain-current model, one may still use the one-carrier model due to simpler formulation and negligible error in φ s. However, a singularity in the derivative of φ s with respect to V gs due to missing one carrier exists exactly at V gf =0,asshownin Fig. 3 for the gate capacitance, C gg = d[c ox V gf φ s ]/dv gs, taken from the φ s data at V ds = 0 for both one- and two-carrier models. This singularity can still be skipped in model implementation, giving rise to tens of femto farads per square centimeter absolute error, or 50% maximum error in C gg. However, one can anticipate a discontinuity in C gg derivative at V gf =0, which may be detrimental in high-frequency and distortion analyses. The new result further brings out the importance of our proposed two-carrier solution, which describes continuous C gg and higher-order φ s derivatives. This obvious but important fact has been neglected by most recent literature on undoped DG modeling. To further demonstrate the application of the proposed twocarrier model in surface-potential-based compact modeling, full Fig. 2. Surface-potential difference between the one-carrier and two-carrier models with variations as indicated. a Body-thickness variation. b Oxidethickness variation. V gs step: 5 mv. Fig. 3. Gate capacitance comparison of one-carrier and two-carrier models V gs step: 1 mv. Inset: surface potential comparison V gs step: 10 pv. Equation residue set to V. range of iterative φ s solutions with various channel voltages are plotted in Fig. 4, with the derivatives plotted in the upper inset for showing the smoothness. As expected, when the channel voltage is zero, the surface potential is exactly symmetrical around V gf =0. For the one-carrier φ s model, one may flip the φ s solution at V ds = 0 to the negative V gf range for nmosfets for all nonzero V ds based on the assumption that the accumulated holes would still be at quasi-equilibrium since holes cannot easily move to the n + -type source/drain even when V ds 0, as shown by the circles. Also shown in the lower inset is the error

6 620 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 2, FEBRUARY 2008 Fig. 4. Surface potential versus gate voltage for three channel voltages indicated. Upper inset: derivatives of φ s. Lower inset: absolute error of one-carrier model at V = 0.1 V. Lines: two-carrier model; circles: one-carrier model at V = 0.1 V. V gs step: 50 mv. Hole imref is assumed a constant zero. the actual voltages at the ends of the source and drain under the gradual-channel approximation i.e., excluding the pinchoff or velocity-saturation region should be used that, in turn, would alter the solutions of the x-dependent voltage equation. The specific results for the two-carrier nonequilibrium voltageequation solutions presented here are only strictly applicable to the symmetric-dg with an ideally pure silicon body. It can be inferred that similar effects extend to body net doping below intrinsic carrier concentration, and also in asymmetric-dg devices, although a rigorous solution using A15 would not be trivial. For practical DG/SOI MOSFET modeling, body doping may not be ignored, even with unintentional dopants since pure silicon N A = N D =0 would not practically exist. This imposes further difficulty for experimental verification, or even numerical validation of the revised theory for undoped DG MOSFETs. One way to verify the prediction of the new theory is to exploit below-intrinsic N A N D <n i condition at high temperature. However, the inclusion of the doping term makes the voltage equation nonintegrable. Together with other considerations, such as short-channel and quantum effects as well as non-charge-sheet formulation of the terminal current and charge, exact surface-potential solutions may not be feasible for use in practical compact models. Other approaches, such as unified regional approach [20], have been pursued. Fig. 5. Two-carrier surface potential versus gate voltage for two channel voltages indicated, comparing with and without the assumption of holes being at equilibrium. Dotted line shows shifting the open-triangle solution down, then left by 0.5 V to obtain the solid-triangle solution. of the one-carrier model at V = 0.1 V, showing a maximum error of 1 nvatv gf =0. Based on the formulations in Section II-B, the two-carrier solutions in Fig. 4 with the φ Fp = φ F =0assumption are shifted by V/2 on both x- and y-axis to obtain the corresponding solutions with the φ Fp = V/2 condition, as shown together in Fig. 5. This new result gives the exact surface-potential solution of the input voltage equation independent of the output current-equation solution, and has important implications for the correct theory of undoped thin-body MOSFETs, although it is still not trivial to derive an equation for the drain current considering both carriers at nonequilibrium. It further pinpoints that the transport solutions are highly dependent on the type of source/drain structures and contacts. When such real contacts are considered in the y-dependent current solutions, IV. CONCLUSIONS In conclusion, a generic analytical solution to the Poisson equation including both electrons and holes for undoped symmetric double-gate MOSFETs has been rigorously derived for the first time, and solved by the Newton Raphson method to reach femtovolt equation residue within ten iterations. The new results quantify the errors involved in existing models based on one carrier and pinpoint a potential problem of the singularity in C gg at flatband. The proposed model can be used for accurate evaluation of surface-potential-based symmetric-dg current/charge models, or for benchmarking other surface-potential solutions in undoped s-dg MOSFETs. The rigorous solutions are also extended to devices without assuming holes being at equilibrium, which presents a revised theory different from existing theories for undoped thin-body MOSFETs. It provides the exact benchmark solution for symmetric-dg with pure body and ideal ohmic contacts for both carriers with infinite recombination velocities although, in practice, the real source/drain contact type and its structure have to be considered when current transport is solved. In conventional MOSFETs with n + or p + diffusion source/drain extensions, equilibrium hole or electron assumption in the body would still be applicable in long-channel transport formulations. With other contact configurations that allow bipolar current flow like BJT and body-contacted DG/SOI devices, drift-diffusion currents of both carriers need to be considered in the drain-current formulation. APPENDIX This Appendix outlines the hole imref expression in a generic MOSFET [18], [20], and its implications as well as extension to

7 ZHOU et al.: RIGOROUS SURFACE-POTENTIAL SOLUTION FOR UNDOPED SYMMETRIC DG MOSFETS 621 with the assumption of extremely thick silicon body without loss of generality. Equations A8 and A9 give and n 0 p 0 = n 2 i e φ Fn φ Fp / = n 2 i e V / A10 V = φ Fn φ Fp A11 is defined as the imref split, which is caused by the applied drain source terminal bias. From A8, and expressing p 0 in terms of n 0 using A7, A8, and A11, one obtains φ Fp = ln p 0 = ln n ie V / vth e φ Fp/ vth + N A N D, n i n i A12 which can be re-written as follows: Fig. 6. Hole imref modeled by A15 lines versus net doping concentration for various channel voltages indicated. Circle and triangle by A3 and A4, respectively. undoped bodies. Under equilibrium conditions i.e., no channel voltage applied, like in an MOS capacitor, from Boltzmann statistics and assuming complete ionization of dopant, the electron and hole concentrations in the neutral region are given by n 0 = n i e φ F / p 0 = n i e φ F /. A1 A2 From charge neutrality, n 0 p 0 = N D N A, the bulk Fermi potential can be calculated [17] φ F = sinh 1 NA N D. A3 2n i For N A N D 2n i and N A N D, A3 can be approximated as φ F NA N D ln φ B n i ln NA n i. A4 Obviously, for below-intrinsic body net doping, φ B in A4, as shown by the triangles in Fig. 6, cannot be used. The electron and hole concentrations under nonequilibrium condition are given by n = n i e φ φ Fn/ p = n i e φ φ Fp/ A5 A6 where φ Fn and φ Fp are the electron and hole quasi-fermi potentials imrefs, respectively. The remote charge neutrality [19] demands that n 0 p 0 = N D N A A7 where n 0 and p 0 are the nonequilibrium electron and hole concentrations in the charge-neutral region, respectively, given by n 0 = n i e φ Fn/ p 0 = n i e φ Fp/ A8 A9 e φ Fp/ = e V / e φ Fp/ + N A N D. A13 n i Equation A13 can be written in the form of a quadratic equation 2 e φ Fp/ v φf th 2sinh e φ Fp/ e V / =0 A14 in which A3 has been used. The solution of A14 is given by [ ] φf φ Fp = ln sinh + sinh 2 φf + e v V / th = ln N NA 2 A N D N D + + e 2n i 2n V /. i A15 It can be seen that when V = 0 MOS capacitor, A15 becomes A3 i.e., φ Fp = φ F based on the identity sinh 1 x =ln x + x A16 Also, for undoped pure silicon, N A = N D =0; hence, from A15, we have φ Fp = V/2, and φ Fn = V + φ Fp = V/2. Fig. 6 plots the hole quasi-fermi potential modeled by A15 as a function of net doping concentration for various channel voltages at room temperature including forward-bias of the source/drain body junctions due to bias at the bulk terminal in a bulk-mos; for DG, there will be no forward bias. It can be seen that for body net doping larger than the intrinsic carrier concentration at the given temperature, nonequilibrium model A15 is essentially the same as the model A3 as conventionally assumed, i.e., holes in the body can always be assumed being at equilibrium. However, nonequilibrium or high-level injection effects [18], [19] cannot be neglected for pure or below-intrinsic devices in which imrefs of both carrier types should be considered. On the other hand, since φ Fp φ F when N A N D n i, this plot also explains why truly bipolar - FET drift-diffusion behavior will be difficult to be observed in practical devices due to difficulties in fabricating transistors on nearly-pure silicon films.

8 622 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 2, FEBRUARY 2008 ACKNOWLEDGMENT X. Zhou would like to thank Prof. C.-T. Sah for invaluable discussions on two-carrier transport in pure thin-base DG modeling. REFERENCES [1] H. R. Farrah and R. F. Steinberg, Analysis of double-gate thin-film transistor, IEEE Trans. Electron Devices, vol.ed-14,no.2,pp.69 74,Feb [2] C.-T. Sah and H. Pao, The effects of fixed bulk charge on the characteristics on metal-oxide-semiconductor transistors, IEEE Trans. Electron Devices, vol. ED-13, no. 4, pp , Apr [3] H. Pao and C.-T. Sah, Effects of diffusion current on characteristics of metal-oxide insulator-semiconductor transistors, Solid-State Electron., vol. 9, no. 10, pp , [4] A. Ortiz-Conde, F. J. García Sánchez, P. E. Schmidt, and A. Sa-Neto, The foundation of a charge-sheet model for the thin-film MOSFET, Solid-State Electron., vol. 31, no. 10, pp , [5] A. Ortiz-Conde, R. Herrera, P. E. Schmidt, F. J. García Sánchez, and J. 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Malobabic, and J. J. Liou, A review of core compact models for undoped double-gate SOI MOS- FETs, IEEE Trans. Electron Devices, vol. 54, no. 1, pp , Jan [12] Z. M. Zhu, X. Zhou, K. Chandrasekaran, S. C. Rustagi, and G. H. See, Explicit compact surface-potential and drain-current models for generic asymmetric double-gate MOSFETs, Jpn. J. Appl. Phys.,vol.46,no.4B, pp , [13] X. Shi and M. Wong, Analytical solutions to the one-dimensional oxidesilicon-oxide system, IEEE Trans. Electron Devices, vol. 50, no. 8, pp , Aug [14] M. Wong and X. Shi, Analytical I-V relationship incorporating fielddependent mobility for a symmetrical DG MOSFET with an undoped body, IEEE Trans. Electron Devices, vol. 53, no. 6, pp , Jun [15] M. Wong and X. Shi, On the threshold voltage of symmetrical doublegate metal-oxide-semiconductor capacitor with intrinsic silicon body, IEEE Trans. Electron Devices, vol. 51, no. 10, pp , Oct [16] A. R. Boothroyd, S. W. Taraswicz, and C. Slaby, MISNAN A physically based continuous MOSFET model for CAD applications, IEEE Trans. CAD, vol. 10, no. 12, pp , Dec [17] R. H. Kingston and S. F. Neustadter, Calculation of the space charge, electric field, and free carrier concentration at the surface of a semiconductor, J. Appl. Phys., vol. 26, no. 6, pp , Jun [18] C. T. Sah, A history of MOS transistor compact modeling, in Proc. NSTI Nanotech 2005, Anaheim, May, vol. WCM, pp [19] C.-T. Sah, private communication before first submission of this manuscript Also see late news paper: C.-T. Sah and B. B. Jie, Doublegate thin-base MOS transistor: the correct theory, presented at NSTI Nanotech, Santa Clara, CA, May [Online]. Abstract available: [20] X. Zhou, G. H. See, G. J. Zhu, K. Chandrasekaran, Z. M. Zhu, S. C. Rustagi, S. H. Lin, C. Q Wei, and G. H. Lim, Unified compact model for generic double-gate MOSFETs, in Proc. NSTI Nanotech, Santa Clara, CA, vol. 3, May 2007, pp Xing Zhou S 88 M 91 SM 99 received the B.E. degree in semiconductor physics from Tsinghua University, Beijing, China, in 1983, and the M.S. and Ph.D. degrees in electrical engineering from the University of Rochester, Rochester, NY, in 1987 and 1990, respectively. From 1990 to 1991, he was a Research Associate in the Department of Electrical Engineering, University of Rochester, where he worked on hot-carrier injection phenomena in MOS devices, as well as development of computer-aided design CAD tools for mixed-signal circuit simulation. From 1992 to 1995, he was a Research Fellow with the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore, where he worked on Monte Carlo and numerical modeling of semiconductor and optoelectronic devices as well as mixed-signal circuit modeling and simulation, and is currently an Associate Professor, teaching and researching deep-submicrometer CMOS technology and device modeling. In November and December 1997 as well as in February and March 2001, he was a Visiting Fellow with the Center for Integrated Systems, Stanford University, Stanford, CA. In January 2003, he was a Visiting Professor with Hiroshima University, Japan. In May 2007, he was a Visiting Professor with Universiti Teknologi Malaysia, Malaysia. His current research interests include the area of semiconductor device physics and modeling, novel device structures, compact model development for advanced devices, technology modeling and simulation, mixed-signal CAD tools, hot-carrier transport, and ultrafast phenomena. Dr. Zhou is an elected member of the IEEE Electron Devices Society EDS Administrative Committee, the Chair of the EDS Asia Pacific Subcommittee for Regions/Chapters, a member of the EDS Compact Modeling and VLSI Technology and Circuits Technical Committees as well as the Educational Activities, Publications, and Membership Committees, an EDS Newsletter Editor for Region 10 Australia, New Zealand,and South Asia, an EDS Distinguished Lecturer, and an Editor of the IEEE ELECTRON DEVICE LETTERS. He received the 2006 Nano Science and Technology Institute NSTI Fellowship Award. He is listed in the Marquis Who s Who in the World and Who s Who in Science and Engineering. Since 2002, he has been the Founding Chair of the Workshop on Compact Modeling in association with the NSTI Nanotech Conference. Zhaomin Zhu received the B.S. degree from Nankai University, Tianjin, China, in 1995, and the M.S. and Ph.D. degrees from Fudan University, Shanghai, China, in 1998 and 2002, respectively, all in electrical engineering. From August 2000 to August 2001, he was a Visiting Scholar at the Microelectronics Center of Chemnitz Technique University, Germany. From April 2002 to March 2005, he was a Guest Researcher at the RCNS, Hiroshima University, Japan. Since June 2005, he has been a Research Fellow at Nanyang Technological University, Singapore. His current research interests include the fields of device modeling and circuit design. Subhash C. Rustagi M 95 SM 03 received the M.Sc. and Ph.D. degrees in physics from Kurukshetra University, Kurukshetra, Haryana, India, in 1975 and 1981, respectively. He joined the Centre for Applied Research in Electronics, Indian Institute of Technology, Delhi, India, in In April 1999, he joined the Institute of Microelectronics IME, Singapore, as a Member of Technical Staff, where he was in charge of the devicemodeling group Integrated Circuits and System Laboratory, and since February 2006, he has been with the Semiconductor Process Technology Group. His current research interests include device simulation, modeling and characterization, radio frequency RF model and test chip development, RF ESD electrostatic discharge, and characterization of the device and substrate noise. He has authored or coauthored about 40 papers in refereed journals and conferences.

9 ZHOU et al.: RIGOROUS SURFACE-POTENTIAL SOLUTION FOR UNDOPED SYMMETRIC DG MOSFETS 623 Guan Huei See S 07 received the B.E. degree in electrical/telecommunication engineering in 2002 and the M.Eng. degree in electrical engineering, in 2004, from the Universiti Technologi Malaysia, Johor Bahru Takzim, Malaysia. He is currently working toward the Ph.D. degree in nanometer scalable RF CMOS technology from Nanyang Technological University, Singapore. He was a Postgraduate Intern at Silterra Malaysia from 2002 to He was responsible for developing RF SPICE model for on-chip passive devices, i.e., inductors, capacitors and resistors. His current research interest includes compact modeling of CMOS transistors. Chengqing Wei was born in Suzhou, China. She received the B.S. degree in electrical and electronic engineering in 2006 from Nanyang Technological University, Singapore, where she is currently working toward the Ph.D. degree in the School of Electrical and Electronic Engineering. Her current research interests include semiconductor device compact modeling and compact noise modeling. Guojun Zhu received the B.E. Hons. degree in electrical and electronic engineering in 2007 from Nanyang Technological University, Singapore, where he is currently working toward the Ph.D. degree in electrical and electronic engineering. His current research interests include compact modeling of multiple-gate and Schottky-Barrier MOSFETs. Guan Hui Lim S 06 received the B.Eng. Hons. degree in electrical engineering in 2005 from the National University of Singapore NUS, Singapore. He is currently working toward the M.Eng. degree in electrical and electronic engineering at Nanyang Technological University NTU, Singapore. His current research interests include statistical MOSFET modeling and MOSFET mismatch study with support from Chartered Semiconductor Manufacturing Ltd., Singapore. Shihuan Lin received the B.Sc. degree in electronic engineering from Beijing Institute of Technology, Beijing, China, in 2001, and the M.Sc. degree in microelectronics in 2006 from Nanyang Technology University, Singapore, where he is currently working toward the Ph.D. degree in the School of Electrical and Electronic Engineering. His current research interests include nanoscale device modeling.