Lecture 7 - PN Junction and MOS Electrostatics (IV) Electrostatics of Metal-Oxide-Semiconductor Structure. September 29, 2005

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1 Microelectronic Devices and Circuits - Fall 25 Lecture 7-1 Lecture 7 - PN Junction and MOS Electrostatics (IV) Electrostatics of Metal-Oide-Semiconductor Structure September 29, 25 Contents: 1. Introduction to MOS structure 2. Electrostatics of MOS at zero bias 3. Electrostatics of MOS under bias Reading assignment: Howe and Sodini, Ch. 3,

2 Microelectronic Devices and Circuits - Fall 25 Lecture 7-2 Key questions What is the big deal about the metal-oide-semiconductor structure? What do the electrostatics of the MOS structure look like at zero bias? How do the electrostatics of the MOS structure get modified if a voltage is applied across its terminals?

3 Microelectronic Devices and Circuits - Fall 25 Lecture Introduction Metal-Oide-Semiconductor structure: gate oide ε o = 3.9 ε o metal interconnect to gate n + polysilicon gate p-type ε s = 11.7 ε o metal interconnect to bulk MOS at the heart of the electronics revolution: Digital and analog functions: Metal-Oide-Semiconductor Field-Effect Transistor (MOSFET) is key element of Complementary Metal-Oide-Semiconductor (CMOS) circuit family Memory function: Dynamic Random Access Memory (DRAM) and Flash Erasable Programmable Memory (EPROM) Imaging: Charge-Couple Device (CCD) camera Displays: Active-Matri Liquid-Crystal Displays...

4 Microelectronic Devices and Circuits - Fall 25 Lecture MOS electrostatics at zero bias Idealized 1D structure: "metal" (n+ polysi) contact oide semiconductor (p type) contact -to Metal: does not tolerate volume charge charge can only eist at its surface Oide: insulator no volume charge (no free carriers, no dopants) Semiconductor: can have volume charge (SCR) Thermal equilibrium can t be established through oide; need wire to allow transfer of charge between metal and semiconductor. MOS structure: sandwich of dissimilar materials carrier transfer space-charge region at zero bias built-in potential

5 Microelectronic Devices and Circuits - Fall 25 Lecture 7-5 For most metals on p-si, equilibrium achieved by electrons diffusing from metal to semiconductor and holes from semiconductor to metal: log po, no po Na no ni 2 Na -to do Remember: n o p o = n 2 i Fewer holes near Si/SiO 2 interface ionized acceptors eposed (volume space charge)

6 Microelectronic Devices and Circuits - Fall 25 Lecture 7-6 Space charge density log po, no Na po no ni 2 Na -to do ρ ο QG -to do -qna In semiconductor: space-charge region close to Si/SiO 2 interface can do depletion approimation In metal: sheet of charge at metal/sio 2 interface Overall charge neutrality t o ρ o () =Q G δ( t o ) t o << ρ o () = < < do ρ o () = qn a do < ρ o () =

7 Microelectronic Devices and Circuits - Fall 25 Lecture 7-7 Electric field Integrate Gauss equation: E o ( 2 ) E o ( 1 )= 1 ɛ 2 1 ρ o ()d At interface between oide and semiconductor: change in permittivity change in electric field ɛ o E o = ɛ s E s E o E s = ɛ s ɛ o 3 E Eo Es

8 Microelectronic Devices and Circuits - Fall 25 Lecture 7-8 Start integrating from deep inside semiconductor: ρ ο -to do -qna Eο Eo Es -to do do < E o () = < < do E o () = qn a ɛ s ( do ) t o << E o () = ɛ s ɛ o E o ( = + )= qn a do ɛ o < t o E o () =

9 Microelectronic Devices and Circuits - Fall 25 Lecture 7-9 Electrostatic potential (with φ o = p o = n i ) φ = kt q ln n o n i φ = kt q ln p o n i In QNR s, n o and p o known can determine φ: in n + gate: n o = N + d φ g = φ n + in p-qnr: p o = N a φ p = kt q ln N a n i φο φn+ φ B -to do φp Built-in potential: φ B = φ g φ p = φ n + + kt q ln N a n i

10 Microelectronic Devices and Circuits - Fall 25 Lecture 7-1 To get φ o (), integrate E o (); start from deep inside semiconductor bulk: φ o ( 2 ) φ o ( 1 )= 2 1 E o ()d Eο Eo Es -to do φο φn+ φb -to do Vo,o VB,o φp do < φ o () =φ p < < d φ o () =φ p + qn a 2ɛ s ( do ) 2 t o << φ o () =φ p + qn a 2 do 2ɛ s + qn a do ( ) ɛ o < t o φ o () =φ n +

11 Microelectronic Devices and Circuits - Fall 25 Lecture 7-11 Still don t know do need one more equation: Potential difference across structure has to add up to φ B : φ B = V B,o + V o,o = qn a 2 do 2ɛ s + qn a do t o ɛ o Solve quadratic equation: do = ɛ s t o [ 1+ 2ɛ2 oφ B ɛ o ɛ s qn a t 2 o 1] = ɛ s [ 1+ 4φ B C o γ 1] 2 where C o is capacitance per unit area of oide [units: F/cm 2 ]: C o = ɛ o t o and γ is body factor coefficient [units: V 1/2 ]: γ = 1 2ɛs qn a C o

12 Microelectronic Devices and Circuits - Fall 25 Lecture 7-12 Numerical eample: N d =1 2 cm 3,N a =1 17 cm 3,t o =8nm φ B = 55 mv + 42 mv = 97 mv C o = F/cm 2 γ =.43 V 1/2 do =91nm

13 Microelectronic Devices and Circuits - Fall 25 Lecture 7-13 There are also contact potentials total contact-to-contact potential difference is zero! "metal" contact oide semiconductor (p type) contact φο φn+ φb -to do φp

14 Microelectronic Devices and Circuits - Fall 25 Lecture MOS electrostatics under bias Apply voltage to gate with respect to semiconductor: "metal" (n+ polysi) VGB + - contact oide semiconductor (p type) contact -to Electrostatics of MOS structure affected potential difference across entire structure now. How is potential difference accommodated? Potential can drop in: gate contact n + -polysilicon gate oide semiconductor SCR semiconductor QNR semiconductor contact

15 Microelectronic Devices and Circuits - Fall 25 Lecture 7-15 Potential difference shows up across oide and SCR in semiconductor: φ V GB -t o? do φ B φ B +V GB Oide is insulator no current anywhere in structure In SCR, quasi-equilibrium situation prevails new balance between drift and diffusion electrostatics qualitatively identical to zero bias (but amount of charge redistribution is different) np = n 2 i

16 Microelectronic Devices and Circuits - Fall 25 Lecture 7-16 Apply V GB > : potential difference across structure increases need larger charge dipole SCR epands into semiconductor substrate: ρ -to d -qna E Eo Es -to d φ VGB= VGB> φb+vgb φb -to d log p, n Na p n ni 2 Na -to d Simple way to remember: with V GB >, gate attracts electrons and repels holes.

17 Microelectronic Devices and Circuits - Fall 25 Lecture 7-17 Qualitatively, physics unchanged by applying V GB >. Use mathematical formulation of zero bias, but: φ B φ B + V GB For eample, d (V GB )= ɛ s [ 1+ 4(φ B + V GB ) 1] C o γ 2 V GB d

18 Microelectronic Devices and Circuits - Fall 25 Lecture 7-18 Key conclusions Charge redistribution in MOS structure at zero bias: SCR in semiconductor built-in potential across MOS structure. In most cases, can do depletion approimation in semiconductor SCR. Application of voltage modulates depletion region width in semiconductor. No current flows.

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