EE105  Spring 2007 Microelectronic Devices and Circuits. Structure and Symbol of MOSFET. MOS Capacitor. MetalOxideSemiconductor (MOS) Capacitor


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1 EE105  Spring 007 Microelectronic Device and ircuit MetalOideSemiconductor (MOS) apacitor Lecture 4 MOS apacitor The MOS tructure can be thought of a a parallelplate capacitor, with the top plate being the poitive plate, ide being the dielectric, and Si ubtrate being the negative plate. (We are auming Pubtrate.) Structure and Symbol of MOSFET MOS apacitor = = Thi device i ymmetric, o either of the n+ region can be ource or drain. 3 MOS = Metal Oide Semiconductor Metal i more commonly a heavily doped (n+ or p+) polyilicon layer NMOS ptype ubtrate PMOS ntype ubtrate 4
2 harge Ditribution at Thermal Equilibrium Potential Ditribution for MOS apacitor (n+ Gate on psubtrate with N a =10 17 cm 3 ) φ + = 550 m n (half of bandgap energy) Depletion Width in Subtrate Na φp = 60 m log Gate charge at poly/ide interface Bulk charge in the letion region of Si ubtrate Oide i an inulator No current flowing through ide 5 Step to contruct the potential ditribution: Gate potential i contant (550 m for n+ gate, 550 m for p+ gate) Potential of neutral ubtrate i contant, it value end on doping onnect the potential between gate and neutral ubtrate (qualitatively) Potential varie linearly in ide Potential varie quadratically in the letion region of ubtrate 6 Flatband oltage < : Accumulation oltage required to produce a flat potential profile = ( φ φ ) n+ p Eample: 17 3 Na = 10 cm, φp = 60m 7 = 40m φn+ = 550m = 970m No net charge at flatband Majority carrier (hole for p ubtrate) accumulate at the SiSiO interface Occur when gate bia i below flatband voltage: < harge ditribution: Two delta function QG = ( ) = [F/cm ] t 7 8
3 < < Tn : Depletion The majority carrier in Si near ide interface are leted Occur when gate bia between flatband voltage and threhold voltage harge ditribution: Gate charge at poly/sio interface Fied acceptor ion in letion region Depletion (cont d) + φ φ = + n+ p B qnad qnad = + = d ( ) = t 1+ 1 q N a 9 10 > Tn : Inverion An inverion layer with minority carrier (electron in pubtrate) i developed at SiSiO interface Occur when gate bia i higher than threhold voltage harge ditribution: Gate charge: delta function Inverion layer: delta function Fied impurity charge: contant in letion region 11 Inverion (ont d) Electron concentration at Si SiO interface qφ kt = i = a n ne N φ = φp Threhold voltage: 1 Tn = φ p + q Na ( φp ) After threhold ( > Tn ), φ i pinned at  φ p Inverion charge = 0 at threhold 1
4 Inverion Stop Depletion Q urve for MOS apacitor A imple apprimation i to aume that once inverion happen, the letion region top growing Thi i a good aumption ince the inverion charge i an eponential function of the urface potential Under thi condition: accumulation Q G letion Tn inverion Q B,ma Q ( ) N ( ) Q ( ) Q G Tn B,ma Q ( ) = ( ) Q G Tn B,ma 13 In accumulation, the charge i imply proportional to the applied gatebody bia In inverion, the ame i true In letion, the charge grow lower ince the voltage i applied over a letion region 14 Numerical Eample Numerical Eample: Electric Field in Oide MOS apacitor with ptype ubtrate: 16 3 t = 0nm N a = 5 10 cm alculate flatband: = ( φ + φp ) = (550 ( 40)) = 0.95 n alculate threhold voltage: F/cm = = 6 t 10 cm 1 Tn = φ p + q Na ( φp ) Tn =.95 ( 0.4) + = Apply a gatetobody voltage: =.5 < Device i in accumulation The entire voltage drop i acro the ide: E + φ + φ n p ( 0.4) = = = = 8 10 t t The charge in the ubtrate (body) conit of hole: cm Q = ( ) = /cm B 7 16
5 Numerical Eample: Depletion Region MOS urve In inverion, what the letion region width and charge? B,ma = φ φp = φp φp = φp = 0.8 Q G Q B,ma Q ( ) N X B,ma 1 qn a = X B,ma d,ma = = qna d,ma 144nm QB,ma = qnaxd,ma = /cm 7 Tn ( ) Smallignal capacitance i lope of Q curve apacitance i linear in accumulation and inverion apacitance in letion region i mallet apacitance i nonlinear in letion Tn urve Equivalent ircuit = tot In accumulation mode the capacitance i jut due to the voltage drop acro t In inverion the incremental charge come from the inverion layer (letion region top growing). In letion region, the voltage drop i acro the ide and the letion region = = = t 19 MOS apacitor: n+ Gate on ntype Subtrate φ + = 550 m n Tp t 1 Tp = φn q Nd ( φn) φ n Nd φn = 60 m log
6 MOS apacitor: n+ Gate on ntype Subtrate 1
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