Lecture 8 PN Junction and MOS Electrostatics (V) Electrostatics of Metal Oxide Semiconductor Structure (cont.) October 4, 2005


 Augusta Weaver
 3 years ago
 Views:
Transcription
1 6.12 Microelectronic Devices and Circuits Fall 25 Lecture 8 1 Lecture 8 PN Junction and MOS Electrostatics (V) Electrostatics of Metal Oide Semiconductor Structure (cont.) Contents: October 4, Overview of MOS electrostatics under bias 2. Depletion regime 3. Flatband 4. Accumulation regime 5. Threshold 6. Inversion regime Reading assignment: Howe and Sodini, Ch. 3, Announcements: Quiz 1: 1/13, 7:3 9:3 PM, (lectures #19); open book; must have calculator.
2 6.12 Microelectronic Devices and Circuits Fall 25 Lecture 8 2 Key questions Is there more than one regime of operation of the MOS structure under bias? What does carrier inversion mean and what is the big deal about it? How does the carrier inversion charge depend on the gate voltage?
3 6.12 Microelectronic Devices and Circuits Fall 25 Lecture Overview of MOS electrostatics under bias VGB "metal" (n polysi) contact oide semiconductor (p type) contact to Application of bias: built in potential across MOS structure increases from φ B to φ B V GB oide forbids current flow J = everywhere in semiconductor need drift= diffusion in SCR must maintain boundary condition at Si/SiO 2 interface: E o /E s 3 How can this be accommo dated simultaneously? quasi equilibrium situation with potential build up across MOS equal to φ B V GB
4 6.12 Microelectronic Devices and Circuits Fall 25 Lecture 8 4 Important consequence of quasi equilibrium: Boltzmann relations apply in semiconductor [they were derived starting from J e = J h =] and n() = n i e qφ()/kt p() = n i e qφ()/kt np = 2 n i at every [not the case in p n junction or BJT under bias]
5 6.12 Microelectronic Devices and Circuits Fall 25 Lecture Depletion regime For V GB > gate attracts electrons, repels holes depletion region widens For V GB < gate repels electrons, attracts holes depletion region shrinks ρ to d(vgb) q E Eo Es to d(vgb) φ VGB< VGB= VGB> φ BVGB φ B to d(vgb) log p, n p to n d(vgb) ni 2
6 6.12 Microelectronic Devices and Circuits Fall 25 Lecture 8 6 In depletion regime, all results obtained for zero bias apply if φ B φ B V GB. For eample: depletion region thickness: ɛ s d (V GB )= [ C o 4(φ B V GB ) 1 1] γ 2 potential drop across semiconductor SCR: V B (V GB )= 2 qn a d (V GB ) 2ɛ s potential drop across oide: V o (V GB )= qn a d (V GB )t o ɛ o
7 6.12 Microelectronic Devices and Circuits Fall 25 Lecture Flatband At a certain negative V GB, depletion region is wiped out Flatband ρ ρ= to E Eo= Es= to φ VGB= VGB=VFB VGB=φ B to log p, n p to n ni 2 Flatband voltage: V FB = φ B
8 6.12 Microelectronic Devices and Circuits Fall 25 Lecture Accumulation regime If V GB <V FB accumulation of holes at Si/SiO 2 interface ρ to E to Es Eo φ to VGBVFB log p, n p n ni 2 to
9 6.12 Microelectronic Devices and Circuits Fall 25 Lecture Threshold Back to V GB >. For sufficiently large V GB >, electrostatics change when n() = N a threshold. Beyond threshold, cannot neglect contributions of electrons towards electrostatics. log p, n n()= p n ni 2 to dma Let s compute the voltage (threshold voltage) that leads to n() = N a. Key assumption: use electrostatics of depletion (neglect electron concentration at threshold).
10 6.12 Microelectronic Devices and Circuits Fall 25 Lecture 8 1 Computation of threshold voltage. Three step process: First, compute potential drop in semiconductor at threshold. Start from: Solve for φ() at V GB = V T : n() = n i e qφ()/kt kt n() kt N a φ() VT = ln V T = ln = φ p q ni q φ n i VTφ B φ p t o dma VB=2φ p φ p Hence: V B (V T )= 2φ p
11 6.12 Microelectronic Devices and Circuits Fall 25 Lecture 8 11 Second, compute potential drop in oide at threshold. Obtain d (V T ) using relationship between V B and d in depletion: Solve for d (V T ): V B (V T )= 2 qn a d (V T ) 2ɛ s = 2φ p d (V T )= dma = 2ɛ s ( 2φ p ) qn a Then: V o (V T )= E o (V T )t o = qn a d (V T ) t o = γ 2φ p ɛ o φ Vo VTφ B φ p t o dma VB=2φ p φ p
12 6.12 Microelectronic Devices and Circuits Fall 25 Lecture 8 12 Finally, sum potential drops across structure. φ Vo VTφ B φ p t o dma VB=2φ p φ p V T φ B = V B (V T ) V o (V T )= 2φ p γ 2φ p Solve for V T : V T = V FB 2φ p γ 2φ p Key dependencies: If N a V T. The higher the doping level, the more voltage required to produce n() = N a. If C o (t o ) V T. The thinner the oide, the less voltage dropped across it.
13 6.12 Microelectronic Devices and Circuits Fall 25 Lecture Inversion What happens for V GB >V T? More electrons at Si/SiO 2 interface than acceptors inversion. log p, n inversion layer n p ni 2 to dma Electron concentration at Si/SiO 2 interface modulated by V GB V GB n() Q n field effect control of mobile charge! [essence of MOSFET] Want to compute Q n vs. V GB [charge control relation] Make sheet charge approimation: electron layer at semiconductor surface is much thinner than any other dimension in problem (t o, d ).
14 6.12 Microelectronic Devices and Circuits Fall 25 Lecture 8 14 Charge control relation Let us look at overall electrostatics: ρ to dma q Qn E Eo Es to dma φ VGBφ B t o dma log p, n n to dma p ni 2
15 6.12 Microelectronic Devices and Circuits Fall 25 Lecture 8 15 Key realization: Q n n() e qφ()/kt Q B φ() Hence, as V GB and φ(), Q B will change very little. Q n will change a lot, but Several consequences: little change in φ() beyond threshold V B does not increase much beyond V B (V T )= 2φ p (a thin sheet of electrons does not contribute much to V B ): V B (inv.) V B (V T )= 2φ p little change in Q B beyond threshold d does not increase much beyond threshold: d (inv.) d (V T )= 2ɛ s ( 2φ p ) qn a = dma
16 6.12 Microelectronic Devices and Circuits Fall 25 Lecture 8 16 All etra voltage beyond V T used to increase inversion charge Q n. Think of it as capacitor: top plate: metal gate bottom plate: inversion layer Q = CV Q n = C o (V GB V T ) for V GB >V T Eistence of Q n and control over Q n by V GB key to MOS electronics Qn C o VT VGB
17 6.12 Microelectronic Devices and Circuits Fall 25 Lecture 8 17 Key conclusions V GB <V FB M O S (ptype) accumulation V GB =V FB flatband V FB <V GB < depletion V GB = zero bias <V GB <VT V GB =VT V GB >VT depletion threshold inversion In inversion: Q n = C o (V GB V T ) for V GB >V T
Lecture 7 PN Junction and MOS Electrostatics(IV) Metal Oxide Semiconductor Structure (contd.)
Lecture 7 PN Junction and MOS Electrostatics(IV) Metal Oxide Semiconductor Structure (contd.) Outline 1. Overview of MOS electrostatics under bias 2. Depletion regime 3. Flatband 4. Accumulation regime
More informationLecture 7  PN Junction and MOS Electrostatics (IV) Electrostatics of MetalOxideSemiconductor Structure. September 29, 2005
6.12  Microelectronic Devices and Circuits  Fall 25 Lecture 71 Lecture 7  PN Junction and MOS Electrostatics (IV) Electrostatics of MetalOideSemiconductor Structure September 29, 25 Contents: 1.
More informationLecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor
Lecture 15 OUTLINE MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Electrostatics Charge vs. voltage characteristic Reading: Chapter 6.1 6.2.1 EE15 Spring 28 Lecture
More informationLecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor
Lecture 15 OUTLINE MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Electrostatics t ti Charge vs. voltage characteristic Reading: Chapter 6.1 6.2.1 EE105 Fall 2007
More informationLecture 6 PN Junction and MOS Electrostatics(III) MetalOxideSemiconductor Structure
Lecture 6 PN Junction and MOS Electrostatics(III) MetalOxideSemiconductor Structure Outline 1. Introduction to MOS structure 2. Electrostatics of MOS in thermal equilibrium 3. Electrostatics of MOS with
More informationLecture 4  PN Junction and MOS Electrostatics (I) Semiconductor Electrostatics in Thermal Equilibrium September 20, 2005
6.012  Microelectronic Devices and Circuits  Fall 2005 Lecture 41 Contents: Lecture 4  PN Junction and MOS Electrostatics (I) Semiconductor Electrostatics in Thermal Equilibrium September 20, 2005
More informationLecture 4  PN Junction and MOS Electrostatics (I) Semiconductor Electrostatics in Thermal Equilibrium. February 13, 2003
6.012  Microelectronic Devices and Circuits  Spring 2003 Lecture 41 Contents: Lecture 4  PN Junction and MOS Electrostatics (I) Semiconductor Electrostatics in Thermal Equilibrium February 13, 2003
More informationElectrical Characteristics of MOS Devices
Electrical Characteristics of MOS Devices The MOS Capacitor Voltage components Accumulation, Depletion, Inversion Modes Effect of channel bias and substrate bias Effect of gate oide charges Thresholdvoltage
More informationMicroelectronic Devices and Circuits Lecture 9  MOS Capacitors I  Outline Announcements Problem set 5 
6.012  Microelectronic Devices and Circuits Lecture 9  MOS Capacitors I  Outline Announcements Problem set 5  Posted on Stellar. Due net Wednesday. Qualitative description  MOS in thermal equilibrium
More informationLecture 13  Carrier Flow (cont.), MetalSemiconductor Junction. October 2, 2002
6.72J/3.43J  Integrated Microelectronic Devices  Fall 22 Lecture 131 Contents: Lecture 13  Carrier Flow (cont.), MetalSemiconductor Junction October 2, 22 1. Transport in spacecharge and highresistivity
More informationLecture 15  The pn Junction Diode (I) IV Characteristics. November 1, 2005
6.012  Microelectronic Devices and Circuits  Fall 2005 Lecture 151 Lecture 15  The pn Junction Diode (I) IV Characteristics November 1, 2005 Contents: 1. pn junction under bias 2. IV characteristics
More informationLecture 22  The Si surface and the MetalOxideSemiconductor Structure (cont.) April 2, 2007
6.720J/3.43J  Integrated Microelectronic Devices  Spring 2007 Lecture 221 Lecture 22  The Si surface and the MetalOxideSemiconductor Structure (cont.) April 2, 2007 Contents: 1. Ideal MOS structure
More informationLecture 12: MOS Capacitors, transistors. Context
Lecture 12: MOS Capacitors, transistors Context In the last lecture, we discussed PN diodes, and the depletion layer into semiconductor surfaces. Small signal models In this lecture, we will apply those
More informationLecture 04 Review of MOSFET
ECE 541/ME 541 Microelectronic Fabrication Techniques Lecture 04 Review of MOSFET Zheng Yang (ERF 3017, email: yangzhen@uic.edu) What is a Transistor? A Switch! An MOS Transistor V GS V T V GS S Ron D
More informationWeek 3, Lectures 68, Jan 29 Feb 2, 2001
Week 3, Lectures 68, Jan 29 Feb 2, 2001 EECS 105 Microelectronics Devices and Circuits, Spring 2001 Andrew R. Neureuther Topics: M: Charge density, electric field, and potential; W: Capacitance of pn
More informationLecture 16  The pn Junction Diode (II) Equivalent Circuit Model. April 8, 2003
6.012  Microelectronic Devices and Circuits  Spring 2003 Lecture 161 Lecture 16  The pn Junction Diode (II) Equivalent Circuit Model April 8, 2003 Contents: 1. IV characteristics (cont.) 2. Smallsignal
More informationEECS130 Integrated Circuit Devices
EECS130 Integrated Circuit Devices Professor Ali Javey 10/02/2007 MS Junctions, Lecture 2 MOS Cap, Lecture 1 Reading: finish chapter14, start chapter16 Announcements Professor Javey will hold his OH at
More informationLecture 22 FieldEffect Devices: The MOS Capacitor
Lecture 22 FieldEffect Devices: The MOS Capacitor F. Cerrina Electrical and Computer Engineering University of Wisconsin Madison Click here for link to F.C. homepage Spring 1999 0 Madison, 1999II Topics
More informationLecture 17  pn Junction. October 11, Ideal pn junction in equilibrium 2. Ideal pn junction out of equilibrium
6.72J/3.43J  Integrated Microelectronic Devices  Fall 22 Lecture 171 Lecture 17  pn Junction October 11, 22 Contents: 1. Ideal pn junction in equilibrium 2. Ideal pn junction out of equilibrium
More informationECE 340 Lecture 39 : MOS Capacitor II
ECE 340 Lecture 39 : MOS Capacitor II Class Outline: Effects of Real Surfaces Threshold Voltage MOS CapacitanceVoltage Analysis Things you should know when you leave Key Questions What are the effects
More informationSection 12: Intro to Devices
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals Bond Model of Electrons and Holes Si Si Si Si Si Si Si Si Si Silicon
More informationElectronic Devices and Circuits Lecture 5  pn Junction Injection and Flow  Outline
6.012  Electronic Devices and Circuits Lecture 5  pn Junction Injection and Flow  Outline Review Depletion approimation for an abrupt pn junction Depletion charge storage and depletion capacitance
More information! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cutoff. " Depletion.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 9, 019 MOS Transistor Theory, MOS Model Lecture Outline CMOS Process Enhancements Semiconductor Physics Band gaps Field Effects
More informationLecture 9 MOSFET(II) MOSFET I V CHARACTERISTICS(contd.)
Lecture 9 MOSFET(II) MOSFET I V CHARACTERISTICS(contd.) Outline 1. The saturation region 2. Backgate characteristics Reading Assignment: Howe and Sodini, Chapter 4, Section 4.4 6.012 Spring 2009 Lecture
More informationLecture 7  Carrier Drift and Diffusion (cont.) February 20, Nonuniformly doped semiconductor in thermal equilibrium
6.720J/3.43J  Integrated Microelectronic Devices  Spring 2007 Lecture 71 Lecture 7  Carrier Drift and Diffusion (cont.) February 20, 2007 Contents: 1. Nonuniformly doped semiconductor in thermal equilibrium
More informationLecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: MOSFET NType, PType. Semiconductor Physics.
ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 24, 217 MOS Transistor Theory, MOS Model Lecture Outline! Semiconductor Physics " Band gaps " Field Effects! MOS Physics " Cutoff
More informationLecture 6  PN Junction and MOS Electrostatics (III) Electrostatics of pn Junction under Bias February 27, 2001
6.012 Microelectronic Devices and Circuits Spring 2001 Lecture 61 Lecture 6 PN Junction and MOS Electrostatics (III) Electrostatics of pn Junction under Bias February 27, 2001 Contents: 1. electrostatics
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 24, 2017 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2017 Khanna Lecture Outline! Semiconductor Physics " Band gaps "
More informationMOS Capacitors ECE 2204
MOS apacitors EE 2204 Some lasses of Field Effect Transistors MetalOxideSemiconductor Field Effect Transistor MOSFET, which will be the type that we will study in this course. MetalSemiconductor Field
More informationDepartment of Electrical and Computer Engineering, Cornell University. ECE 3150: Microelectronics. Spring Due on March 01, 2018 at 7:00 PM
Department of Electrical and Computer Engineering, Cornell University ECE 3150: Microelectronics Spring 2018 Homework 4 Due on March 01, 2018 at 7:00 PM Suggested Readings: a) Lecture notes Important Note:
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 29, 2019 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2019 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor
More informationLecture 23  The Si surface and the MetalOxideSemiconductor Structure (cont.) April 4, 2007
6.720J/3.43J Integrated Microelectronic Devices Spring 2007 Lecture 231 Lecture 23 The Si surface and the MetalOxideSemiconductor Structure (cont.) April 4, 2007 Contents: 1. Ideal MOS structure under
More information! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cutoff. " Depletion.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 3, 018 MOS Transistor Theory, MOS Model Lecture Outline! CMOS Process Enhancements! Semiconductor Physics " Band gaps " Field Effects!
More informationLecture 2. Introduction to semiconductors Structures and characteristics in semiconductors
Lecture 2 Introduction to semiconductors Structures and characteristics in semiconductors Semiconductor pn junction Metal Oxide Silicon structure Semiconductor contact Literature Glen F. Knoll, Radiation
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 23, 2018 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2018 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor
More informationn N D n p = n i p N A
Summary of electron and hole concentration in semiconductors Intrinsic semiconductor: E G n kt i = pi = N e 2 0 Donordoped semiconductor: n N D where N D is the concentration of donor impurity Acceptordoped
More informationFIELDEFFECT TRANSISTORS
FIELEFFECT TRANSISTORS 1 Semiconductor review 2 The MOS capacitor 2 The enhancementtype NMOS transistor 3 IV characteristics of enhancement MOSFETS 4 The output characteristic of the MOSFET in saturation
More informationEE105  Spring 2007 Microelectronic Devices and Circuits. Structure and Symbol of MOSFET. MOS Capacitor. MetalOxideSemiconductor (MOS) Capacitor
EE105  Spring 007 Microelectronic Device and ircuit MetalOideSemiconductor (MOS) apacitor Lecture 4 MOS apacitor The MOS tructure can be thought of a a parallelplate capacitor, with the top plate being
More informationEE105  Fall 2006 Microelectronic Devices and Circuits
EE105  Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 7: MOS Transistor Some Administrative Issues Lab 2 this week Hw 2 due on We Hw 3 will be posted same day MIDTERM
More informationSemiconductor Devices. C. Hu: Modern Semiconductor Devices for Integrated Circuits Chapter 5
Semiconductor Devices C. Hu: Modern Semiconductor Devices for Integrated Circuits Chapter 5 Global leader in environmental and industrial measurement Wednesday 3.2. afternoon Tour around facilities & lecture
More informationLecture 8  Carrier Drift and Diffusion (cont.) September 21, 2001
6.720J/3.43J  Integrated Microelectronic Devices  Fall 2001 Lecture 81 Lecture 8  Carrier Drift and Diffusion (cont.) September 21, 2001 Contents: 1. Nonuniformly doped semiconductor in thermal equilibrium
More information6.012 Electronic Devices and Circuits
Page 1 of 12 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits FINAL EXAMINATION Open book. Notes: 1. Unless
More informationFinal Examination EE 130 December 16, 1997 Time allotted: 180 minutes
Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes Problem 1: Semiconductor Fundamentals [30 points] A uniformly doped silicon sample of length 100µm and crosssectional area 100µm 2
More informationLecture 11: MOS Transistor
Lecture 11: MOS Transistor Prof. Niknejad Lecture Outline Review: MOS Capacitors Regions MOS Capacitors (3.8 3.9) CV Curve Threshold Voltage MOS Transistors (4.1 4.3): Overview Crosssection and layout
More informationMOS CAPACITOR AND MOSFET
EE336 Semiconductor Devices 1 MOS CAPACITOR AND MOSFET Dr. Mohammed M. Farag Ideal MOS Capacitor Semiconductor Devices Physics and Technology Chapter 5 EE336 Semiconductor Devices 2 MOS Capacitor Structure
More informationLecture 2. Introduction to semiconductors Structures and characteristics in semiconductors
Lecture 2 Introduction to semiconductors Structures and characteristics in semiconductors Semiconductor pn junction Metal Oxide Silicon structure Semiconductor contact Literature Glen F. Knoll, Radiation
More informationLecture 17  The Bipolar Junction Transistor (I) Forward Active Regime. April 10, 2003
6.012  Microelectronic Devices and Circuits  Spring 2003 Lecture 171 Lecture 17  The Bipolar Junction Transistor (I) Contents: Forward Active Regime April 10, 2003 1. BJT: structure and basic operation
More information! PN Junction. ! MOS Transistor Topology. ! Threshold. ! Operating Regions. " Resistive. " Saturation. " Subthreshold (next class)
ESE370: ircuitlevel Modeling, Design, and Optimization for Digital Systems Lec 7: September 20, 2017 MOS Transistor Operating Regions Part 1 Today! PN Junction! MOS Transistor Topology! Threshold! Operating
More informationIntroduction to Power Semiconductor Devices
ECE442 Power Semiconductor Devices and Integrated Circuits Introduction to Power Semiconductor Devices Zheng Yang (ERF 3017, email: yangzhen@uic.edu) Power Semiconductor Devices Applications System Ratings
More informationOperation and Modeling of. The MOS Transistor. Second Edition. Yannis Tsividis Columbia University. New York Oxford OXFORD UNIVERSITY PRESS
Operation and Modeling of The MOS Transistor Second Edition Yannis Tsividis Columbia University New York Oxford OXFORD UNIVERSITY PRESS CONTENTS Chapter 1 l.l 1.2 1.3 1.4 1.5 1.6 1.7 Chapter 2 2.1 2.2
More informationSchottky Rectifiers Zheng Yang (ERF 3017,
ECE442 Power Semiconductor Devices and Integrated Circuits Schottky Rectifiers Zheng Yang (ERF 3017, email: yangzhen@uic.edu) Power Schottky Rectifier Structure 2 MetalSemiconductor Contact The work function
More informationUNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. EECS 130 Professor Ali Javey Fall 2006
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences EECS 130 Professor Ali Javey Fall 2006 Midterm 2 Name: SID: Closed book. Two sheets of notes are
More informationLecture 12: MOSFET Devices
Lecture 12: MOSFET Devices GuYeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background
More informationThe Three terminal MOS structure. Semiconductor Devices: Operation and Modeling 115
The Three terminal MOS structure 115 Introduction MOS transistor two terminal MOS with another two opposite terminal (back to back of inversion layer). Theses two new terminal make the current flow if
More informationEECS130 Integrated Circuit Devices
EECS130 Integrated Circuit Devices Professor Ali Javey 9/18/2007 P Junctions Lecture 1 Reading: Chapter 5 Announcements For THIS WEEK OLY, Prof. Javey's office hours will be held on Tuesday, Sept 18 3:304:30
More informationELEC 3908, Physical Electronics, Lecture 23. The MOSFET Square Law Model
ELEC 3908, Physical Electronics, Lecture 23 The MOSFET Square Law Model Lecture Outline As with the diode and bipolar, have looked at basic structure of the MOSFET and now turn to derivation of a current
More informationSemiconductor Integrated Process Design (MS 635)
Semiconductor Integrated Process Design (MS 635) Instructor: Prof. Keon Jae Lee  Office: 응용공학동 #4306, Tel: #3343  Email: keonlee@kaist.ac.kr Lecture: (Tu, Th), 1:002:15 #2425 Office hour: Tues & Thur
More informationLecture 20  pn Junction (cont.) October 21, Nonideal and secondorder effects
6.70J/3.43J  Integrated Microelectronic Devices  Fall 00 Lecture 01 Lecture 0  pn Junction (cont.) October 1, 00 Contents: 1. Nonideal and secondorder effects Reading assignment: del Alamo, Ch.
More informationChoice of V t and Gate Doping Type
Choice of V t and Gate Doping Type To make circuit design easier, it is routine to set V t at a small positive value, e.g., 0.4 V, so that, at V g = 0, the transistor does not have an inversion layer and
More informationSemiconductor Physics Problems 2015
Semiconductor Physics Problems 2015 Page and figure numbers refer to Semiconductor Devices Physics and Technology, 3rd edition, by SM Sze and MK Lee 1. The purest semiconductor crystals it is possible
More information6.152J / 3.155J Spring 05 Lecture 08 IC Lab Testing. IC Lab Testing. Outline. Structures to be Characterized. Sheet Resistance, Nsquare Resistor
IC Lab Testing Review Process Outline Structures to be Characterized Resistors Sheet Resistance, Nsquare Resistor MOS Capacitors Flatband Voltage, Threshold Voltage, Oxide Thickness, Oxide Charges, Substrate
More informationSemiconductor Junctions
8 Semiconductor Junctions Almost all solar cells contain junctions between different materials of different doping. Since these junctions are crucial to the operation of the solar cell, we will discuss
More informationMOS Capacitor MOSFET Devices. MOSFET s. INEL Solid State Electronics. Manuel Toledo Quiñones. ECE Dept. UPRM.
INEL 6055  Solid State Electronics ECE Dept. UPRM 20th March 2006 Definitions MOS Capacitor Isolated Metal, SiO 2, Si Threshold Voltage qφ m metal d vacuum level SiO qχ 2 E g /2 qφ F E C E i E F E v qφ
More informationLecture 19  pn Junction (cont.) October 18, Ideal pn junction out of equilibrium (cont.) 2. pn junction diode: parasitics, dynamics
6.720J/3.43J  Integrated Microelectronic Devices  Fall 2002 Lecture 191 Lecture 19  pn Junction (cont.) October 18, 2002 Contents: 1. Ideal pn junction out of equilibrium (cont.) 2. pn junction diode:
More informationLecture #27. The Short Channel Effect (SCE)
Lecture #27 ANNOUNCEMENTS Design Project: Your BJT design should meet the performance specifications to within 10% at both 300K and 360K. ( β dc > 45, f T > 18 GHz, V A > 9 V and V punchthrough > 9 V )
More information1st YearComputer Communication EngineeringRUC. 4 PN Junction
4 PN Junction We begin our study of semiconductor devices with the junction for three reasons. (1) The device finds application in many electronic systems, e.g., in adapters that charge the batteries
More informationLecture 16 The pn Junction Diode (III)
Lecture 16 The pn Junction iode (III) Outline I V Characteristics (Review) Small signal equivalent circuit model Carrier charge storage iffusion capacitance Reading Assignment: Howe and Sodini; Chapter
More informationEE105 Fall 2015 Microelectronic Devices and Circuits: Semiconductor Fabrication and PN Junctions
EE105 Fall 2015 Microelectronic Devices and Circuits: Semiconductor Fabrication and PN Junctions Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 pn Junction ptype semiconductor in
More informationECE 342 Electronic Circuits. 3. MOS Transistors
ECE 342 Electronic Circuits 3. MOS Transistors Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to
More informationPN Junction and MOS structure
PN Junction and MOS structure Basic electrostatic equations We will use simple onedimensional electrostatic equations to develop insight and basic understanding of how semiconductor devices operate Gauss's
More informationLongchannel MOSFET IV Corrections
Longchannel MOSFET IV orrections Three MITs of the Day The body ect and its influence on longchannel V th. Longchannel subthreshold conduction and control (subthreshold slope S) Scattering components
More informationan introduction to Semiconductor Devices
an introduction to Semiconductor Devices Donald A. Neamen Chapter 6 Fundamentals of the MetalOxideSemiconductor FieldEffect Transistor Introduction: Chapter 6 1. MOSFET Structure 2. MOS Capacitor 
More informationLecture 2. Introduction to semiconductors Structures and characteristics in semiconductors. Fabrication of semiconductor sensor
Lecture 2 Introduction to semiconductors Structures and characteristics in semiconductors Semiconductor pn junction Metal Oxide Silicon structure Semiconductor contact Fabrication of semiconductor sensor
More informationSection 12: Intro to Devices
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si
More informationLecture 3 Semiconductor Physics (II) Carrier Transport
Lecture 3 Semiconductor Physics (II) Carrier Transport Thermal Motion Carrier Drift Carrier Diffusion Outline Reading Assignment: Howe and Sodini; Chapter 2, Sect. 2.42.6 6.012 Spring 2009 Lecture 3 1
More informationLecture 9  Carrier Drift and Diffusion (cont.), Carrier Flow. September 24, 2001
6.720J/3.43J  Integrated Microelectronic Devices  Fall 2001 Lecture 91 Lecture 9  Carrier Drift and Diffusion (cont.), Carrier Flow September 24, 2001 Contents: 1. QuasiFermi levels 2. Continuity
More informationEE 560 MOS TRANSISTOR THEORY
1 EE 560 MOS TRANSISTOR THEORY PART 1 TWO TERMINAL MOS STRUCTURE V G (GATE VOLTAGE) 2 GATE OXIDE SiO 2 SUBSTRATE ptype doped Si (N A = 10 15 to 10 16 cm 3 ) t ox V B (SUBSTRATE VOLTAGE) EQUILIBRIUM:
More informationESE370: CircuitLevel Modeling, Design, and Optimization for Digital Systems. Today. Refinement. Last Time. No Field. Body Contact
ESE370: CircuitLevel Modeling, Design, and Optimization for Digital Systems Day 10: September 6, 01 MOS Transistor Basics Today MOS Transistor Topology Threshold Operating Regions Resistive Saturation
More informationDepartment of Electrical and Computer Engineering, Cornell University. ECE 3150: Microelectronics. Spring Exam 1 ` March 22, 2018
Department of Electrical and Computer Engineering, Cornell University ECE 3150: Microelectronics Spring 2018 Exam 1 ` March 22, 2018 INSTRUCTIONS: Every problem must be done in the separate booklet Only
More information6.012 Electronic Devices and Circuits
Page 1 of 10 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits Exam No. 2 Thursday, November 5, 2009 7:30 to
More informationLecture Notes 2 ChargeCoupled Devices (CCDs) Part I. Basic CCD Operation CCD Image Sensor Architectures Static and Dynamic Analysis
Lecture Notes 2 ChargeCoupled Devices (CCDs) Part I Basic CCD Operation CCD Image Sensor Architectures Static and Dynamic Analysis Charge Well Capacity Buried channel CCD Transfer Efficiency Readout Speed
More informationLecture 8  Carrier Drift and Diffusion (cont.), Carrier Flow. February 21, 2007
6.720J/3.43J  Integrated Microelectronic Devices  Spring 2007 Lecture 81 Lecture 8  Carrier Drift and Diffusion (cont.), Carrier Flow February 21, 2007 Contents: 1. QuasiFermi levels 2. Continuity
More informationLecture 28  The Long MetalOxideSemiconductor FieldEffect Transistor (cont.) April 18, 2007
6.720J/3.43J  Integrated Microelectronic Devices  Spring 2007 Lecture 281 Lecture 28  The Long MetalOxideSemiconductor FieldEffect Transistor (cont.) April 18, 2007 Contents: 1. Secondorder and
More informationSchottky diodes. JFETs  MESFETs  MODFETs
Technische Universität Graz Institute of Solid State Physics Schottky diodes JFETs  MESFETs  MODFETs Quasi Fermi level When the charge carriers are not in equilibrium the Fermi energy can be different
More informationMOSFET: Introduction
E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major
More informationESE 570 MOS TRANSISTOR THEORY Part 1. Kenneth R. Laker, University of Pennsylvania, updated 5Feb15
ESE 570 MOS TRANSISTOR THEORY Part 1 TwoTerminal MOS Structure 2 GATE Si Oxide interface n n Mass Action Law VB 2 Chemical Periodic Table Donors American Chemical Society (ACS) Acceptors Metalloids 3 Ideal
More informationThe Devices: MOS Transistors
The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, AddisonWesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall NMOS Transistor
More informationSemiconductor Physics and Devices
The pn Junction 1) Charge carriers crossing the junction. 3) Barrier potential Semiconductor Physics and Devices Chapter 8. The pn Junction Diode 2) Formation of positive and negative ions. 4) Formation
More informationLecture 17. The Bipolar Junction Transistor (II) Regimes of Operation. Outline
Lecture 17 The Bipolar Junction Transistor (II) Regimes of Operation Outline Regimes of operation Largesignal equivalent circuit model Output characteristics Reading Assignment: Howe and Sodini; Chapter
More informationLong Channel MOS Transistors
Long Channel MOS Transistors The theory developed for MOS capacitor (HO #2) can be directly extended to MetalOxideSemiconductor FieldEffect transistors (MOSFET) by considering the following structure:
More informationSECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University
NAME: PUID: SECTION: Circle one: Alam Lundstrom ECE 305 Exam 5 SOLUTIONS: April 18, 2016 M A Alam and MS Lundstrom Purdue University This is a closed book exam You may use a calculator and the formula
More informationAppendix 1: List of symbols
Appendix 1: List of symbols Symbol Description MKS Units a Acceleration m/s 2 a 0 Bohr radius m A Area m 2 A* Richardson constant m/s A C Collector area m 2 A E Emitter area m 2 b Bimolecular recombination
More information6.012 Electronic Devices and Circuits
Page 1 of 1 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.12 Electronic Devices and Circuits Exam No. 1 Wednesday, October 7, 29 7:3 to 9:3
More informationL03: pn Junctions, Diodes
8/30/2012 Page 1 of 5 Reference:C:\Users\Bernhard Boser\Documents\Files\Lib\MathCAD\Default\defaults.mcd L03: pn Junctions, Diodes Intrinsic Si Q: What are n, p? Q: Is the Si charged? Q: How could we make
More informationEE105  Fall 2005 Microelectronic Devices and Circuits
EE105  Fall 005 Microelectronic Devices and Circuits ecture 7 MOS Transistor Announcements Homework 3, due today Homework 4 due next week ab this week Reading: Chapter 4 1 ecture Material ast lecture
More informationLecture 18  The Bipolar Junction Transistor (II) Regimes of Operation. November 10, 2005
6.012  Microelectronic Devices and ircuits  Fall 2005 Lecture 181 Lecture 18  The ipolar Junction Transistor (II) ontents: 1. Regimes of operation. Regimes of Operation November 10, 2005 2. Largesignal
More informationReview Energy Bands Carrier Density & Mobility Carrier Transport Generation and Recombination
Review Energy Bands Carrier Density & Mobility Carrier Transport Generation and Recombination The MetalSemiconductor Junction: Review Energy band diagram of the metal and the semiconductor before (a)
More informationECE305: Spring 2018 Exam 2 Review
ECE305: Spring 018 Exam Review Pierret, Semiconductor Device Fundamentals (SDF) Chapter 3 (pp. 75138) Chapter 5 (pp. 1956) Professor Peter Bermel Electrical and Computer Engineering Purdue University,
More informationChapter 7. The pn Junction
Chapter 7 The pn Junction Chapter 7 PN Junction PN junction can be fabricated by implanting or diffusing donors into a Ptype substrate such that a layer of semiconductor is converted into N type. Converting
More informationBipolar junction transistor operation and modeling
6.01  Electronic Devices and Circuits Lecture 8  Bipolar Junction Transistor Basics  Outline Announcements Handout  Lecture Outline and Summary; Old eam 1's on Stellar First Hour Eam  Oct. 8, 7:309:30
More information