A New Surface Potential-based Compact Model for IGZO TFTs in RFID Applications

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1 A New Surface Potential-based Compact Model for IGZO TFTs in RFID Applications Ling Li, Guanhua Yang, Ming Liu Institute of Microelectronics,Chinese Academy of Sciences, China

2 Outline Introduction of IGZO TFT Multiple Trapping and Release Theory Surface Potential and Model Equations RFID Circuit simulation Summary

3 IGZO TFT application-display a-si LTPS a-igzo Organic Mobility(cm 2 /Vs) ~0.5 ~100 10~80 5~6 Uniformity Good Poor Good Poor Reliability Poor Good Good Poor Cost Low High Low Low

4 IGZO TFT application-flexible Circuit Adrian Chasin, et al., An Integrated a-igzo UHF Energy Harvester for Passive RFID Tags Haitian, et al., Large-scale complementatry macroelectronics using hybrid integration of carbon nanotubes and IGZO thin-film transistors Flexible Transparent Room temperature process Low cost

5 IGZO TFT Structure S/D: CrAu L= 5um T=294K

6 Motivation IGZO TFT is an excellent candidate for display and flexible circuit application Circuit designers need accurate but fast compact model The charge transport mechanism in IGZO is different from a-si and organic More physical meaning. Without numerical calculation.

7 Outline Introduction of IGZO TFT Multiple Trapping and Release Theory Surface Potential and Model Equations RFID Circuit simulation Summary

8 Multiple-trapping and release theory Band-like Hopping like Free carrier density Effective mobility Trapped carrier density

9 Multiple-trapping and release theory Gate voltage and temperature dependent mobility,mobility vs. Temperature, at different Gate Voltage

10 Outline Introduction of IGZO TFT Multiple Trapping and Release Theory Surface Potential and Model Equations RFID Circuit simulation Summary

11 Analytical Surface Potential Solution Density of total carrier Poisson s Equation Gauss Law = F(0): The electric field at the interface x=0

12 Analytical Surface Potential Solution Density of states in IGZO Trapped carrier density Final Surface Potential Equation Free carrier Trapped carrier

13 Surface Potential (V) Analytical Surface Potential Solution Taylor expansion Schroder series modification Maximum error : 0.03mV Vch=5V Vch=2.5V Line: Analytic solution Symbol: Numerical result Vg-Vfb (V) Vch=7.5V Fully analytical without adding new fitting parameters

14 Model equations Effective Mobility Equation Drain Current Equation Integrate from FSS to FSD Ids (ua) Line:Model Symbol:Experimental Vg=20V Vg=16V Vg=12V Vds (V)

15 Model equations Capacitance Equations Minkyung Bae, et al., Analytical Current and Capacitance Models for Amorphous IGZO Thin-Film Transistors Ward s chargepartitioning scheme

16 Gummel Symmetry Test Key requirements for GST Odd function Nonsingular for nth-order derivative 1st-order 2nd-order 3rd-order All derivatives are continuous at Vds=0

17 Parameters extraction m0 Parameter initialization Choose fitting strategy Input experimental data RMS lsqerror RMS lsqerror without noise Log RMS lsqerror TA Change convergence condition No Least square method Converge Yes Output fitting parameters n0t0 Exit

18 Ids [A] Ids [A] Parameters extraction 2 x 10-5 Automatic parameter extraction 1.5 data model 1.5 x 10-5 Automatic parameter extraction 1 data model Vds=1V, 20V 0.5 Vgs=-4V, 4V, 12V, 20V Vgs [V] Vds [V] Vds [V] Accurate & Rational

19 Model results Output and gds-vds curves Ids (ua) gds (ms) Line:Model Symbol:Experimental Vg=20V Vg=16V Vg=12V Line: Model Symbol: Measurements Vgs=12V,16V,20V Vds (V) Vds (V) Comparison between the calculation and experimental data for output characteristics of IGZO under different gate voltages and g ds -V ds curves.

20 Ids(A) gm (ms) Model results Transfer and trans-conductance curves 1E-3 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 Line:Model Symbol:Experimental Vds=9.1V Vds=3.1V Vds=0.1V Vg(V) Line: Model Symbol: Measurements Vds=0.1V, 3.1V, 9.1V Vgs (V) Comparison between the calculation and experimental data for transfer characteristics of IGZO under different drain-source voltages and transconductance curves.

21 Ids (ua) Gate capacitance (pf) Model results Temperature and gate capacitance curves Vg=5V Line: Model Symbol: Experiment T=300K T=280K T=260K Vds (V) L=40um L=30um L=20um L=40um L=30um L=20um Line:Model Symbol:Experiment Gate voltage (V) Model results and experimental data a good agreement

22 Outline Introduction of IGZO TFT Multiple Trapping and Release Theory Surface Potential and Model Equations RFID Circuit simulation Summary

23 RFID circuit simulation Verilog-A Module Minkyung Bae, et al., Analytical Current and Capacitance Models for Amorphous IGZO Thin-Film Transistors

24 Vout (V) Frequency (KHz) Simulation results & discussion Pseudo -CMOS W/L=60 W/L= W/L= Vin (V) W/L=50/1 W/L=50/2 W/L=50/ VDD (V)

25 RFID circuit simulation RFID digital circuit block Ring Oscillator Synchronous Counter Synchronous counter 3-8 Decoder BL<1:8> 3-8 Decoder 64bit ROM Manchester Encoder Ring Oscillator Synchronous counter CLK WL<1:8> 3-8 Decoder 64bit ROM DFF Manchester encoder RFID logic output

26 RFID circuit simulation Schematic diagram

27 Simulation results & discussion Failure situation 1: Vdd=5V Driver transistor W/L=35 Minimum power consumption

28 Simulation results & discussion Failure situation 2: Vdd=12V Driver transistor W/L=50 Maximum Clock Frequency

29 Failure voltage (V) Simulation results & discussion Failure voltage at different W/L of driver transistor W/L The shaded area shows available region for V DD and W/L.

30 Simulation results & discussion RFID circuit simulation results Manchester encoded data

31 Summary Incorporated multiple-trapping and release theory into compact modeling Proposed a new method for calculating surface potential analytically Developed the parameter extraction program for IGZO TFT compact model RFID circuit design based on developed model Discussed the maximum operating frequency and minimum power consumption in particular situation

32 Thanks for your attention! Q & A

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