A New Surface Potential-based Compact Model for IGZO TFTs in RFID Applications
|
|
- Ophelia Morris
- 6 years ago
- Views:
Transcription
1 A New Surface Potential-based Compact Model for IGZO TFTs in RFID Applications Ling Li, Guanhua Yang, Ming Liu Institute of Microelectronics,Chinese Academy of Sciences, China
2 Outline Introduction of IGZO TFT Multiple Trapping and Release Theory Surface Potential and Model Equations RFID Circuit simulation Summary
3 IGZO TFT application-display a-si LTPS a-igzo Organic Mobility(cm 2 /Vs) ~0.5 ~100 10~80 5~6 Uniformity Good Poor Good Poor Reliability Poor Good Good Poor Cost Low High Low Low
4 IGZO TFT application-flexible Circuit Adrian Chasin, et al., An Integrated a-igzo UHF Energy Harvester for Passive RFID Tags Haitian, et al., Large-scale complementatry macroelectronics using hybrid integration of carbon nanotubes and IGZO thin-film transistors Flexible Transparent Room temperature process Low cost
5 IGZO TFT Structure S/D: CrAu L= 5um T=294K
6 Motivation IGZO TFT is an excellent candidate for display and flexible circuit application Circuit designers need accurate but fast compact model The charge transport mechanism in IGZO is different from a-si and organic More physical meaning. Without numerical calculation.
7 Outline Introduction of IGZO TFT Multiple Trapping and Release Theory Surface Potential and Model Equations RFID Circuit simulation Summary
8 Multiple-trapping and release theory Band-like Hopping like Free carrier density Effective mobility Trapped carrier density
9 Multiple-trapping and release theory Gate voltage and temperature dependent mobility,mobility vs. Temperature, at different Gate Voltage
10 Outline Introduction of IGZO TFT Multiple Trapping and Release Theory Surface Potential and Model Equations RFID Circuit simulation Summary
11 Analytical Surface Potential Solution Density of total carrier Poisson s Equation Gauss Law = F(0): The electric field at the interface x=0
12 Analytical Surface Potential Solution Density of states in IGZO Trapped carrier density Final Surface Potential Equation Free carrier Trapped carrier
13 Surface Potential (V) Analytical Surface Potential Solution Taylor expansion Schroder series modification Maximum error : 0.03mV Vch=5V Vch=2.5V Line: Analytic solution Symbol: Numerical result Vg-Vfb (V) Vch=7.5V Fully analytical without adding new fitting parameters
14 Model equations Effective Mobility Equation Drain Current Equation Integrate from FSS to FSD Ids (ua) Line:Model Symbol:Experimental Vg=20V Vg=16V Vg=12V Vds (V)
15 Model equations Capacitance Equations Minkyung Bae, et al., Analytical Current and Capacitance Models for Amorphous IGZO Thin-Film Transistors Ward s chargepartitioning scheme
16 Gummel Symmetry Test Key requirements for GST Odd function Nonsingular for nth-order derivative 1st-order 2nd-order 3rd-order All derivatives are continuous at Vds=0
17 Parameters extraction m0 Parameter initialization Choose fitting strategy Input experimental data RMS lsqerror RMS lsqerror without noise Log RMS lsqerror TA Change convergence condition No Least square method Converge Yes Output fitting parameters n0t0 Exit
18 Ids [A] Ids [A] Parameters extraction 2 x 10-5 Automatic parameter extraction 1.5 data model 1.5 x 10-5 Automatic parameter extraction 1 data model Vds=1V, 20V 0.5 Vgs=-4V, 4V, 12V, 20V Vgs [V] Vds [V] Vds [V] Accurate & Rational
19 Model results Output and gds-vds curves Ids (ua) gds (ms) Line:Model Symbol:Experimental Vg=20V Vg=16V Vg=12V Line: Model Symbol: Measurements Vgs=12V,16V,20V Vds (V) Vds (V) Comparison between the calculation and experimental data for output characteristics of IGZO under different gate voltages and g ds -V ds curves.
20 Ids(A) gm (ms) Model results Transfer and trans-conductance curves 1E-3 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 Line:Model Symbol:Experimental Vds=9.1V Vds=3.1V Vds=0.1V Vg(V) Line: Model Symbol: Measurements Vds=0.1V, 3.1V, 9.1V Vgs (V) Comparison between the calculation and experimental data for transfer characteristics of IGZO under different drain-source voltages and transconductance curves.
21 Ids (ua) Gate capacitance (pf) Model results Temperature and gate capacitance curves Vg=5V Line: Model Symbol: Experiment T=300K T=280K T=260K Vds (V) L=40um L=30um L=20um L=40um L=30um L=20um Line:Model Symbol:Experiment Gate voltage (V) Model results and experimental data a good agreement
22 Outline Introduction of IGZO TFT Multiple Trapping and Release Theory Surface Potential and Model Equations RFID Circuit simulation Summary
23 RFID circuit simulation Verilog-A Module Minkyung Bae, et al., Analytical Current and Capacitance Models for Amorphous IGZO Thin-Film Transistors
24 Vout (V) Frequency (KHz) Simulation results & discussion Pseudo -CMOS W/L=60 W/L= W/L= Vin (V) W/L=50/1 W/L=50/2 W/L=50/ VDD (V)
25 RFID circuit simulation RFID digital circuit block Ring Oscillator Synchronous Counter Synchronous counter 3-8 Decoder BL<1:8> 3-8 Decoder 64bit ROM Manchester Encoder Ring Oscillator Synchronous counter CLK WL<1:8> 3-8 Decoder 64bit ROM DFF Manchester encoder RFID logic output
26 RFID circuit simulation Schematic diagram
27 Simulation results & discussion Failure situation 1: Vdd=5V Driver transistor W/L=35 Minimum power consumption
28 Simulation results & discussion Failure situation 2: Vdd=12V Driver transistor W/L=50 Maximum Clock Frequency
29 Failure voltage (V) Simulation results & discussion Failure voltage at different W/L of driver transistor W/L The shaded area shows available region for V DD and W/L.
30 Simulation results & discussion RFID circuit simulation results Manchester encoded data
31 Summary Incorporated multiple-trapping and release theory into compact modeling Proposed a new method for calculating surface potential analytically Developed the parameter extraction program for IGZO TFT compact model RFID circuit design based on developed model Discussed the maximum operating frequency and minimum power consumption in particular situation
32 Thanks for your attention! Q & A
Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson
Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics Lena Peterson 2015-10-13 Outline (1) Why is the CMOS inverter gain not infinite? Large-signal
More informationL ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling
L13 04202017 ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling Scaling laws: Generalized scaling (GS) p. 610 Design steps p.613 Nanotransistor issues (page 626) Degradation
More informationECE 342 Electronic Circuits. 3. MOS Transistors
ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to
More informationComplete Surface-Potential Modeling Approach Implemented in the HiSIM Compact Model Family for Any MOSFET Type
Complete Surface-Potential Modeling Approach Implemented in the HiSIM Compact Model Family for Any MOSFET Type WCM in Boston 15. June, 2011 M. Miura-Mattausch, M. Miyake, H. Kikuchihara, U. Feldmann and
More informationEE 466/586 VLSI Design. Partha Pande School of EECS Washington State University
EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 8 Power Dissipation in CMOS Gates Power in CMOS gates Dynamic Power Capacitance switching Crowbar
More informationANALYSIS AND MODELING OF 1/f NOISE IN IGZO TFTS
ANALYSIS AND MODELING OF 1/f NOISE IN IGZO TFTS Gerard Uriarte, Wondwosen E. Muhea, Benjamin Iñiguez Dep. of Electronic Engineering, University Rovira i Virgili, Tarragona (Spain) Thomas Gneiting AdMOS
More informationAnnouncements. EE141- Fall 2002 Lecture 7. MOS Capacitances Inverter Delay Power
- Fall 2002 Lecture 7 MOS Capacitances Inverter Delay Power Announcements Wednesday 12-3pm lab cancelled Lab 4 this week Homework 2 due today at 5pm Homework 3 posted tonight Today s lecture MOS capacitances
More informationMOS Transistor Theory
CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS
More informationPower Dissipation. Where Does Power Go in CMOS?
Power Dissipation [Adapted from Chapter 5 of Digital Integrated Circuits, 2003, J. Rabaey et al.] Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit
More informationMOS Transistor Properties Review
MOS Transistor Properties Review 1 VLSI Chip Manufacturing Process Photolithography: transfer of mask patterns to the chip Diffusion or ion implantation: selective doping of Si substrate Oxidation: SiO
More informationECE 342 Electronic Circuits. Lecture 6 MOS Transistors
ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2
More informationDigital Integrated Circuits A Design Perspective. Semiconductor. Memories. Memories
Digital Integrated Circuits A Design Perspective Semiconductor Chapter Overview Memory Classification Memory Architectures The Memory Core Periphery Reliability Case Studies Semiconductor Memory Classification
More informationLecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Total Power. Energy and Power Optimization. Worksheet Problem 1
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 20, 2018 Energy and Power Optimization, Design Space Exploration Lecture Outline! Energy and Power Optimization " Tradeoffs! Design
More informationObjective and Outline. Acknowledgement. Objective: Power Components. Outline: 1) Acknowledgements. Section 4: Power Components
Objective: Power Components Outline: 1) Acknowledgements 2) Objective and Outline 1 Acknowledgement This lecture note has been obtained from similar courses all over the world. I wish to thank all the
More informationECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN
ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN CMOS PROCESS CHARACTERIZATION VISHAL SAXENA VSAXENA@UIDAHO.EDU Vishal Saxena DESIGN PARAMETERS Analog circuit designers care about: Open-loop Gain: g m r o
More informationECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter
ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.
More informationSemiconductor Memories
Semiconductor References: Adapted from: Digital Integrated Circuits: A Design Perspective, J. Rabaey UCB Principles of CMOS VLSI Design: A Systems Perspective, 2nd Ed., N. H. E. Weste and K. Eshraghian
More informationInvestigation of the Thermal Noise of MOS Transistors under Analog and RF Operating Conditions
Investigation of the Thermal Noise of MOS Transistors under Analog and RF Operating Conditions Ralf Brederlow 1, Georg Wenig 2, and Roland Thewes 1 1 Infineon Technologies, Corporate Research, 2 Technical
More informationTopic 4. The CMOS Inverter
Topic 4 The CMOS Inverter Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk Topic 4-1 Noise in Digital Integrated
More informationEKV MOS Transistor Modelling & RF Application
HP-RF MOS Modelling Workshop, Munich, February 15-16, 1999 EKV MOS Transistor Modelling & RF Application Matthias Bucher, Wladek Grabinski Electronics Laboratory (LEG) Swiss Federal Institute of Technology,
More informationECE 546 Lecture 10 MOS Transistors
ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 17: March 23, 2017 Energy and Power Optimization, Design Space Exploration, Synchronous MOS Logic Lecture Outline! Energy and Power Optimization
More informationEE141Microelettronica. CMOS Logic
Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit
More informationTHE INVERTER. Inverter
THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)
More informationChoice of V t and Gate Doping Type
Choice of V t and Gate Doping Type To make circuit design easier, it is routine to set V t at a small positive value, e.g., 0.4 V, so that, at V g = 0, the transistor does not have an inversion layer and
More informationEECS 427 Lecture 11: Power and Energy Reading: EECS 427 F09 Lecture Reminders
EECS 47 Lecture 11: Power and Energy Reading: 5.55 [Adapted from Irwin and Narayanan] 1 Reminders CAD5 is due Wednesday 10/8 You can submit it by Thursday 10/9 at noon Lecture on 11/ will be taught by
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 15: March 15, 2018 Euler Paths, Energy Basics and Optimization Midterm! Midterm " Mean: 89.7 " Standard Dev: 8.12 2 Lecture Outline! Euler
More informationELEC516 Digital VLSI System Design and Design Automation (spring, 2010) Assignment 4 Reference solution
ELEC516 Digital VLSI System Design and Design Automation (spring, 010) Assignment 4 Reference solution 1) Pulse-plate 1T DRAM cell a) Timing diagrams for nodes and Y when writing 0 and 1 Timing diagram
More informationDigital Integrated Circuits A Design Perspective
Semiconductor Memories Adapted from Chapter 12 of Digital Integrated Circuits A Design Perspective Jan M. Rabaey et al. Copyright 2003 Prentice Hall/Pearson Outline Memory Classification Memory Architectures
More informationThe Physical Structure (NMOS)
The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1 Transistor Resistance Two
More informationCMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor
CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1
More informationBSIM-CMG Model. Berkeley Common-Gate Multi-Gate MOSFET Model
BSIM-CMG Model Why BSIM-CMG Model When we reach the end of the technology roadmap for the classical CMOS, multigate (MG) CMOS structures will likely take up the baton. Numerous efforts are underway to
More informationMidterm. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. Pass Transistor Logic. Restore Output.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 21, 2017 Transmission Gates, Euler Paths, Energy Basics Review Midterm! Midterm " Mean: 79.5 " Standard Dev: 14.5 2 Lecture Outline!
More informationSEMICONDUCTOR MEMORIES
SEMICONDUCTOR MEMORIES Semiconductor Memory Classification RWM NVRWM ROM Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable (PROM) SRAM FIFO FLASH DRAM LIFO Shift Register CAM
More informationSemiconductor Memories
!"#"$%&'()$*#+%$*,' -"+./"$0 1'!*0"#)'2*+03*.$"4* Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Semiconductor Memories December 20, 2002 !"#$%&'()*&'*+&, Memory Classification Memory Architectures
More informationESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals
University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 2016 Final Friday, May 6 5 Problems with point weightings shown.
More informationMOSFET: Introduction
E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major
More informationFig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)
1 Introduction to Transistor-Level Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed
More informationS-1000 Series ULTRA-SMALL PACKAGE HIGH-PRECISION VOLTAGE DETECTOR. Features. Applications. Packages. Seiko Instruments Inc. 1.
S-1000 Series www.sii-ic.com ULTRA-SMALL PACKAGE HIGH-PRECISION VOLTAGE DETECTOR Seiko Instruments Inc., 2004-2015 Rev.3.1_00 The S-1000 series is a series of high-precision voltage detectors developed
More informationCMOS Inverter (static view)
Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:
More informationEnhancing the Performance of Organic Thin-Film Transistor using a Buffer Layer
Proceedings of the 9th International Conference on Properties and Applications of Dielectric Materials July 19-23, 29, Harbin, China L-7 Enhancing the Performance of Organic Thin-Film Transistor using
More informationToday s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model
- Spring 003 Lecture 4 Design Rules CMOS Inverter MOS Transistor Model Today s lecture Design Rules The CMOS inverter at a glance An MOS transistor model for manual analysis Important! Labs start next
More informationUniversity of Toronto. Final Exam
University of Toronto Final Exam Date - Apr 18, 011 Duration:.5 hrs ECE334 Digital Electronics Lecturer - D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last
More informationLecture 11: MOSFET Modeling
Digital Integrated Circuits (83-313) Lecture 11: MOSFET ing Semester B, 2016-17 Lecturer: Dr. Adam Teman TAs: Itamar Levi, Robert Giterman 18 June 2017 Disclaimer: This course was prepared, in its entirety,
More informationMASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences
MSSCHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences nalysis and Design of Digital Integrated Circuits (6.374) - Fall 2003 Quiz #1 Prof. nantha Chandrakasan Student
More informationEEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #2: MOSFET Structure and Basic Operation Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 1 this week, report due next week Bring
More informationWhere Does Power Go in CMOS?
Power Dissipation Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit Path between Supply Rails during Switching Leakage Leaking
More informationCHAPTER 3: TRANSISTOR MOSFET DR. PHAM NGUYEN THANH LOAN. Hà Nội, 9/24/2012
1 CHAPTER 3: TRANSISTOR MOSFET DR. PHAM NGUYEN THANH LOAN Hà Nội, 9/24/2012 Chapter 3: MOSFET 2 Introduction Classifications JFET D-FET (Depletion MOS) MOSFET (Enhancement E-FET) DC biasing Small signal
More informationECE 497 JS Lecture - 12 Device Technologies
ECE 497 JS Lecture - 12 Device Technologies Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 NMOS Transistor 2 ρ Source channel charge density
More information04. What is the Mod number of the counter circuit shown below? Assume initially reset.
. Which of the following is the state diagram for the Meale machine shown below. 4. What is the Mod number of the counter circuit shown below? Assume initiall reset. input CLK D output D D a. b. / / /
More informationLecture 310 Open-Loop Comparators (3/28/10) Page 310-1
Lecture 310 Open-Loop Comparators (3/28/10) Page 310-1 LECTURE 310 OPEN-LOOP COMPARATORS LECTURE ORGANIZATION Outline Characterization of comparators Dominant pole, open-loop comparators Two-pole, open-loop
More informationHN58C256 Series word 8-bit Electrically Erasable and Programmable CMOS ROM
32768-word 8-bit Electrically Erasable and Programmable CMOS ROM ADE-203-092G (Z) Rev. 7.0 Nov. 29, 1994 Description The Hitachi HN58C256 is a electrically erasable and programmable ROM organized as 32768-word
More informationRFIC2017 MO2B-2. A Simplified CMOS FET Model using Surface Potential Equations For Inter-modulation Simulations of Passive-Mixer-Like Circuits
A Simplified CMOS FET Model using Surface Potential Equations For Inter-modulation Simulations of Passive-Mixer-Like Circuits M. Baraani Dastjerdi and H. Krishnaswamy CoSMIC Lab, Columbia University, New
More informationEE247 Lecture 16. Serial Charge Redistribution DAC
EE47 Lecture 16 D/A Converters D/A examples Serial charge redistribution DAC Practical aspects of current-switch DACs Segmented current-switch DACs DAC self calibration techniques Current copiers Dynamic
More informationP-channel enhancement mode MOS transistor
FEATURES SYMBOL QUICK REFERENCE DATA Very low threshold voltage s V DS = 2 V Fast switching Logic level compatible I D =.2 A Subminiature surface mount g package R DS(ON). Ω (V GS =. V) GENERAL DESCRIPTION
More informationESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals
University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 017 Final Wednesday, May 3 4 Problems with point weightings shown.
More informationTopics. Dynamic CMOS Sequential Design Memory and Control. John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut
Topics Dynamic CMOS Sequential Design Memory and Control Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance
More informationCOMP 103. Lecture 16. Dynamic Logic
COMP 03 Lecture 6 Dynamic Logic Reading: 6.3, 6.4 [ll lecture notes are adapted from Mary Jane Irwin, Penn State, which were adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] COMP03
More informationDATASHEET CD4093BMS. Features. Pinout. Functional Diagram. Applications. Description. CMOS Quad 2-Input NAND Schmitt Triggers
DATASHEET CD9BMS CMOS Quad -Input NAND Schmitt Triggers FN Rev. December 199 Features High Voltage Types (V Rating) Schmitt Trigger Action on Each Input With No External Components Hysteresis Voltage Typically.9V
More informationEE 330 Lecture 37. Digital Circuits. Other Logic Families. Propagation Delay basic characterization Device Sizing (Inverter and multiple-input gates)
EE 330 Lecture 37 Digital Circuits Other Logic Families Static Power Dissipation Propagation Delay basic characterization Device Sizing (Inverter and multiple-input gates) Review from Last Time Inverter
More informationMOS Transistor Theory
MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors
More informationLecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:
Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I- curve (Square-Law Model)
More informationEE241 - Spring 2000 Advanced Digital Integrated Circuits. Announcements
EE241 - Spring 2 Advanced Digital Integrated Circuits Lecture 11 Low Power-Low Energy Circuit Design Announcements Homework #2 due Friday, 3/3 by 5pm Midterm project reports due in two weeks - 3/7 by 5pm
More informationMicroelectronics Main CMOS design rules & basic circuits
GBM8320 Dispositifs médicaux intelligents Microelectronics Main CMOS design rules & basic circuits Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim mohamad.sawan@polymtl.ca M5418 6 & 7 September
More informationElectronics with 2D Crystals: Scaling extender, or harbinger of new functions?
Electronics with 2D Crystals: Scaling extender, or harbinger of new functions? 1 st Workshop on Data Abundant Systems Technology Stanford, April 2014 Debdeep Jena (djena@nd.edu) Electrical Engineering,
More informationSemiconductor Memories
Introduction Classification of Memory Devices "Combinational Logic" Read Write Memories Non Volatile RWM Read Only Memory Random Access Non-Random Access Static RAM FIFO Dynamic RAM LIFO Shift Register
More informationFree-standing Organic Transistors and Circuits. with Sub-micron thickness
Supplementary Information Free-standing Organic Transistors and Circuits with Sub-micron thickness Kenjiro Fukuda 1,2,3,4 (*), Tomohito Sekine 1, Rei Shiwaku 1, Takuya Morimoto 5, Daisuke Kumaki 1, and
More informationSample Test Paper - I
Scheme G Sample Test Paper - I Course Name : Computer Engineering Group Marks : 25 Hours: 1 Hrs. Q.1) Attempt any THREE: 09 Marks a) Define i) Propagation delay ii) Fan-in iii) Fan-out b) Convert the following:
More informationGMU, ECE 680 Physical VLSI Design 1
ECE680: Physical VLSI Design Chapter VIII Semiconductor Memory (chapter 12 in textbook) 1 Chapter Overview Memory Classification Memory Architectures The Memory Core Periphery Reliability Case Studies
More informationEE115C Digital Electronic Circuits Homework #4
EE115 Digital Electronic ircuits Homework #4 Problem 1 Power Dissipation Solution Vdd =1.0V onsider the source follower circuit used to drive a load L =20fF shown above. M1 and M2 are both NMOS transistors
More information9-Channel 64steps Constant-Current LED Driver with SPI Control. Features
BCT3119 with SPI Control General Description The BCT3119 is a constant current driver incorporating shift register and data latch. This CMOS device is designed for LED display applications. The max output
More informationDesign of Analog Integrated Circuits
Design of Analog Integrated Circuits Chapter 11: Introduction to Switched- Capacitor Circuits Textbook Chapter 13 13.1 General Considerations 13.2 Sampling Switches 13.3 Switched-Capacitor Amplifiers 13.4
More informationa-igzo TFT Simulation
Engineered Excellence A Journal for Process and Device Engineers a-igzo TFT Simulation 1. Introduction The flat panel device for active matrix liquid crystal displays (AMLCDs and active matrix organic
More informationLOGIC CIRCUITS. Basic Experiment and Design of Electronics. Ho Kyung Kim, Ph.D.
Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Digital IC packages TTL (transistor-transistor
More informationMicroelectronics Part 1: Main CMOS circuits design rules
GBM8320 Dispositifs Médicaux telligents Microelectronics Part 1: Main CMOS circuits design rules Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim! http://www.cours.polymtl.ca/gbm8320/! med-amine.miled@polymtl.ca!
More informationLECTURE 380 TWO-STAGE OPEN-LOOP COMPARATORS - II (READING: AH ) Trip Point of an Inverter
Lecture 380 Two-Stage Open-Loop Comparators-II (4/5/02) Page 380-1 LECTURE 380 TWO-STAGE OPEN-LOOP COMPARATORS - II (READING: AH 445-461) Trip Point of an Inverter V DD In order to determine the propagation
More informationThe transistor is not in the cutoff region. the transistor is in the saturation region. To see this, recognize that in a long-channel transistor ifv
ECE 440 Spring 005 Page 1 Homework Assignment No. Solutions P.4 For each transistor, first determine if the transistor is in cutoff by checking to see if GS is less than or greater than. may have to be
More informationINTEGRATED CIRCUITS. For a complete data sheet, please also download:
INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC0 74C/CT/CU/CMOS ogic Family Specifications The IC0 74C/CT/CU/CMOS ogic Package Information The IC0 74C/CT/CU/CMOS ogic
More informationMM74C922 MM74C Key Encoder 20-Key Encoder
MM74C922 MM74C923 16-Key Encoder 20-Key Encoder General Description The MM74C922 and MM74C923 CMOS key encoders provide all the necessary logic to fully encode an array of SPST switches. The keyboard scan
More informationEECS 141: FALL 05 MIDTERM 1
University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 11-1:3 Thursday, October 6, 6:3-8:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION
More informationPreparation of Examination Questions and Exercises: Solutions
Questions Preparation of Examination Questions and Exercises: Solutions. -bit Subtraction: DIF = B - BI B BI BO DIF 2 DIF: B BI 4 6 BI 5 BO: BI BI 4 5 7 3 2 6 7 3 B B B B B DIF = B BI ; B = ( B) BI ( B),
More informationDATASHEET CD40109BMS. Features. Description. Applications. Functional Diagram. Pinout. CMOS Quad Low-to-High Voltage Level Shifter
DATASHEET CD19BMS CMOS Quad Low-to-High Voltage Level Shifter Features High Voltage Type (V Rating) Independence of Power Supply Sequence Considerations - can Exceed - Input Signals can Exceed Both and
More information1/13/12 V DS. I d V GS. C ox ( = f (V GS ,V DS ,V SB = I D. + i d + I ΔV + I ΔV BS V BS. 19 January 2012
/3/ 9 January 0 Study the linear model of MOS transistor around an operating point." MOS in saturation: V GS >V th and V S >V GS -V th " VGS vi - I d = I i d VS I d = µ n ( L V V γ Φ V Φ GS th0 F SB F
More informationName: Answers. Mean: 83, Standard Deviation: 12 Q1 Q2 Q3 Q4 Q5 Q6 Total. ESE370 Fall 2015
University of Pennsylvania Department of Electrical and System Engineering Circuit-Level Modeling, Design, and Optimization for Digital Systems ESE370, Fall 2015 Final Tuesday, December 15 Problem weightings
More informationEEC 116 Lecture #3: CMOS Inverters MOS Scaling. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 116 Lecture #3: CMOS Inverters MOS Scaling Rajeevan Amirtharajah University of California, Davis Jeff Parhurst Intel Corporation Outline Review: Inverter Transfer Characteristics Lecture 3: Noise Margins,
More informationAmplifiers, Source followers & Cascodes
Amplifiers, Source followers & Cascodes Willy Sansen KULeuven, ESAT-MICAS Leuven, Belgium willy.sansen@esat.kuleuven.be Willy Sansen 0-05 02 Operational amplifier Differential pair v- : B v + Current mirror
More information1. (50 points, BJT curves & equivalent) For the 2N3904 =(npn) and the 2N3906 =(pnp)
HW 3 1. (50 points, BJT curves & equivalent) For the 2N3904 =(npn) and the 2N3906 =(pnp) a) Obtain in Spice the transistor curves given on the course web page except do in separate plots, one for the npn
More informationS No. Questions Bloom s Taxonomy Level UNIT-I
GROUP-A (SHORT ANSWER QUESTIONS) S No. Questions Bloom s UNIT-I 1 Define oxidation & Classify different types of oxidation Remember 1 2 Explain about Ion implantation Understand 1 3 Describe lithography
More informationCombinatorial and Sequential CMOS Circuits Dr. Lynn Fuller Webpage:
ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Combinatorial and Sequential CMOS Circuits Webpage: http://people.rit.edu/lffeee 82 Lomb Memorial Drive Rochester, NY 14623-5604 Tel (585)
More informationCPE100: Digital Logic Design I
Professor Brendan Morris, SEB 3216, brendan.morris@unlv.edu CPE100: Digital Logic Design I Midterm01 Review http://www.ee.unlv.edu/~b1morris/cpe100/ 2 Logistics Thursday Oct. 5 th In normal lecture (13:00-14:15)
More informationUNIVERSITY OF BOLTON SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER /2017
UNIVERSITY OF BOLTON TW35 SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER 2-2016/2017 INTERMEDIATE DIGITAL ELECTRONICS AND COMMUNICATIONS MODULE NO: EEE5002
More informationIntroduction to Reliability Simulation with EKV Device Model
Introduction to Reliability Simulation with Device Model Benoît Mongellaz Laboratoire IXL ENSEIRB - Université Bordeaux 1 - UMR CNRS 5818 Workshop november 4-5th, Lausanne 1 Motivation & Goal Introduced
More informationTransfer Gate and Dynamic Logic Dr. Lynn Fuller Webpage:
ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Transfer Gate and Dynamic Logic Dr. Lynn Fuller Webpage: http://people.rit.edu/lffeee 82 Lomb Memorial Drive Rochester, NY 14623-5604 Tel (585)
More informationLecture 5: CMOS Transistor Theory
Lecture 5: CMOS Transistor Theory Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline q q q q q q q Introduction MOS Capacitor nmos I-V Characteristics
More informationSelf-heat Modeling of Multi-finger n-mosfets for RF-CMOS Applications
Self-heat Modeling of Multi-finger n-mosfets for RF-CMOS Applications Hitoshi Aoki and Haruo Kobayashi Faculty of Science and Technology, Gunma University (RMO2D-3) Outline Research Background Purposes
More informationThe Devices: MOS Transistors
The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, Addison-Wesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall NMOS Transistor
More informationSimple and accurate modeling of the 3D structural variations in FinFETs
Simple and accurate modeling of the 3D structural variations in FinFETs Donghu Kim Electrical Engineering Program Graduate school of UNIST 2013 Simple and accurate modeling of the 3D structural variations
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 18: March 27, 2018 Dynamic Logic, Charge Injection Lecture Outline! Sequential MOS Logic " D-Latch " Timing Constraints! Dynamic Logic " Domino
More informationSwitching circuits: basics and switching speed
ECE137B notes; copyright 2018 Switching circuits: basics and switching speed Mark Rodwell, University of California, Santa Barbara Amplifiers vs. switching circuits Some transistor circuit might have V
More information