Introduction to Switched Capacitor Circuits

Transcription

1 Microprocessor Laboratory Asian ourse on Advanced LSI Design Techniques usg a Hardware Description Language Manila, The Philippes 25 November 13 December 2002 Introduction to Switched apacitor ircuits Giovanni Anelli ERN - European Organization for Nuclear Research Experimental Physics Division Microelectronics Group H-1211 Geneva 23 Switzerland Giovanni.Anelli@cern.ch

2 Outle Introduction The basic idea behd Switched-apacitor ircuits apacitors and Switches MOS processes 2 circuit examples Low-voltage Switched-apacitor ircuits design onclusions Giovanni Anelli, ERN 2

3 Outle Introduction ¾ Sampled-data analog system ¾ Why Switched-apacitor ircuits? The basic idea behd Switched-apacitor ircuits apacitors and Switches MOS processes 2 circuit examples Low-voltage Switched-apacitor ircuits design onclusions Giovanni Anelli, ERN 3

4 Analog and digital systems ANALOG The signals (represented by voltages, currents, charges) are contuous functions of the contuous time variable. Both dependent and dependent variables are contuous. Examples: amplifiers, passive or active R filters. DIGITAL Each signal is represented by a sequence of numbers (bits a bary system). The signals can have only discrete values, taken at discrete time stances. Both dependent and dep. variables are discrete. Example: microprocessors. S(t) S(nT) T t nt Giovanni Anelli, ERN 4

5 Sampled-data analog systems As the analog systems, the signals (dependent variable) can take any value with a given range. However, the signal amplitude is sampled only at discrete time stances, as digital systems. Therefore, sampled-data analog systems as well as digital systems need a clock. S(nT) T S(nT) = S(t) t=nt, n=0,1,2 nt S sh (t) T t S sh (t) = S(nT), nt <= t < (n+1)t Sampled and held signal Giovanni Anelli, ERN 5

6 Why Switched apacitor ircuits? Switched-apacitor (S) circuits where troduced, at the begng, maly to make tegrated filters Historically, filters were first realized as passive circuits, with resistors (R), capacitors () and ductors (L) Sce ductors (L) have several drawbacks, people started to design active-r filters (still hybrid construction), which use operational amplifiers, resistors and capacitors. The next step was to make fully tegrated filters, but monolithic active-r filters are sometimes difficult to make, maly because of area and accuracy constrats. This led to the vention of S filters: we are gog to see why the followg. Today, the switched-capacitor prciple is used not only for tegrated filters, but also for ADs, DAs, programmable ga amplification and non lear circuits (multipliers, modulators, ). R. Gregorian and G.. Temes, Analog MOS Integrated ircuits for Signal Processg, J. Wiley & Sons, Giovanni Anelli, ERN 6

7 Why MOS technology? Availability of good switches ¾ No voltage offset ¾ Low off-state leakage ¾ Good on-state conductance Availability of high-quality capacitors ¾ Precise ratios ¾ Learity ¾ Low temperature coefficient Possibility to store a charge on a node for a long time (up to 1 second) due to the low leakage Possibility to sense a charge nondestructively and contuously (due to the high gate impedance) Switched-capacitor circuits can be built any digital MOS process, and can therefore be tegrated together with complex digital functions v ck v out H. Yoshizawa et al., "MOSFET-Only Switched-apacitor ircuits Digital MOS Technology", IEEE JSS, vol. 34, no. 6, June 1999, pp Giovanni Anelli, ERN 7

8 Inductors drawbacks Inductors are generally very lossy For low frequencies, large ductors are needed Inductors radiate and pick up electromagnetic disturbances Inductors can not be scaled without decreasg the quality factor L R ZL Q L R Inductors are also very difficult to tegrate, and this is one of the major problems of today s RF tegrated circuits T. H. Lee, The Design of MOS Radio-Frequency Integrated ircuits, ambridge University Press, Giovanni Anelli, ERN 8

9 Difficulties scalg ductors If we reduce all the dimensions by a factor x >1 l d 2 d L P n F( ) d l lw nsd R U U A A L x R x L x R x A ZL Q L R Q Lx ZL R x x Q x L 2 l d = 2r Sr 2 L P n 2 S r l 2 G.. Temes and J. W. LaPatra, Introduction to ircuit Synthesis and Design, McGraw-Hill, Giovanni Anelli, ERN 9

10 Integrated Active-R filters There are several difficulties when makg monolithic active-r filters: ¾ Limited capacitance per unit area (around 1 ff/pm 2 ) ¾ Limited resistance per unit area ( :/sq.) ¾ Poor resistance and capacitance absolute value accuracy (10-20 %) For example, if we need an R of 10-4 (voice band application), we would need a 10 pf capacitor (100 Pm by 100 Pm) and a 10 M: resistor (1000 Pm by 1000 Pm if each square is 3 Pm by 3 Pm ). The error on the R time constant will be > 20 %, sce the errors R and are not correlated. Temperature and agg coefficients of capacitors and resistors do not track. This creases even more the already poorly controlled R constant spread. For many applications the accuracy that can be obtaed with tegrated active R filters is not good enough. Giovanni Anelli, ERN 10

11 Outle Introduction The basic idea behd Switched-apacitor ircuits ¾ How to replace a resistor with a capacitor and two switches ¾ The orig of this idea (and of its application) apacitors and Switches MOS processes 2 circuit examples Low-voltage Switched-apacitor ircuits design onclusions Giovanni Anelli, ERN 11

12 Resistor emulation I1 I2 1 2 v 1 v S1 S2 2 'q 1 'q 2 v1 and v2 are supposed to be slow varyg signals (compared to T) Each clock cycle T, a charge 'q goes from 1 to 2, where ' q ' q1 ' q2 (v1 v2) I2 I1 T T/2 t t The average current flowg from 1 to 2 is i (v1 v2) T, S1 and S2 emulate therefore a resistor R T Giovanni Anelli, ERN 12

13 Resistor emulation (2) I2 I1 S2 1 2 v 1 'q S1 'q v T T/2 R T I2 I1 t R T f t Giovanni Anelli, ERN 13

14 The origs! The idea that the dc behavior of a capacitor with periodically terchanged termals is the same as that of a resistor was already present a book first published 1873!!! James lerk Maxwell, A Treatise on Electricity & Magnetism, Dover Publications, 1954, Second volume, pp Giovanni Anelli, ERN 14

15 The origs! Giovanni Anelli, ERN 15

16 And the first application D. L. Fried, Analog Sample-Data Filters, IEEE Journal of Solid-State ircuits, vol. 7, August 1972, pp Giovanni Anelli, ERN 16

17 Area and precision advantages Let s take aga the already discussed example: R = Suppose we use a clock frequency f c = 100 khz. 2 2 R f 1 From we obta 1 This means that stead of a 10 M: resistor ( Pm 2 ) we need a 1 pf capacitor. We ga a factor 1000 area! The ratio between tegrated capacitors can be very well controlled (down to the 0.1 %). The clock frequency is also a parameter which can be very precisely controlled. Giovanni Anelli, ERN 17

18 Outle Introduction The basic idea behd Switched-apacitor ircuits apacitors and Switches MOS processes ¾ apacitors ¾ NMOS, PMOS and MOS switches ¾ Non-idealities troduced by the switches 2 circuit examples Low-voltage Switched-apacitor ircuits design onclusions Giovanni Anelli, ERN 18

19 apacitors MOS There are several possibilities of buildg a capacitor a MOS process: 1. Metal (or Poly) over diffusion 2. Metal (or Poly) over Poly 3. Metal over metal The structure Poly over diffusion is present ANY process The matchg between two capacitors on the same tegrated circuit can be very good. For two identical capacitors, we have that ' A B WL 2 S where WL is the capacitor area, S it the distance between their centers and A, B and are constants characteristic of a given technology Example: two 1 pf capacitors and S = 100 Pm. Supposg A = 3 %, B = 1.8 Pm 2 and = 10-4 Pm -1, we obta '/ = 0.4% Giovanni Anelli, ERN 19

20 NMOS switch An NMOS transistor can be used as a switch. When the switch is on the transistor works the lear region. nds IDS E (GS T ) DS 2 The conductance of the switch is given by G wi w DS DS E n P The switch is on when gate = DD, it is off when gate = 0. GS TN DS N ox W L GS TN DD out Plot of the on conductance G G P N ox W L Here the switch is off even if the gate = DD DD DD - TN DD TN < DD - TN Giovanni Anelli, ERN 20

21 PMOS switch Similar considerations hold for a PMOS transistor. Remember that for a PMOS transistor the threshold voltage is negative. In the followg, TP is the absolute value of the threshold voltage. The conductance of the switch is given by: P ox GS The switch is off when gate = DD, it is on when gate = 0. G P W L TP 0 Plot of the on conductance G G P Here the switch is off even if the gate = 0 P ox W L TP > TP out TP DD Giovanni Anelli, ERN 21

22 MOS switch onnectg two transistors (one NMOS and one PMOS) parallel we obta a switch with an improved conductance from 0 to DD. The switch is on when: clk = DD and clkb = 0 G G N P P P N P ox ox W L W L ¹ ¹ N P DD TP TN G G = G N if < TP G N + G P if TP < < DD - TN G P if DD - TN < < DD clk NMOS PMOS out clkb TP DD - TN DD Giovanni Anelli, ERN 22

23 hannel harge jection When a switch is turned off the charge Q ch which constitutes the version layer exits through the source and dra termals. It is difficult to determe which fraction of charge will go on the samplg capacitor H. For a worst-case calculation, we will assume that all the charge goes on H. DD Q ch WL ox DD T clk 0 out WL ox DD H T H out out 1 WL H ox ¹ WL H ox DD T harge jection troduces therefore a ga and an offset error. Giovanni Anelli, ERN 23

24 hannel harge jection In the previous slide, we did not take to account the bulk effect! If we do, we see that charge jection also gives non learity errors. T T0 J sb I Si I Si J 2qH Si ox N a out 1 WL H ox ¹ J WL H ox I Si WL H ox DD T0 J I Si The non learity comes from the dependence of T upon IN. From this formula we see that to mimize the effect of the charge jection we should make the switch as small as possible. B. J. Sheu and. Hu, "Switch-Induced Error oltage on a Switched apacitor", IEEE JSS, vol. 19, no. 4, August 1984, pp J. B. Kuo et al., "MOS Pass Transistor Turn-Off Transient Analysis", IEEE TED, vol. 33, no. 10, October 1986, pp J.-H. Shieh et al., "Measurement and Analysis of harge Injection MOS Analog Switches", IEEE JSS, vol. 22, no. 2, April 1987, pp G. Wegmann et al., "harge Injection Analog MOS Switches", IEEE Journal of Solid-State ircuits, vol. 22, no. 6, Dec. 1987, pp Giovanni Anelli, ERN 24

25 Speed-precision trade-off To be less sensitive to charge jection we can: ¾ make the samplg capacitor bigger ¾ make the switch smaller ( area) Both these solutions crease the R constant of the circuit, makg it slower. To evaluate the speed-precision trade-off, we calculate the product W ', where W= R represents the verse of the speed and ' the error. We obta: W R on H P ox W L DD H T W ' ' WL ox DD It is terestg to note that this product does not depend on the switch width nor on the samplg capacitor, and that it improves (becomes smaller) with scalg! 2 L P H T Giovanni Anelli, ERN 25

26 lock Feedthrough The overlap capacitances between gate and source or dra couple the clock transition to the samplg capacitance when the switch is switched off. This also troduce an error, which is proportional to the width W of the transistor. DD ov 0 ov out DD Wov W ov H out H The clock feedthrough troduces an offset error. Giovanni Anelli, ERN 26

27 harge jection cancellation To reduce the charge jection problem we can use dummy switches. DD clk 0 0 clkb DD If we assume that half of the charge the switch channel goes towards the samplg capacitor, then H out 1 W dummy W switch 2 The assumption we made is not exact, and therefore this method is not perfect. On the other hand, it is terestg to note that dummies elimate the clock feedthrough problem (with the sizg of the transistors dicated). Giovanni Anelli, ERN 27

28 harge jection cancellation Another (not much more effective) technique is to use MOS switches. DD clk 0 Q N W L N N ox DD TN Q N out clkb Q P DD H Q P W L P P ox TP 0 In this case, perfect cancellation is provided only for one put level. This technique is not perfect for clock feedthrough either, sce the overlap capacitances for NMOS and PMOS are slightly different. Giovanni Anelli, ERN 28

29 harge jection cancellation The third possibility to fight charge jection is to use differential operation H + out+ Q + DD 0 clk Q Q WL ox out out out Q H out Q H Q Q > J I Si Si H - Q - out- H This technique removes the constant offset and reduce the nonlear component. It is also effective for the clock feedthrough. Giovanni Anelli, ERN 29

30 Other non-idealities There are several other thgs which can create problems S circuits: Switches junction leakage Parasitic capacitances of the samplg capacitor and of the switches Timg differences between clk and clkb MOS switches Op-amp D offset voltage Op-amp fite D ga Op-amp fite bandwidth Op-amp fite slew rate Op-amp nonzero output resistance Noise switches and op-amps Noise jection from power, ground and clock les and from the substrate Giovanni Anelli, ERN 30

31 Outle Introduction The basic idea behd Switched-apacitor ircuits apacitors and Switches MOS processes 2 circuit examples ¾ S tegrator ¾ Non-filterg applications of S ircuits ¾ Multiply-by-two circuit Low-voltage Switched-apacitor ircuits design onclusions Giovanni Anelli, ERN 31

32 Active R tegrator R.G. _ + out Integrators are very useful analog blocks, extensively used filters and oversampled Analog-to-Digital onverters. If the ga of the operational amplifier is very high (an therefore the negative put behaves as a virtual ground, we can write: H(s) out (s) (s) 1 sr out (t) 1 R ³ (t) dt Giovanni Anelli, ERN 32

33 Switched-capacitor tegrator Substitutg the resistor with its switched-capacitor equivalent we obta: I1 I2 S1 S2.G. _ + out I 1, I 2 T T/2 I 1 I 2 I 1 I 2 I 1 I 2 I 1 I 2 t Giovanni Anelli, ERN 33

34 Non idealities effects I1 I2 S1 H j S2.G. _ + out This implementation of a S tegrator suffers from two important effects: The put-dependent charge jection from S1 The voltage dependent parasitic (stray) capacitances of the diffusions of the two switches S1 and S2 give orig to nonlearities. Giovanni Anelli, ERN 34

35 Stray-sensitive S tegrator 2 S 1 S 2 1 S 3 S4.G. - + out SAMPLING MODE INTEGRATION MODE out + out Giovanni Anelli, ERN 35

36 Stray-sensitive S tegrator 2 S 1 A S 2 1 B S 3 S4.G. - + out The stray the nodes A, B and.g. do not count anymore because: A (Node A) is constantly switched between and ground. B (Node B) is grounded at both termals. (Node ) is grounded at both termals. In the transition from samplg mode to tegration mode S3 turns off first, and its charge jection troduces a constant offset. S1 turns off after S3, so that its charge jection does not count. Giovanni Anelli, ERN 36

37 S filters disadvantages S filters must be preceded by an Anti-Aliasg filter and followed by a Smoothg Filter. This complicates the overall system and crease the power consumption. The accuracy is limited to about 0.1 %. This is only 10-bit. For some applications, higher accuracies are needed. The dynamic range (which is basically the maximum SNR) is rarely more than (100 db). This is due to the various sources of noise comg from the amplifiers, the switches and the substrate. Digital filters are more easily programmable and more flexible. Sampled signals systems can not be analyzed with Laplace or Fourier transformations. They need a special mathematical tool, called z-transformation. We will not have the time to see it here S filters are tegrated circuits. The economical advantage is there only for great numbers! Development cost + I_cost * N < Hybrid_circuit_cost*N Giovanni Anelli, ERN 37

38 Non filterg application of S A part from filterg purposes, switched-capacitor circuits are widely used many other analog signal processg applications: oltage amplifiers Analog-to-Digital onverters Digital-to-Analog onverters oltage comparators Modulators Rectifiers Peak detectors Oscillators Giovanni Anelli, ERN 38

39 Multiply-by-two circuit S 4 S 3 S 1 S 2.G. - + out S 5 SAMPLING MODE AMPLIFIATION MODE.G. - + out.g. - + out Giovanni Anelli, ERN 39

40 Multiply-by-two circuit Transition from samplg mode to accumulation mode. 1 S 3 2.G. - + out G. - + out 2.G. - + out = 2 Giovanni Anelli, ERN 40

41 Outle Introduction The basic idea behd Switched-apacitor ircuits apacitors and Switches MOS processes 2 circuit examples Low-voltage Switched-apacitor ircuits design ¾ The problem: MOS low DD ¾ Possible solutions onclusions Giovanni Anelli, ERN 41

42 MOS low DD The maximum voltage which can drive the gates of the switch is DD. If DD is not high enough (at least > TN + TP ), we can have a hole the conduction curve of the switch. clk out clkb G DD = 5 G NMOS PMOS DD = 1 TP DD DD - TN TP DD DD - TN Giovanni Anelli, ERN 42

43 Measured switch on resistance Switch Resistance [ k : ] dd = 2.5 dd = 1.5 dd = [ ] MOS switch made a 0.25 Pm process. The NMOS and the PMOS transistors have the same size. The three measurements are three different DD Giovanni Anelli, ERN 43

44 Low-voltage S ircuits The problem of the switches is seen at the circuit level. If we take, as an example, the stray sensitive S tegrator shown below, we see that the switches S1 and S5 are not capable to transmit the signal as desired. These switches are called floatg switches. All the other switches are connected to ground (or virtual ground), so they do not give problems. 2 S 1 S 2 1 S 3 S4.G. - + S 5 out M. Kesk et al., A 1-10-MHz lock-rate 13-Bit MOS '6 Modulator Usg Unity-Ga-Reset Opamps, IEEE JSS, vol. 37, no. 7, 2002, p J. rols and M. Steyaert, Switched-Opamp: An Approach to realize Full MOS Switched-apacitor ircuits at ery Low Power Supply oltages, IEEE Journal of Solid-State ircuits, vol. 29, no. 8, August 1994, p J.-T. Wu and K.-L. hang MOS harge Pumps for Low-oltage Operation, IEEE JSS, vol. 33, no. 4, April 1998, p Giovanni Anelli, ERN 44

45 Switched op-amp technique The switched op-amp technique replaces the floatg switches with operational amplifiers, which are switched on and off. When the op-amp is off, its output is grounded S 2 1 S 3 S4 - + out S 1 S 5 This technique solve the problem but limits the maximum speed of the circuit because of the time required for the powerup / powerdown of the op-amps. Moreover, it requires the design of special low-voltage op-amps Giovanni Anelli, ERN 45

46 Other solutions Other possible solutions are: Low-threshold voltage devices. This solve the problem of the high R on of the switches the middle of the dynamic range, but it troduces other problems due to the high leakage currents when the switch is off. This can lead to unacceptable charge losses. Moreover, low-threshold voltage devices are not always available or imply an additional cost. harge-pump circuits. These circuits allow multiplyg on chip a low voltage. The multiplied voltage can then be used to drive the switches. Besides the fact that charge-pump circuits require chip area and power, the ma drawback of this techniques is that for some signals the gate oxide can undergo an important stress. This can have a severe impact on the reliability of the circuit. Reset op-amp technique. It is similar to the switched op-amp technique, sce it uses op-amps to replace the floatg switches. In this case, the op-amps are always on, and therefore this technique allows a faster operation of the circuits. Giovanni Anelli, ERN 46

47 Outle Introduction The basic idea behd Switched-apacitor ircuits apacitors and Switches MOS processes 2 circuit examples Low-voltage Switched-apacitor ircuits design onclusions Giovanni Anelli, ERN 47

48 onclusion Have you realized that we have made a gigantic tellectual step just six hours? We went from a sgle silicon atom to the design of simple tegrated circuits! giovanni.anelli@cern.ch Giovanni Anelli, ERN 48