Introduction to CMOS RF Integrated Circuits Design

Transcription

1 V. Voltage Controlled Oscillators Fall 2012, Prof. JianJun Zhou V-1

2 Outline Phase Noise and Spurs Ring VCO LC VCO Frequency Tuning (Varactor, SCA) Phase Noise Estimation Quadrature Phase Generator Fall 2012, Prof. JianJun Zhou V-2

3 VCO Phase Noise S block SNR f RF S desired f LO f IF IF RF L{ LO Fall 2012, Prof. JianJun Zhou V-3

4 Phase Noise Requirement SNR S S desired noise Sdesired [ Sblock L{ } 10log( fch)] L{ } Sdesired Sblock SNRmin 10log( fch) Ex: GSM Sdesired 102 db; Sblock 23 db@600khz SNRmin 9 db; fch 200KHz L{ } log(200 K) 141 dbc / Fall 2012, Prof. JianJun Zhou V-4

5 Spurious-Tone Performance S block SNR S desired RF f RF flo f IF IF S spur LO Fall 2012, Prof. JianJun Zhou V-5

6 Spurious-Tone Requirement SNR S S S spur S S ( S S S SNR Ex: GSM Sdesired 102dB; Sblock 23dB@600KHz SNRmin 9dB; S dBc spur desired desired desired noise block block spur ) min Fall 2012, Prof. JianJun Zhou V-6

7 Typical Figure of Merits for VCO Frequency ~ 1 5 GHz Tuning Range ~ % Phase Noise KHz Supply Voltage ~ 1.5 V Current < 10 ma Fall 2012, Prof. JianJun Zhou V-7

8 Oscillation Theory Y(s) X(s) H(s) 1 H(s)G(s) For steady oscillation, Barkhausen s criteria must be simultaneously met: H(s)G(s) H ( s) G( s) 2n 1 Fall 2012, Prof. JianJun Zhou V-8

9 Negative Resistance Model Z a s Z r s Equivalent Circuit GL GM During Oscillation: Re Z s Z s a Re 0 r Fall 2012, Prof. JianJun Zhou V-9

10 Negative Resistance Model V 1 A G m G o V 2 Y A GmZ in 1 G Z o in 1 1 G o Gmβ G o Z in Z 1 in Aβ β V 2 Z in Im Im 1 Determine the oscillation frequency Y 0 Aβ 0 Oscillation: Aβ 1 1 Re G o Z in Negative Conductance 1 Aβ 0 Fall 2012, Prof. JianJun Zhou V-10

11 Negative Resistance Model Z(jω) Z(j) f o 2 1 L C f 0 Fall 2012, Prof. JianJun Zhou V-11

12 Ring vs LC Oscillators Parameters Phase Noise Tuning Range Power Consumption Chip Area Output Waveform Ring VCO Poor Large High Small Square LC VCO Good Small Low Large Sinusoidal Fall 2012, Prof. JianJun Zhou V-12

13 Ring VCO A Cascade of Delay Cells Connected in Feedback to Meet Oscillation Criteria ( Barkhausen) Loop w osc > 1 Total Phase w osc = 2nπ For Single-Ended Design, Needs An Odd Number of Delay Cells to provide 2nπ phase shift f osc 1 2N d Fall 2012, Prof. JianJun Zhou V-13

14 Implementation of Ring Oscillator in out H( j f 0 N 0 ) ( ) osc GmR 1 j R C 1 2N d G m Gm Gm C0 R 0 C0 R0 C 0 R0 Fall 2012, Prof. JianJun Zhou V-14

15 Ring VCO Delay Cells Can Simply Be Digital or Analog Inverters Delay and Frequency Can Be Tuned By Bias Current, Device Transconductance, or Loading Resistance or Capacitance Can Provide Rail-To-Rail Output Waveform and Wide Tuning Range All Components Contribute Phase Noise Fall 2012, Prof. JianJun Zhou V-15

16 Delay Cells Fall 2012, Prof. JianJun Zhou V-16

17 Ring VCO Differential Design Signal is Increased by 6 db while Noise is Increased by 3 db => Phase Noise is Improved by 3 db Common-Mode Rejection (Supply, Even-Order Harmonics, Common-Mode, Substrate Noise) Double Power, Double Chip Area Fall 2012, Prof. JianJun Zhou V-17

18 LC VCO Single-Ended Design Use Feedback Principle for Oscillation: Loop w osc > 1 Total Phase w osc = 2nπ Critical to Include Impedance Transform: Not to Degrade Tank Q Improve Gain for Oscillation Either Capacitive or Inductive Divider Can Be Used for Impedance Transformation Fall 2012, Prof. JianJun Zhou V-18

19 LC VCO Single-Ended Design Feedback can be from drain to source or gate to source Impedance Transform Fall 2012, Prof. JianJun Zhou V-19

20 LC VCO Single-Ended Design L 1 f o 1 2 ( L L ) C 1 2 R L L 2 R L R s (1 L L 2 2 ) 1 Hartley Oscillator R s Fall 2012, Prof. JianJun Zhou V-20

21 LC VCO - Single-Ended Design f o 1 CC L C C ( ) 1 2 R L C 1 R L R s (1 C C 2 2 ) 1 R s C 2 Colpitts Oscillator Fall 2012, Prof. JianJun Zhou V-21

22 LC VCO Negative Resistance Design Make Use of LC Resonant Tank Use Negative-Gm Compensation Technique to Achieve Infinite Q for Oscillation L P C L P C Y L G P -G m Y eq G eq = 0 Fall 2012, Prof. JianJun Zhou V-22

23 Negative Resistance -G m M 1 M 2 I B Fall 2012, Prof. JianJun Zhou V-23

24 Negative Resistance i x V x i d2 M 1 M 2 I B i x V id 2 id1 x gs2 gs1 i x G m v x v g 2 At high-frequency the device capacitance and input resistance should be included in the analysis. m v x v Fall 2012, Prof. JianJun Zhou V-24

25 Differential VCO Fall 2012, Prof. JianJun Zhou V-25

26 Differential VCOs Fall 2012, Prof. JianJun Zhou V-26

27 LC VCO Frequency Tuning f osc 1 2 LC Frequency Tuning Can Be Achieved By Tuning Capacitance Using a Varactor or a Switchable Capacitor Array (SCA) Or Effective Inductance Fall 2012, Prof. JianJun Zhou V-27

28 PN-Junction Varactor n+ p+ n-well C T A C jo VB 1 F R S C T 1 QC R C S T Fall 2012, Prof. JianJun Zhou V-28

29 PN-Junction Varactor 1.5 Capacitance=img(Y11)/w (pf) Control Voltage (V) Fall 2012, Prof. JianJun Zhou V-29

30 PN-Junction Varactor Make Use of Depletion Capacitance of p-n Diode Junction n+ Contacts Are Used to Minimize Contact Resistance and thus to Maximize Q Reducing Size of p+ Would Minimize p+ Series Resistance Increasing Size of p+ Would Increase Number of Contacts and Reduce Contact Resistance Measurements Indicate Contact Resistance Dominates => Larger Size of p+ Diffusion is Desired for Higher Q Fall 2012, Prof. JianJun Zhou V-30

31 Accumulation-Mode Varactor n+ n- n- n+ n-well 1 C T 1 C ox 1 C dep R S C T 1 QC R C S T Fall 2012, Prof. JianJun Zhou V-31

32 Accumulation-Mode Varactor 1.4 Capacitance=img(Y11)/w (pf) Control Voltage (V) Fall 2012, Prof. JianJun Zhou V-32

33 Accumulation-Mode Varactor Similar to NMOS with N-Well Instead of P-Substrate n+ Are Used to Minimize Parasitic p-n Junction Capacitance to Maximize Tuning For Gate Voltage Larger Than Flat-Band Voltage V FB => Accumulate => C T = C ox For Smaller Gate Voltage, Depletion Capacitance C dep Exists Between Oxide and N-Well => 1/C T = 1/C ox + 1/C dep Compared to p-n Junction Capacitance, Advantages of Accumulation-Mode Capacitance Include [Soorapanth]: Better Average Q Larger Tuning Capacitance Fall 2012, Prof. JianJun Zhou V-33

34 Switchable-Capacitance Array C U C U C U M 1 C GD R ON C GD R ON Fall 2012, Prof. JianJun Zhou V-34

35 Larger Tuning Range Fall 2012, Prof. JianJun Zhou V-35

36 Switchable-Capacitance Array C U M 1 C off C on -C off C C on off C u C C C u u gd C 1 Q C R C on gd on Fall 2012, Prof. JianJun Zhou V-36

37 Switchable-Capacitance Array Wide Tuning Range Can Be Achieved By Increasing Number of Bits in the Array Large Switch => Small Turn-On Resistance => High Q Large Switch => Large Parasitic Capacitance => Small Tuning Range and Limited Operating Frequency Fall 2012, Prof. JianJun Zhou V-37

38 Phase Noise Estimation Power dbc Phase Noise f 3 (flicker FM) f 2 (random walk phase or white FM) f -1 (flicker phase) f 0 (white phase) 0 1Hz Freq Frequency L total Psideband 0 1, 10log Pcarrier Hz Fall 2012, Prof. JianJun Zhou V-38

39 Phase Noise Estimation-Leeson Leeson s Model L( ) S S ( ) ( ) 1 ( 2Q α Δω 2FkΤ Ρ s 0 ) 2 S ( ) L( ) 1 /( ) 3 1 /( ) 1 /( ) 1/( ) 2 Noise floor Δω Fall 2012, Prof. JianJun Zhou V-39

40 Phase Noise Hajimiri s Theory ν(t) ν(t) t t i(t) i(t) τ (a) t τ (b) t Fall 2012, Prof. JianJun Zhou V-40

41 Phase Noise Hajimiri s Theory 1 f ( x ) 1 ' f rise 1 f ' fall ' f rise f ' fall 2 x ( x ) 1 ' f rise 2 f ' fall 2 x 2 ' f rise 1 f ' fall Fall 2012, Prof. JianJun Zhou V-41

42 Phase Noise Hajimiri s Theory Use Impulse Sensitivity Function (ISF) G(x) which is a Periodic Function of Phase Shift for A Unit Impulse Applied at Time t = x Phase Noise is Maximum when Noise Current Impulses are Injected at Zero-Crossing Point Phase Noise is Minimum when Noise Current Impulses are Injected at Output Peaks Fall 2012, Prof. JianJun Zhou V-42

43 Phase Noise Hajimiri s Theory L( ) q 2 rms 2 max i 2 n / f 2( ) 2 L( ) c q max 2 in / f 8( ) 2 1/ f Fall 2012, Prof. JianJun Zhou V-43

44 Phase Noise in the VCO We see that all noise a distance ω around all the harmonics, including DC, contributes to the phase noise. DC 1/f noise contributes to the 1/f 3 region. Fall 2012, Prof. JianJun Zhou V-44

45 Optimization of Phase Noise in the LC VCO Evaluate the optimization gate length of the active device Calculate minimize spectral density of each oscillator noise source by using the optimization gate length of the active device. Derive the impulse sensitivity function of each oscillator source after the transient simulation is done when a current noise is injected at the node of the oscillator circuit (Cadence SpectreRF). Combine above results to obtain for each oscillator noise. source. Calculate Fourier Series Coefficient for each ISF Calculate the overall output phase noise using the results from above step. Fall 2012, Prof. JianJun Zhou V-45

46 Quadrature Phase Generator Divide-by-2 Quadrature VCO Poly phase shifter (RC-CR network) Fall 2012, Prof. JianJun Zhou V-46