EE141-Fall 2012 Digital Integrated Circuits. Announcements. Homework #3 due today. Homework #4 due next Thursday EECS141 EE141
|
|
- Rosa Robertson
- 5 years ago
- Views:
Transcription
1 EE4-Fall 0 Digital Integrated Circuits Lecture 7 Gate Delay and Logical Effort nnouncements Homework #3 due today Homework #4 due next Thursday
2 Class Material Last lecture Inverter delay optimization Today s lecture Gate delay and logical effort Reading (Chapter 6) 3 Complex Gate Delay Use RC model to estimate delay: R p R p R n C L R n Cint 4
3 Complex Gate Delay () Now what is the delay? R p R p R n C L R n Cint 5 Elmore Delay Elmore delay : approximation for delay of arbitrary (complex) RC circuits To find Elmore time constant : For each capacitor, draw path of current from cap to input Multiply C by sum of R s on current path that are common with path from V in to V out dd up RC products from all capacitors 6 3
4 Elmore Delay (Formal Method) Set V in to (incremental) ground pply current I across C, measure V out Calculate R eff = V out /I Time constant due to that C is R eff *C 7 Simplified Model: Elmore Delay Elmore R C R R C R R R C
5 nother Elmore Delay Example R V in R 3 V out C R C C 3 Elmore 9 nother Example Gate 0 5
6 Gate Sizing R p R p 4 R p R n C L 4 R p C int R n Cint R n R n C L Sizing Example C D D OUT = D + ( + C) C 6
7 Logical Effort 3 Question # ll of these are decoders Which one is best? 4 7
8 Question # Is it better to drive a big capacitive load directly with the NND gate, or after some buffering? C L C L Method to answer both of these questions: Logical effort Extension of buffer sizing problem 5 uffer Chain Review In Out C C C N N C L = C N+ Delay t f N inv i i For given N: C i+ /C i = C i /C i- To find N: C i+ /C i ~ 4 f i = C i+ /C i 6 8
9 Delay of NND Gate C dnand = 6C D Cgnand = 4C G = (4/3) C ginv C D /C G = t pnnd = kr W (C int + C L) = k(r sq,n *L/W)(WC dnand + C L ) = k(r sq,n *L*C gnand )(C dnand /C gnand +C L /(WC gnand )) = k(r sq,n *L*4*C g )(3/* +C L /(WC gnand )) = (4/3) t inv (3/ + f) 7 Delay of NOR Gate 4 C dnor = 6C D Cgnor = 5C G = (5/3) C ginv C D /C G = 4 t pnnd = kr(c int + C L) = k(r sq,n *L/W)(WC dnor + C L ) = k(r sq,n *L*C gnor )(C dnor /C gnor +C L /(WC gnor )) = k(r sq,n *L*5*C g )(6/5* +C L /(WC gnor )) = (5/3) t inv (6/5 + f) 8 9
10 Sizing a Chain t p,tot = t inv [C nd /C inv ) + 4/3*(3/*+C nr /C nd ) + 5/3*(6/5*+C L /C nr )] = t inv [( + C nd /C inv ) + ( + (4/3)*C nr /C nd ) + ( + (5/3)*C L /C nr )] You already know how to solve this! NND and NOR are just like inverters Except that their fanout looks larger i.e., get more delay than an inverter for same fanout 9 Logical Effort t p,tot = t inv [C nd /C inv ) + 4/3*(3/*+C nr /C nd ) + 5/3*(6/5*+C L /C nr )] = t inv [( + C nd /C inv ) + ( + (4/3)*C nr /C nd ) + ( + (5/3)*C L /C nr )] p gate parasitic delay f(w) LE logical effort f(w) f electrical fanout t pgate = t inv (p gate + LE f) 0 0
11 Finding Logical Effort of a Gate Inverter has the smallest logical effort and intrinsic delay of all static CMOS gates So normalize everything to inverter Logical effort LE is defined as: (R eq,gate C in,gate )/(R eq,inv C in,inv ) Easiest way to calculate (usually): Size gate to deliver same current as an inverter, take ratio of gate input capacitance to inverter capacitance LE increases with gate complexity Finding Logical Effort of a Gate Calculating LE by sizing for same drive strength: V DD V DD V DD 4 F F 4 F Inverter -input NND -input NOR LE = LE = LE =
12 Gate Sizing Convention Need to set a convention: What does a gate of size mean? For an inverter it is clear: C inv =, R inv = ½ For a gate, two possibilities: C gate = C inv R gate = (LE/)*R inv R gate = R inv / C gate = (*LE)*C inv In my notes, size C gate /C inv Size gate has twice the input capacitance of a unit inverter 3 dding ranching ranching effort: C b C L, onpath L, off path C Lon, path C L,on_path C L,off_path 4
13 Chain of rbitrary Gates N i Delay p LE f i i i Effective fanout: EF i = LE i f i Path electrical fanout: F = C out /C in Path logical effort: LE = LE LE LE N ranching effort: = b b b N Path effort: PE = LE F Path delay D = d i = p i + EF i 5 Optimum EF/Stage Just like buffer chain, but use (PE, EF) instead of (F, f): N EF EF PE N PE Effective fanouts: LE f = LE f = = LE N f N Minimum path delay / N ˆ N N i i i i i i D LE f p N PE p 6 3
14 Optimal Number of Stages For a given load, and given input capacitance of the first gate Find optimal number of stages and optimal sizing / N D NPE p i Remember: we can always add inverters to the end of the chain The best effective fanout EF PE / Nˆ is still around 4 (3.6 with =) 7 Example: Optimize Path a b c 5 LE = f = a LE = 5/3 f = b/a LE = 5/3 f = c/b LE = f = 5/c Electrical fanout, F = LE = PE = EF/stage = a = b = c = 8 4
15 Example: Optimize Path a b c 5 LE = f = a LE = 5/3 f = b/a LE = 5/3 f = c/b LE = f = 5/c Electrical fanout, F = 5 LE = (5/3) (5/3) = (5/9) PE = ( LE) F = (5/9) EF/stage = (5/9)^(/4) =.93 a =.93 b =.3 c =.59 5/c =.93 (5/3)c/b =.93 (5/3)b/a =.93 9 Method of Logical Effort Compute the path effort: PE = (LE)F Find the best number of stages N ~ log 4 PE Compute the effective fanout/stage EF = PE /N Sketch the path with this number of stages Work either from either end, find sizes: C in = C out *LE/EF Reference: Sutherland, Sproull, Harris, Logical Effort, Morgan-Kaufmann
16 Next Lecture pplying logical effort to a decoder 3 6
Logical Effort EE141
Logical Effort 1 Question #1 How to best combine logic and drive for a big capacitive load? C L C L 2 Question #2 All of these are decoders Which one is best? 3 Method to answer both of these questions
More informationEECS 151/251A Spring 2018 Digital Design and Integrated Circuits. Instructors: Nick Weaver & John Wawrzynek. Lecture 12 EE141
EECS 151/251A Spring 2018 Digital Design and Integrated Circuits Instructors: Nick Weaver & John Wawrzynek Lecture 12 1 Wire Models All-inclusive model Capacitance-only 2 Capacitance Capacitance: The Parallel
More informationDigital Integrated Circuits A Design Perspective
Digital Integrated Circuits Design Perspective Jan M. Rabaey nantha Chandrakasan orivoje Nikolić Designing Combinational Logic Circuits November 2002. 1 Combinational vs. Sequential Logic In Combinational
More informationAnnouncements. EE141-Spring 2007 Digital Integrated Circuits. CMOS SRAM Analysis (Read/Write) Class Material. Layout. Read Static Noise Margin
Vo l ta ge ri s e [ V] EE-Spring 7 Digital Integrated ircuits Lecture SRM Project Launch nnouncements No new labs next week and week after Use labs to work on project Homework #6 due Fr. pm Project updated
More informationEE141. Administrative Stuff
-Spring 2004 Digital Integrated ircuits Lecture 15 Logical Effort Pass Transistor Logic 1 dministrative Stuff First (short) project to be launched next Th. Overall span: 1 week Hardware lab this week Hw
More informationEE115C Digital Electronic Circuits Homework #5
EE115C Digital Electronic Circuits Homework #5 Due Thursday, May 13, 6pm @ 56-147E EIV Problem 1 Elmore Delay Analysis Calculate the Elmore delay from node A to node B using the values for the resistors
More informationEE141-Fall Digital Integrated Circuits. Announcements. Lab #2 Mon., Lab #3 Fri. Homework #3 due Thursday. Homework #4 due next Thursday
EE4-Fall 2000 Digital Integrated ircuits Lecture 6 Inverter Delay Optimization Announcements Lab #2 Mon., Lab #3 Fri. Homework #3 due Thursday Homework #4 due next Thursday 2 2 lass Material Last lecture
More informationInterconnect (2) Buffering Techniques. Logical Effort
Interconnect (2) Buffering Techniques. Logical Effort Lecture 14 18-322 Fall 2002 Textbook: [Sections 4.2.1, 8.2.3] A few announcements! M1 is almost over: The check-off is due today (by 9:30PM) Students
More informationEE M216A.:. Fall Lecture 5. Logical Effort. Prof. Dejan Marković
EE M26A.:. Fall 200 Lecture 5 Logical Effort Prof. Dejan Marković ee26a@gmail.com Logical Effort Recap Normalized delay d = g h + p g is the logical effort of the gate g = C IN /C INV Inverter is sized
More informationDigital Microelectronic Circuits ( ) Logical Effort. Lecture 7: Presented by: Adam Teman
Digital Microelectronic ircuits (361-1-3021 ) Presented by: Adam Teman Lecture 7: Logical Effort Digital Microelectronic ircuits The VLSI Systems enter - BGU Lecture 7: Logical Effort 1 Last Lectures The
More informationDigital EE141 Integrated Circuits 2nd Combinational Circuits
Digital Integrated Circuits Designing i Combinational Logic Circuits 1 Combinational vs. Sequential Logic 2 Static CMOS Circuit t every point in time (except during the switching transients) each gate
More informationLogic Gate Sizing. The method of logical effort. João Canas Ferreira. March University of Porto Faculty of Engineering
Logic Gate Sizing The method of logical effort João Canas Ferreira University of Porto Faculty of Engineering March 016 Topics 1 Modeling CMOS Gates Chain of logic gates João Canas Ferreira (FEUP) Logic
More informationEE141-Fall 2011 Digital Integrated Circuits
EE4-Fall 20 Digital Integrated Circuits Lecture 5 Memory decoders Administrative Stuff Homework #6 due today Project posted Phase due next Friday Project done in pairs 2 Last Lecture Last lecture Logical
More informationLogical Effort. Sizing Transistors for Speed. Estimating Delays
Logical Effort Sizing Transistors for Speed Estimating Delays Would be nice to have a back of the envelope method for sizing gates for speed Logical Effort Book by Sutherland, Sproull, Harris Chapter 1
More informationLecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: 1st Order RC Delay Models. Review: Two-Input NOR Gate (NOR2)
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 14: March 1, 2016 Combination Logic: Ratioed and Pass Logic Lecture Outline! CMOS Gates Review " CMOS Worst Case Analysis! Ratioed Logic Gates!
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 15: March 3, 2016 Combination Logic: Ratioed & Pass Logic, and Performance Lecture Outline! CMOS NOR2 Worst Case Analysis! Pass Transistor
More informationLecture 8: Logic Effort and Combinational Circuit Design
Lecture 8: Logic Effort and Combinational Circuit Design Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline q Logical Effort q Delay in a Logic Gate
More informationAnnouncements. EE141- Spring 2003 Lecture 8. Power Inverter Chain
- Spring 2003 Lecture 8 Power Inverter Chain Announcements Homework 3 due today. Homework 4 will be posted later today. Special office hours from :30-3pm at BWRC (in lieu of Tuesday) Today s lecture Power
More informationLecture 5. Logical Effort Using LE on a Decoder
Lecture 5 Logical Effort Using LE on a Decoder Mark Horowitz Computer Systems Laboratory Stanford University horowitz@stanford.edu Copyright 00 by Mark Horowitz Overview Reading Harris, Logical Effort
More informationVery Large Scale Integration (VLSI)
Very Large Scale Integration (VLSI) Lecture 4 Dr. Ahmed H. Madian Ah_madian@hotmail.com Dr. Ahmed H. Madian-VLSI Contents Delay estimation Simple RC model Penfield-Rubenstein Model Logical effort Delay
More informationEE241 - Spring 2000 Advanced Digital Integrated Circuits. Announcements
EE241 - Spring 2000 Advanced Digital Integrated Circuits Lecture 3 Circuit Optimization for Speed Announcements Tu 2/8/00 class will be pre-taped on Friday, 2/4, 4-5:30 203 McLaughlin Class notes are available
More informationECE429 Introduction to VLSI Design
ECE429 Introduction to VLSI Design Lecture 5: LOGICAL EFFORT Erdal Oruklu Illinois Institute of Technology Some of these slides have been adapted from the slides provided by David Harris, Harvey Mudd College
More informationEE 447 VLSI Design. Lecture 5: Logical Effort
EE 447 VLSI Design Lecture 5: Logical Effort Outline Introduction Delay in a Logic Gate Multistage Logic Networks Choosing the Best Number of Stages Example Summary EE 4475: VLSI Logical Design Effort
More informationEE M216A.:. Fall Lecture 4. Speed Optimization. Prof. Dejan Marković Speed Optimization via Gate Sizing
EE M216A.:. Fall 2010 Lecture 4 Speed Optimization Prof. Dejan Marković ee216a@gmail.com Speed Optimization via Gate Sizing Gate sizing basics P:N ratio Complex gates Velocity saturation ti Tapering Developing
More informationC.K. Ken Yang UCLA Courtesy of MAH EE 215B
Decoders: Logical Effort Applied C.K. Ken Yang UCLA yang@ee.ucla.edu Courtesy of MAH 1 Overview Reading Rabaey 6.2.2 (Ratio-ed logic) W&H 6.2.2 Overview We have now gone through the basics of decoders,
More informationVLSI Design, Fall Logical Effort. Jacob Abraham
6. Logical Effort 6. Logical Effort Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 207 September 20, 207 ECE Department, University of
More informationLecture 6: Logical Effort
Lecture 6: Logical Effort Outline Logical Effort Delay in a Logic Gate Multistage Logic Networks Choosing the Best Number of Stages Example Summary Introduction Chip designers face a bewildering array
More informationLogical Effort: Designing for Speed on the Back of an Envelope David Harris Harvey Mudd College Claremont, CA
Logical Effort: Designing for Speed on the Back of an Envelope David Harris David_Harris@hmc.edu Harvey Mudd College Claremont, CA Outline o Introduction o Delay in a Logic Gate o Multi-stage Logic Networks
More informationLecture 8: Combinational Circuit Design
Lecture 8: Combinational Circuit Design Mark McDermott Electrical and Computer Engineering The University of Texas at ustin 9/5/8 Verilog to Gates module mux(input s, d0, d, output y); assign y = s? d
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 16 CMOS Combinational Circuits - 2 guntzel@inf.ufsc.br
More informationCMOS Inverter. Performance Scaling
Announcements Exam #2 regrade requests due today. Homework #8 due today. Final Exam: Th June 12, 8:30 10:20am, CMU 120 (extension to 11:20am requested). Grades available for viewing via Catalyst. CMOS
More informationStatic CMOS Circuits. Example 1
Static CMOS Circuits Conventional (ratio-less) static CMOS Covered so far Ratio-ed logic (depletion load, pseudo nmos) Pass transistor logic ECE 261 Krish Chakrabarty 1 Example 1 module mux(input s, d0,
More information! Delay when A=1, B=0? ! CMOS Gates. " Dual pull-down and pull-up networks, only one enabled at a time
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Pass Transistor XOR Delay when A, B0? Start with equivalent RC circuit Lec : October 9, 08 Driving Large Capacitive Loads 3
More information9/18/2008 GMU, ECE 680 Physical VLSI Design
ECE680: Physical VLSI Design Chapter III CMOS Device, Inverter, Combinational circuit Logic and Layout Part 3 Combinational Logic Gates (textbook chapter 6) 9/18/2008 GMU, ECE 680 Physical VLSI Design
More informationEE115C Digital Electronic Circuits Homework #6
Problem 1 Sizing of adder blocks Electrical Engineering Department Spring 2010 EE115C Digital Electronic Circuits Homework #6 Solution Figure 1: Mirror adder. Study the mirror adder cell (textbook, pages
More informationCMOS logic gates. João Canas Ferreira. March University of Porto Faculty of Engineering
CMOS logic gates João Canas Ferreira University of Porto Faculty of Engineering March 2016 Topics 1 General structure 2 General properties 3 Cell layout João Canas Ferreira (FEUP) CMOS logic gates March
More informationDigital Integrated Circuits (83-313) Lecture 5: Interconnect. Semester B, Lecturer: Adam Teman TAs: Itamar Levi, Robert Giterman 1
Digital Integrated Circuits (83-313) Lecture 5: Interconnect Semester B, 2015-16 Lecturer: Adam Teman TAs: Itamar Levi, Robert Giterman 1 What will we learn today? 1 A First Glance at Interconnect 2 3
More informationInterconnect (2) Buffering Techniques.Transmission Lines. Lecture Fall 2003
Interconnect (2) Buffering Techniques.Transmission Lines Lecture 12 18-322 Fall 2003 A few announcements Partners Lab Due Times Midterm 1 is nearly here Date: 10/14/02, time: 3:00-4:20PM, place: in class
More informationCARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002
CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 18-322 DIGITAL INTEGRATED CIRCUITS FALL 2002 Final Examination, Monday Dec. 16, 2002 NAME: SECTION: Time: 180 minutes Closed
More informationLecture 4: CMOS review & Dynamic Logic
Lecture 4: CMOS review & Dynamic Logic Reading: ch5, ch6 Overview CMOS basics Power and energy in CMOS Dynamic logic 1 CMOS Properties Full rail-to-rail swing high noise margins Logic levels not dependent
More informationand V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )
ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets
More informationThe Wire. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Wire July 30, 2002 1 The Wire transmitters receivers schematics physical 2 Interconnect Impact on
More informationHomework #2 10/6/2016. C int = C g, where 1 t p = t p0 (1 + C ext / C g ) = t p0 (1 + f/ ) f = C ext /C g is the effective fanout
0/6/06 Homework # Lecture 8, 9: Sizing and Layout of omplex MOS Gates Reading: hapter 4, sections 4.3-4.5 October 3 & 5, 06 hapter, section.5.5 Prof. R. Iris ahar Weste & Harris vailable on course webpage
More informationLecture 9: Combinational Circuit Design
Lecture 9: Combinational Circuit Design Outline Bubble Pushing Compound Gates Logical Effort Example Input Ordering symmetric Gates Skewed Gates Best P/N ratio 0: Combinational Circuits CMOS VLSI Design
More informationDigital Microelectronic Circuits ( )
Digital Microelectronic ircuits (361-1-3021 ) Presented by: Dr. Alex Fish Lecture 5: Parasitic apacitance and Driving a Load 1 Motivation Thus far, we have learned how to model our essential building block,
More informationDesigning Information Devices and Systems II Fall 2017 Miki Lustig and Michel Maharbiz Homework 1. This homework is due September 5, 2017, at 11:59AM.
EECS 16 Designing Information Devices and Systems II Fall 017 Miki Lustig and Michel Maharbiz Homework 1 This homework is due September 5, 017, at 11:59M. 1. Fundamental Theorem of Solutions to Differential
More informationDigital Integrated Circuits A Design Perspective
Digital Integrated Circuits Design Perspective Jan M. Rabaey nantha Chandrakasan orivoje Nikolić Designing Combinational Logic Circuits November 2002. 1 Views / bstractions / Hierarchies ehavioral Structural
More informationLecture 8: Combinational Circuits
Introduction to CMOS VLSI Design Lecture 8: Combinational Circuits David Harris Harvey Mudd College Spring 00 Outline ubble Pushing Compound Gates Logical Effort Example Input Ordering symmetric Gates
More informationUNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences
UNIVERSITY OF LIFORNI, ERKELEY ollege of Engineering Department of Electrical Engineering and omputer Sciences Elad lon Homework #3 EE141 Due Thursday, September 13 th, 5pm, box outside 125 ory PROLEM
More informationIntroduction to CMOS VLSI Design. Logical Effort B. Original Lecture by Jay Brockman. University of Notre Dame Fall 2008
Introduction to CMOS VLSI Design Logical Effort Part B Original Lecture b Ja Brockman Universit of Notre Dame Fall 2008 Modified b Peter Kogge Fall 2010,2011,2015, 2018 Based on lecture slides b David
More informationThe CMOS Inverter: A First Glance
The CMOS Inverter: A First Glance V DD V in V out C L CMOS Properties Full rail-to-rail swing Symmetrical VTC Propagation delay function of load capacitance and resistance of transistors No static power
More informationLecture 8: Combinational Circuits
Introduction to CMOS VLSI Design Lecture 8: Combinational Circuits David Harris Harvey Mudd College Spring 004 Outline ubble Pushing Compound Gates Logical Effort Example Input Ordering symmetric Gates
More informationEE 466/586 VLSI Design. Partha Pande School of EECS Washington State University
EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 9 Propagation delay Power and delay Tradeoffs Follow board notes Propagation Delay Switching Time
More informationUNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences
UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #7 Solutions EECS141 PROBLEM 1: Logical Effort with Velocity Saturated
More informationIntroduction to CMOS VLSI Design. Lecture 5: Logical Effort. David Harris. Harvey Mudd College Spring Outline
Introduction to CMOS VLSI Design Lecture 5: Logical Effort David Harris Harve Mudd College Spring 00 Outline Introduction Dela in a Logic Gate Multistage Logic Networks Choosing the Best Number of Stages
More informationLecture 9: Combinational Circuits
Introduction to CMOS VLSI Design Lecture 9: Combinational Circuits David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q ubble Pushing q Compound Gates
More informationLecture 9: Interconnect
Digital Integrated Circuits (83-313) Lecture 9: Interconnect Semester B, 2016-17 Lecturer: Dr. Adam Teman TAs: Itamar Levi, Robert Giterman 23 May 2017 Disclaimer: This course was prepared, in its entirety,
More informationCMPEN 411 VLSI Digital Circuits Spring 2012
CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 09: Resistance & Inverter Dynamic View [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic]
More informationCPE/EE 427, CPE 527 VLSI Design I Delay Estimation. Department of Electrical and Computer Engineering University of Alabama in Huntsville
CPE/EE 47, CPE 57 VLSI Design I Delay Estimation Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) Review: CMOS Circuit
More informationAdvanced VLSI Design Prof. A. N. Chandorkar Department of Electrical Engineering Indian Institute of Technology- Bombay
Advanced VLSI Design Prof. A. N. Chandorkar Department of Electrical Engineering Indian Institute of Technology- Bombay Lecture - 04 Logical Effort-A Way of Designing Fast CMOS Circuits (Contd.) Last time,
More informationUNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. Professor Oldham Fall 1999
UNIVERSITY OF CLIFORNI College of Engineering Department of Electrical Engineering and Computer Sciences Professor Oldham Fall 1999 EECS 40 FINL EXM 13 December 1999 Name: Last, First Student ID: T: Kusuma
More informationEE115C Digital Electronic Circuits Homework #4
EE115 Digital Electronic ircuits Homework #4 Problem 1 Power Dissipation Solution Vdd =1.0V onsider the source follower circuit used to drive a load L =20fF shown above. M1 and M2 are both NMOS transistors
More informationEE 330 Lecture 6. Improved Switch-Level Model Propagation Delay Stick Diagrams Technology Files
EE 330 Lecture 6 Improved witch-level Model Propagation elay tick iagrams Technology Files Review from Last Time MO Transistor Qualitative iscussion of n-channel Operation Bulk ource Gate rain rain G Gate
More informationSpiral 2 7. Capacitance, Delay and Sizing. Mark Redekopp
2-7.1 Spiral 2 7 Capacitance, Delay and Sizing Mark Redekopp 2-7.2 Learning Outcomes I understand the sources of capacitance in CMOS circuits I understand how delay scales with resistance, capacitance
More informationDigital Integrated Circuits 2nd Inverter
Digital Integrated Circuits The Inverter The CMOS Inverter V DD Analysis Inverter complex gate Cost V in V out complexity & Area Integrity and robustness C L Static behavior Performance Dynamic response
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 14 The CMOS Inverter: dynamic behavior (sizing, inverter
More informationLecture 6: DC & Transient Response
Lecture 6: DC & Transient Response Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline Pass Transistors DC Response Logic Levels and Noise Margins
More informationEE 330 Lecture 37. Digital Circuits. Other Logic Families. Propagation Delay basic characterization Device Sizing (Inverter and multiple-input gates)
EE 330 Lecture 37 Digital Circuits Other Logic Families Static Power Dissipation Propagation Delay basic characterization Device Sizing (Inverter and multiple-input gates) Review from Last Time Inverter
More information! Dynamic Characteristics. " Delay
EE 57: Digital Integrated ircuits and LI Fundamentals Lecture Outline! Dynamic haracteristics " Delay Lec : February, 8 MO Inverter and Interconnect Delay 3 Review: Propogation Delay Definitions Dynamic
More informationEE141-Spring 2008 Digital Integrated Circuits EE141. Announcements EECS141 EE141. Lecture 24: Wires
EE141-Spring 2008 Digital Integrated Circuits Lecture 24: Wires 1 Announcements Hw 8 posted last graded homework Project phase II feedback to be expected anytime 2 Material Last Lecture: Wire capacitance
More informationName: Grade: Q1 Q2 Q3 Q4 Q5 Total. ESE370 Fall 2015
University of Pennsylvania Department of Electrical and System Engineering Circuit-Level Modeling, Design, and Optimization for Digital Systems ESE370, Fall 205 Midterm Wednesday, November 4 Point values
More informationEECS 151/251A Homework 5
EECS 151/251A Homework 5 Due Monday, March 5 th, 2018 Problem 1: Timing The data-path shown below is used in a simple processor. clk rd1 rd2 0 wr regfile 1 0 ALU REG 1 The elements used in the design have
More informationEE5780 Advanced VLSI CAD
EE5780 Advanced VLSI CAD Lecture 4 DC and Transient Responses, Circuit Delays Zhuo Feng 4.1 Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay
More informationProperties of CMOS Gates Snapshot
MOS logic 1 Properties of MOS Gates Snapshot High noise margins: V OH and V OL are at V DD and GND, respectively. No static power consumption: There never exists a direct path between V DD and V SS (GND)
More informationTopics. CMOS Design Multi-input delay analysis. John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut
Topics CMO Design Multi-input delay analysis pring 25 Transmission Gate OUT Z OUT Z pring 25 Transmission Gate OUT When is low, the output is at high impedance When is high, the output follows However,
More informationThe Inverter. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Inverter Revised from Digital Integrated Circuits, Jan M. Rabaey el, 2003 Propagation Delay CMOS
More informationAnnouncements. EE141- Fall 2002 Lecture 7. MOS Capacitances Inverter Delay Power
- Fall 2002 Lecture 7 MOS Capacitances Inverter Delay Power Announcements Wednesday 12-3pm lab cancelled Lab 4 this week Homework 2 due today at 5pm Homework 3 posted tonight Today s lecture MOS capacitances
More informationDynamic operation 20
Dynamic operation 20 A simple model for the propagation delay Symmetric inverter (rise and fall delays are identical) otal capacitance is linear t p Minimum length devices R W C L t = 0.69R C = p W L 0.69
More informationLecture 14: Circuit Families
Introduction to CMOS VLSI Design Lecture 4: Circuit Families David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Pseudo-nMOS Logic q Dynamic Logic q
More informationEE 434 Lecture 33. Logic Design
EE 434 Lecture 33 Logic Design Review from last time: Ask the inverter how it will interpret logic levels V IN V OUT V H =? V L =? V LARGE V H V L V H Review from last time: The two-inverter loop X Y X
More informationUNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences
UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #2 EECS141 Due Thursday, September 9, 5pm, box in 240 Cory PROBLEM
More informationLecture 1: Gate Delay Models
High Speed CMOS VLSI Design Lecture 1: Gate Delay Models (c) 1997 David Harris 1.0 Designing for Speed on the Back of an Envelope Custom IC design is all about speed. For a small amount of money, one synthesize
More informationUNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences
UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #2 - Solutions EECS141 Due Thursday, September 10, 5pm, box in 240
More informationEEC 118 Lecture #6: CMOS Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #6: CMOS Logic Rajeevan mirtharajah University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW 3 due this
More informationEEC 116 Lecture #5: CMOS Logic. Rajeevan Amirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation
EEC 116 Lecture #5: CMOS Logic Rajeevan mirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW
More informationLecture 12 CMOS Delay & Transient Response
EE 471: Transport Phenomena in Solid State Devices Spring 2018 Lecture 12 CMOS Delay & Transient Response Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor
More informationLecture 4: DC & Transient Response
Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response David Harris Harvey Mudd College Spring 004 Outline DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Slide
More informationChapter 4. Digital Integrated Circuit Design I. ECE 425/525 Chapter 4. CMOS design can be realized meet requirements from
Digital Integrated Circuit Design I ECE 425/525 Professor R. Daasch Depar tment of Electrical and Computer Engineering Portland State University Portland, OR 97207-0751 (daasch@ece.pdx.edu) http://ece.pdx.edu/~ecex25
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 24: April 19, 2018 Crosstalk and Wiring, Transmission Lines Lecture Outline! Crosstalk! Repeaters in Wiring! Transmission Lines " Where transmission
More informationLecture 6: Circuit design part 1
Lecture 6: Circuit design part 6. Combinational circuit design 6. Sequential circuit design 6.3 Circuit simulation 6.4. Hardware description language Combinational Circuit Design. Combinational circuit
More information7. Combinational Circuits
7. Combinational Circuits Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2017 September 25, 2017 ECE Department, University of Texas
More informationEE 230 Lecture 31. THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR
EE 23 Lecture 3 THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR Quiz 3 Determine I X. Assume W=u, L=2u, V T =V, uc OX = - 4 A/V 2, λ= And the number is? 3 8 5 2? 6 4 9 7 Quiz 3
More informationCPE/EE 427, CPE 527 VLSI Design I L13: Wires, Design for Speed. Course Administration
CPE/EE 427, CPE 527 VLSI Design I L3: Wires, Design for Speed Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) www.ece.uah.edu/~milenka/cpe527-05f
More informationEE141Microelettronica. CMOS Logic
Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit
More informationDigital Integrated Circuits EECS 312
14 12 10 8 6 Fujitsu VP2000 IBM 3090S Pulsar 4 IBM 3090 IBM RY6 CDC Cyber 205 IBM 4381 IBM RY4 2 IBM 3081 Apache Fujitsu M380 IBM 370 Merced IBM 360 IBM 3033 Vacuum Pentium II(DSIP) 0 1950 1960 1970 1980
More information! Crosstalk. ! Repeaters in Wiring. ! Transmission Lines. " Where transmission lines arise? " Lossless Transmission Line.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 24: April 19, 2018 Crosstalk and Wiring, Transmission Lines Lecture Outline! Crosstalk! Repeaters in Wiring! Transmission Lines " Where transmission
More informationEE241 - Spring 2000 Advanced Digital Integrated Circuits. Announcements
EE241 - Spring 2 Advanced Digital Integrated Circuits Lecture 11 Low Power-Low Energy Circuit Design Announcements Homework #2 due Friday, 3/3 by 5pm Midterm project reports due in two weeks - 3/7 by 5pm
More informationUNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences
UNIVERSITY OF CAIFORNIA, BERKEEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #7 - Solutions EECS141 Due Thursday, October 22, 5pm, box in 240 Cory
More informationDelay and Power Estimation
EEN454 Digital Integrated ircuit Design Delay and Power Estimation EEN 454 Delay Estimation We would like to be able to easily estimate delay Not as accurate as simulation But make it easier to ask What
More information