Self-Repairing and Self-Calibration: A Design/Test Strategy for Nano-scale CMOS

Transcription

1 Self-Repairing and Self-Calibration: A Design/Test Strategy for Nano-scale CMOS Kaushik Roy S. Mukhopadhyay, H. Mahmoodi, A. Raychowdhury, Chris Kim, S. Ghosh, K. Kang School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN

2 Process Variation in Nano-scale Transistors 1.4 Normalized Frequency % 5X 130nm Source: Intel Normalized Leakage (Isb( Isb) Delay and Leakage Spread Inter and Intra-die Variations Mean Number of Dopant Atoms Source: Intel Technology Node (nm) Random dopant fluctuation Device parameters are no longer deterministic

3 Process Variations: Failures, Test, Self- Calibration, and Self Repair Memories (Caches and Register Files) Failure analysis Updated March Test for process induced failures Process/Defect tolerant caches Self-Repairing SRAM s Leakage and delay sensors for self-repair Logic Failure analysis in pipelines and robust pipeline design Delay sensor to measure critical path delays and integrated test generation for robust segment delay coverage Updated scan chain logic FLH and FLS (First level hold and scan flip-flops) for lowpower (dynamic and leakage) and efficient delay testing Temperature control to prevent thermal runaway during burn-in

4 SRAM Memory Cell Failure Process variation: Device miss-match Cell failure Primary source: Random dopant fluctuation V th miss-match Results in three types of failures AF: Access time failure RF: Read failure WF: Write failure HF: Hold failure T ACCESS > T MAX VL Flipping VR No writing VL VR AF: Access time failure RF: Read failure WF: Write failure

5 Mechanisms of Parametric Failures BL Access Failure Read Failure Voltage WL ΔMIN BR Voltage WL V R V L Time -> Time -> Write Failure Hold Failure Voltage WL V L V R Voltage V DDH V R V L Time -> Time ->

6 Read Failure (RF) WL Monte Carlo Gaussian Model VDD 700 AXL PL V L = 1 PR V R = 0 AXR # of occurance NL NR BL I = I dsataxr I dlinnr dsatnl Subthreshold leakage ( I sub ) Gate leakage ( I gd ) Junction leakage ( I jn ) RF ( V ) P = P V > READ Solve for V READ TRIPRD ( VTRIPRD, VTRIPRD, gnd ) IdsatPL ( VTRIPRD, VTRIPRD, VDD P RF = P [ Z ( V V ) > 0] where, η = η η and σ = σ + σ Z V READ READ BR V TRIPRD TRIP Z = 1 F 2 V READ ) Solve for V TRIPRD Z (0) 2 V TRIPRD V READ [V] Distribution of V READ

7 Write Failure (WF) WL VDD Monte Carlo Gaussian Model Non Central F Model AXL V L = 1 NL PL V R = 0 NR PR AXR # of occurance T WL The write failures mostly comes from the long tail of the distribution. Non Central F distribution matches the tail of the distribution better. 100 Subthreshold leakage ( I sub ) 50 BL Gate leakage ( I gd ) Junction leakage ( I jn ) BR Twrite [ps] T I WRITE in( L) VTRIP CL( VL ) dv = I V in( L) ( VL ) I DD ; = current into L I, I dspl out( L) WF ( T ) P = P T > L ( V out( L) L ; if ( V ) if ( V WR WR < V V TRIPWR TRIPWR = current out of L I WRITE ) ) dsaxl P WF WL = t WR = T f WL WR ( twr) d( twr) = 1 FWR( TWL)

8 Hold Failure (HF) MODEL MEDICI Variation in δvt NR, δvt NL, δvt PL, δvt PR Monte Carlo Gaussian Model V DDMin at HOLD (V HOLD [V]) Variation in δvt NL, δvt PL Variation in δvt NR, δvt PR # of occurance V HOLD ΔVt [V] V DDHmin [V] V L Variation of and Distribution of V DDHmin HF ( V ) P = P V > DDHmin HOLD ( V δ Vt, δvt ) V ( V, δvt, δvt ) DDHmin, PL NL = TRIP DDHmin PR NR Solve for V DDHmin P HF = V f HOLD VDDHmin ( vddhmin) d( vddhmin) = 1 FVDDHmin( VHOLD)

9 Access Time Failure (AF) T ACCESS [ps] ΔVt applied to N R only (δvt NR ) ΔVt applied to AX R only (δvt AXR ) MODEL MEDICI # of occurance Distribution of T ACCESS Monte Carlo Gaussian Model T MAX ΔVt [V] Taccess [ps] AF Variation and distribution of T ACCESS with variation in δvt P = P > P AF ( TACCESS TMAX = t ACCESS f TACCESS = T MAX ) T ACCESS = C C I BL BR CBLΔ C BR MIN BR I BL = I dsataxr ( taccess ) d( taccess ) = 1 FTACCESS ( TMAX ) C B Δ MIN I subaxl ( i) i= 1,.., N

10 Basic Modeling Approach Estimation of the mean and the variance of a function several independent normal random variable T ACCESS = = f f ( V ( η Expand f in Taylor series with respect to Vt 1,,Vt 6 around their mean and consider up to 2 nd order terms. Estimate the mean and the variance as: Mean ( T t1 Vt 1, V ACCESS Variance ( T t 2, η,..., Vt 2 ) = ACCESS,..., η f ( η ) V = t 6 ) Vt 6 Vt1 ( f V ti ) i= 1,...,6,..., η ( 2 2 f V ) Estimation of the probability distribution function of Y Assume a normal pdf with the estimated mean and variance. The δvt of each transistors are assumed to be independent normal random variables. σ Vt α 1 ) + Vt6 i = 1,.., 6 ) + ( ) LW ( f i= 1,...,6 σ 2 Vti / V ti )( V ti ti η σ 2 Vti Vti ) +...

11 Estimation of Overall SRAM Cell F Failure Probability (P F ) [ ] P[ A R W H ] P = P Fail = U F F F F PASS AF WF Fail RF HF 1-P F P F

12 Estimation of Memory Failure Probability (P MEM ) P COL : Probability that any of the cells in a column fails P MEM : Probability that more than N RC (# of redundant columns) fail P COL = 1 (1 P F ) N and P MEM = N i= N COL RC + 1 N i COL P i COL ( 1 P ) COL N COL i P MEM Redundant Columns P F P COL

13 Estimation of Yield Select inter-die parameters (L, W, Vt) Find P F N INTER times Find P COL Find P MEM Find Yield Yield = 1 PMEM ( LINTER, WINTER, VtINTER ) N INTER INTER N INTER : the total number of inter-die Monte- Carlo simulations (i.e. total number of chips)

14 Snapshot: Transistor Sizing and Yield Yield 100% 80% 60% 40% 20% 0% 27% 76% 87% W N W A Proposed failure analysis assists SRAM designers to achieve maximum memory yield 65% WA/ WN

15 Parametric Failures in SRAM Cell AXL BL High-Vt PL NL PR NR WL BR Low-Vt AXR Transistor mismatch => Parametric failures Read failure Write failure Access failure Hold failure Chip Count Yield 33% Fault statistics σ Vt 30mv, using BPTM 45nm technology Number of faulty cells (N( Faulty Faulty-Cells ) Parametric Failures => Yield degradation 1049

16 SRAM Failure Mechanisms and Logic Fault Models Random Dopant Fluctuations; W, L, Tox Variations Process Variations Instability in SRAM cells Vt mismatch in Sense-amplifiers Delay variations in address decoders Circuit Level Deviations Hold Failure Access Failure Sense-amp Functional Failure Write Failure Flipping Read Failure Physical Failure Mechanisms Low Supply Data Retention Fault Data Retention Fault Random Read Fault Incorrect Read Fault Transition Fault Read Destructive Fault Deceptive Read Destructive Fault Logic Fault Models Deceptive read destructive faults are overlooked in conventional test sequences Hold failures not detectable in conventional test sequences

17 Efficient Testing of SRAM * Failures due to Process Variations Contributions Challenges Fault Coverage of Existing Test Sequences Optimized Test Sequences to improve fault coverage Test Time of Existing Test Sequences Novel DFT Circuit to reduce test time * IEEE VLSI Test Symposium,, May 2005

18 Test: Optimized March Test Sequence 1. Optimized March C- ( W0) ( R0 W1) ( R1 W0) ( R0 W1) (HOLD) ( R1 R1 W0) (HOLD) ( R0 R0) + Good fault coverage - Test time increases 2. March Q ( W0) (HOLD) ( R0 W0 W1 R1) (HOLD) ( R1 W1 W0 R0) ( R0) + Reduce the test time + Cover all the fault models induced by process variations - Not able to detect Transition Coupling Fault and Address Decoder Fault

19 March test sequence comparison Logic Fault Models Conventional Test Sequences Proposed Sequences March C- March B March SR Opt. March C- March Q Address Decoder Fault Data Retention Fault Low Supply Data Retention Fault Stuck-at Fault Transition Fault Random Read Fault Read Destructive Fault Deceptive Read Destructive Fault Incorrect Read Fault State Coupling Fault Disturb Coupling Fault Incorrect Read Coupling Fault Read Destructive Coupling Fault Transition Coupling Fault Test Time 10N 17N 14N 12N 10N

20 Double Sensing: A Novel DFT Circuit to Reduce Test Time In order to reduce test time, double sensing is used to detect Deceptive Read Destructive Fault in one cycle However, the WL can NOT be extended too long for test The The since WL content can in normal be of extended the mode cell flips so the as after for memory the the WL flipping should is to show still operates itself activated. on bitlines at the designed frequency. Disturbance Another No time parallel left is to generated sense-amp detect the during flipping is fired the since at the test the time to accelerate the WL is the dis-activated. development WL is disabled of the soon bitline after differential that. voltage. Read Access Timing 900m 800m 700m 600m 500m 400m 300m 200m 100m 0 WL VL VR 900m BL 800m 700m 600m 600m 500m 500m 400m 400m 300m 300m 200m 200m 100m 100m 0 SE 0 WL WL VL VL BL BL BR VR VR SE1 SE1 BR WL Already extended discharged bitline is pulled up The flipping is sensed. SE2 SE2 Then the required WL extension time is minimized.

21 Parametric Failures and Yield P MEM Redundant Columns Inter-die Variation P F SRAM die with a global shift in process parameter Failure Probability P COL Hold Failure Read Failure Access Failure Write Failure Std. dev. of intra-die variation Intra-die Variation => Cell, Column and Memory failure PMEM Yield = f ( Inter- die Variation) # Non- Faulty Die = # Total Die

22 What is the effect of Inter-die variation on Parametric Failures?

23 Inter-die Variation and Cell Failure LVT Nom. Vt HVT RF/HF high Read (RF) AF/WF high Access (AF) Hold (HF) Write (WF) Inter-die shift in process parameter amplifies the failure due to intra-die variations.

24 Inter-die Variation and Memory Failure LVT Nom. Vt HVT Reg. A High RF/HF Reg. B Low Failures Col. Fail. Prob. Reg. C High AF/WF Cell. Fail. Prob. Mem. Fail. Prob. Memory failure probabilities are high at high when interdie (global) shift in process is high.

25 How can we improve yield considering both inter-die and intra-die variations?

26 Adaptive Repairing of SRAM Array LVT Nom. Vt HVT Region A LVT Corner Region A Region B Region C P MEM 1 P MEM 1 Region C HVT Corner Read & Hold failures dominate Mem. Fail. Probability Access & Write failures dominate Reduce RF & HF P MEM 0 Reduce AF & WF Reduce the dominant failures at different inter-die corners to increase width of low failure region.

27 How can we reduce the dominant failures at different inter-die corners?

28 Body Bias and Parametric Failures WL VDD Overall Cell Fail. Prob Write (WF) Read (HF) Access (AF) BL GND VBB BR Hold (HF) Proper body bias can reduce parametric failures Forward bias reduces Access & Write failures Reverse bias reduces Read & Hold failures

29 Adaptive Repair using Body Bias LVT Nom. Vt HVT Region A LVT Corner Read & Hold failures dominate Region A Region B Region C RBB ZBB Mem. Fail. Probability FBB Region C HVT Corner Access & Write failures dominate Apply RBB P MEM 0 Apply FBB Reduce the dominant failures at different inter-die corners to increase width of low failure region.

30 Self-Repair Technique in SRAM SRAM Array Pre-Silicon Design of Circuit and Architecture Post-Silicon Adaptive Repair Separation of inter-die process corners Vt Binning Adaptive Repair using Body Bias Self-Repairing SRAM Enhanced Yield

31 How we can identify the inter-die Vt corner under a large random intradie variation? Monitor circuit parameters e.g. delay and leakage Effect of inter-die variation can be masked by that of intra-die variation Adding a large number of random variables reduces the effect of intra-die variation Y σ => μ = μ = μ σ = σ = σ = = n i= 1 n n Y X Y Xi N X & Y Xi N X=> i= 1 i= 1 μy N μx X i 1 σ

32 Vt Binning by Leakage Monitoring WL VDD BL GND BR ΔVt Inter = 100mV High Vt Nom. Vt Low Vt ΔVt Inter = 0mV ΔVt Inter = -100mV ΔVt Inter = -100mV ΔVt Inter = 0mV ΔVt Inter = -100mV

33 Self-Repair using Leakage Monitoring V DD Bypass Switch Calibrate Signal On-chip Leakage Monitor V out V REF1 V REF2 Comparator SRAM ARRAY V OUT SRAM Array Body bias Body-Bias Generator LVT V REF1 On-chip monitoring of leakage of entire array Body-bias is generated based on leakage monitor output Leakage monitored is bypassed in normal operating mode Nom. Vt V REF2 HVT Nom. Vt LVT Current Monitor Circuit

34 Yield Enhancement using Self-Repair 265KB Self-Repairing SRAM 265KB SRAM with No Body-Bias Self-Repairing SRAM using body-bias can significantly improve design yield.

35 Self-Repairing SRAM: Die Photo Self-Repair Circuit 64KB High-Vt SRAM 64KB Low-Vt SRAM

36 Schematic and measurement of self-repair mechanisms FBB signal Body voltage (Zero bias Body voltage (Forward Bias) Schematic of the Self-repairing SRAM Measured waveform of body voltage for Forward bias with On-chip FBB generator RBB signal Body voltage (Zero bias Body voltage (Reverse Bias) Bodybias generation logic (MUX switches are designed with level converter for negative bias, not shown here) Measured waveform of body voltage for 36 Reverse bias with On-chip RBB generator

37 Design and Measurement of Current Sensor Sensor Output [V] 2 Conv. design with 1.8 diode load in LVT Proposed design => Higher changre in Vout with process change Design with diode load => Lower change in Vout with process change Proposed design with LVT Conv. design with diode load in HVT Proposed design with HVT Temperature [C] sensor output with temperature and Vt change (simulation 0.13μm) # of occurance Proposed design in HVT Conv. design with diode load in HVT Proposed design in LVT Conv. design with diode load in LVT Sensor Output [V] Effect of intra-die variation on sensor output (simulation 0.13μm) Sensor Output [V] > Different symbols represent data from different chips Current Sensor Circuit Leakage Current [ua] > Measured current sensor output attached to the 64KB LVT array 37

38 P Fault = P AF U P RF U P WF In 45nm technology σ Vth 30mV P Fault > 1.0x10-3 Large number of faulty cells in nano-scale SRAM under process variation Failure Probability in SRAM Memory Cells Probability of Failure P AF P RF P WF P Fault MONTE CARLO simulation using BPTM 45nm tech σ Vth ( mv) Intrinsic Fluctuation of V th due to random dopant effect

39 Chip Count (Nchip) Fault Statistics in 32K Cache Conv. Yield 33.4% Fault statistics σ Vt 30mv, using BPTM 45nm technology MONTE CARLO simulation of 1000 chips N Faulty-Cells N Faulty-Cells = P Fault X N Cells (total number of cells in a cache) Conventional 32K cache results in only 33.4% yield Need a process/fault-tolerant mechanisms to improve the yield in memory

40 Basic Cache Architecture Index = Row Address + Column Address Multiple cache blocks are stored in a single row Minimize delay, area, routing complexity Column MUX selects one block

41 Basic Cache Architecture BPTM 45nm technology, 32KByte direct mapped cache # of Block in a Row 1 Block 2 Blocks 4 Blocks Decoder Delay 0.086ns 0.085ns Wordline Delay 0.069ns 0.075ns 0.128ns Bitline to Q Delay 0.452ns 0.355ns 0.313ns Total Delay 0.608ns 0.515ns 0.525ns Energy 0.166nJ 0.181nJ 0.195nJ For 32K cache best # of cache blocks/row = 2 We choose 4 blocks in a row for our design Results in higher yield 16.25% increase 2% cache access penalty 7% energy overhead

42 Fault-Tolerant Cache Architecture BIST detects the faulty blocks Config Storage stores the fault information Idea is to resize the cache to avoid faulty blocks during regular operation Faulty

43 Handle large number of faults without significantly reducing the cache size Resizing the Cache Config Storage is accessed in parallel with cache 00 Feeds the fault information to controller Controller alters the column address Force the column MUX to select a non-faulty block in the same row if the accessed block is faulty

44 Mapping Issue More than one INDEX are mapped to same block Include column address bits into TAG bits Resizing is transparent to processor same memory address

45 Config Storage Cache 32KByte Config Storage 1Kbit Blocks per row 4 x Block Size 32Byte 4bit Accessed in parallel with cache 4 bit fault information about 4 blocks stored in a single cache row One bit fault information per cache block Bits are determined by BIST at the time of testing Accessed using row address part of INDEX Provides the fault information of all the blocks in a cache row to controller

46 Controller Column address selection based on fault location Faulty Blocks in Accessed Row Fault Information by Config Storage Accessed Column Address Forced Column Address None rd Block nd &3 rd Block st, 2 nd & 3 rd Block All four Blocks 1111 NA NA NA NA Based on 4 bits read from Config Storage controller alters the column address

47 Controller Column address selection based on fault location Faulty Blocks in Accessed Row Fault Information by Config Storage Accessed Column Address Forced Column Address None rd Block nd &3 rd Block st, 2 nd & 3 rd Block All four Blocks 1111 NA NA NA NA One block in a row is faulty Selects the first available non-faulty block e.g 3 rd block 1 st block

48 Controller Column address selection based on fault location Faulty Blocks in Accessed Row Fault Information by Config Storage Accessed Column Address Forced Column Address None rd Block nd &3 rd Block st, 2 nd & 3 rd Block All four Blocks 1111 NA NA NA NA Two blocks in a row is faulty Selects two non-faulty blocks respectively e.g 2 nd block 1 st block 3 rd block 4 th block

49 Controller Column address selection based on fault location Faulty Blocks in Accessed Row Fault Information by Config Storage Accessed Column Address Forced Column Address None rd Block nd &3 rd Block st, 2 nd & 3 rd Block All four Blocks 1111 NA NA NA NA Three blocks in a row is faulty All the blocks are mapped to non-faulty block, e.g 4 th block One non-faulty block in each row, this architecture can correct any number of faults

50 Energy, Performance, and Area Overhead of Config Storage and Controller BPTM 45nm technology, 32KByte Cache, 1Kbit Config Storage Energy and Performance 32KB Cache Config Storage & Controller Delay (ns) Area overhead NA 0.5% Energy overhead NA 1.8% Controller changes the column address before data reaches at column MUX Does not affect the cache access time Negligible energy and area overhead (excluding BIST)

51 Results: P op (ECC, Redundancy and Proposed Scheme) P op : Probability that a chip with N Faulty-cells can be made operational Faults are randomly distributed across chip Yield is defined as: Y chip = 1 N Tot N P Faulty _ Cell op ( N Faulty _ Cell )* N Each scheme add some extra storage space P op includes the probability of having faults in these blocks ( N Faulty _ Cell To consider area, yield is redefined as: Y eff chip = Y chip A A chip chip _ without _ any _ scheme chip _ with _ fault _ tolerant _ scheme )

52 Results: P op Faulty cells Redundency R = 32 ECC 1bit Proposed Architecture Pop Prop. 65% ECC 6% N Faulty-Cells % of the chips with 105 faulty cells which can be saved by Proposed scheme ~ 65% (high fault tolerant capability) ECC ~ 6% Redundancy ~ 0%

53 Results: P op Pop Adding redundant rows (r) in config storage r=0 r=1 r=2 r=3 r= N Faulty-Cells P op improves with redundant rows in config storage r = 2 is optimum for 32K cache with 1Kbit config storage

54 Results: P op 1.0 Pop R=0 r=2 R=8 r=2 R=16 r=2 Proposed architecture with redundancy N Faulty-Cells Adding redundant rows (R) in cache in proposed scheme improves the P op further (optimum is R =8 for 32K cache)

55 % Yield Effective Yield of 32K Cache Optimum r = 2 Proposed Arch. Yield without any Redundancy Redundent Rows in Config Storage (r) 89 Proposed Architecture % Yield 100 ECC + Redundancy yield ~ 77% Conv. Yield Proposed Architecture with r = 2 ECC Redundency Redundent Rows in Cache (R) Proposed architecture + Redundancy yield ~ 93% (with 2 blocks in a cache row yield ~ 80%)

56 Chip Count (Nchip) Fault Tolerant Capability Fault statistics Chips saved by the proposed + redundancy (R=8, r=2) Chips saved by ECC + redundancy ( R=8) More number of saved chips as compare to ECC ECC fails to save any chips N Faulty-Cells Proposed architecture can handle more number of faulty cells than ECC, as high as 419 faulty cells Saves more number of chips than ECC for a given N Faulty-Cells

57 Chip Count (Nchip) Process Tolerance: Fault Statistics in 64K Cache Conv. Yield 33.4% Fault statistics σ Vt 30mv, using BPTM 45nm technology N Faulty-Cells N Faulty-Cells = P Fault X N Cells (total number of cells in a cache) Conventional 64K cache results in only 33.4% yield Need a process/fault-tolerant mechanisms to improve the yield in memory

58 Process-Tolerant Cache Architecture BIST detects the faulty blocks Config Storage stores the fault information Resize the cache to avoid faulty blocks during regular operation

59 Fault Tolerant Capability Chip Count (Nchip) Fault statistics Chips saved by the proposed + redundancy (R=8, r=3) Chips saved by ECC + redundancy ( R=16) More number of saved chips as compare to ECC N Faulty-Cells ECC fails to save any chips Proposed architecture can handle more number of faulty cells than ECC, as high as 890 faulty cells with marginal perf loss

60 CPU Performance Loss % CPU Performance Loss For a 64K cache averaged over SPEC 2000 benchmarks N Faulty-Cells Increase in miss rate due to downsizing of cache Average CPU performance loss over all SPEC 2000 benchmarks for a cache with 890 faulty cells is ~ 2%

61 Register File: Self-Calibration using Leakage Sensing C. Kim, R. Krishnamurthy, & K. Roy

62 Process Compensating Dynamic Circuit Technology Conventional Static Keeper clk LBL0 RS0 RS1 RS7 N0... D0 D1 D7 LBL1 Keeper upsizing degrades average performance

63 Process Compensating Dynamic Circuit Technology b[2:0] clk 3-bit programmable keeper W s 2W s 4W s LBL0 RS0 RS1 RS7 N0... D0 D1 D7 LBL1 C. Kim et al., VLSI Circuits Symp. 03 Opportunistic speedup via keeper downsizing

64 Robustness Squeeze Number of dies Noise floor saved dies Conventional This work Normalized DC robustness 5X reduction in robustness failing dies

65 Number of dies Delay Squeeze PCD μ = 0.90 Conventional This work Conv. μ = 1.00 μ : avg. delay Normalized delay 10% opportunistic speedup

66 Self-Contained Process Compensation Fab Wafer test Process detection Leakage measurement On-die leakage sensor Program PCD using fuses Customer Package test Burn in Assembly

67 On-Die Leakage Sensor For Measuring Process Variation current reference 73μm compa rators VBIAS gen. NMOS device current mirrors test interface 83μm C. Kim et al., VLSI Circuits Symp. 04 High leakage sensing gain Compact analog design sharing bias generators

68 Leakage Current Sensing Circuits I REF V BIAS + - V SEN d0 V SEN V DD /2 + - d0 T. Kuroda et al., JSSC, Nov M. Griffin et al., JSSC, Nov Susceptible to P/N skew and supply fluctuation Large area due to multiple analog bias circuits Limited leakage sensing gain 68

69 ingle Channel Leakage Sensing Circuit M1 (saturation) V SEN V BIAS + - d0 I REF + - V REF M2 (subthreshold) Basic principle: Drain induced barrier lowering Low sensitivity to P/N skew and supply fluctuation 69

70 PV Insensitive Current Reference (I REF ) V t generation circuit Subtraction circuit 2/0.4 6/0.4 18/0.4 18/0.4 6/0.4 2/0.4 I REF 2/0.4 6/0.4 18/0.4 1/1.6 6/0.8 6/0.8 4/0.8 4/0.8 S. Narendra et al., VLSI Circuits Symp Sub-1V process, voltage compensated MOS current generation concept Reference voltage, external resistor not required Scalable, low cost, flexible solution 70

71 PV Insensitive Bias Voltage (V BIAS ) 8/0.4 1/0.4 96/0.2 I 1 V REF BIAS log ( ) E. Vittoz et al., JSSC, June /0.2 kt = q W W (W 1 =96μm, W 2 =2μm) 2 PTAT containing no resistive dividers Based on weak inversion MOS characteristics Desired output voltage achieved via sizing 71

72 Comparator + - = 4/0.4 4/0.4 Subtraction circuit (-) (+) 8/0.4 8/0.4 8/0.4 output I REF 4/0.4 4/0.4 2-stage differential amplifier Already designed I REF is used for bias current 72

73 PV Sensitivity of Designed I REF, V BIAS V, 90nm CMOS, 80 C I REF V BIAS I REF V BIAS fast typical slow V DD (V) Process skew I REF variation < 4%, V BIAS variation < 2% Under realistic process skews, ±100mV supply voltage fluctuations 73

74 Proposed Leakage Current Sensing M1 (saturation) V SEN V BIAS + - d0 I REF + - V REF M2 (sub-threshold) fast typical slow NMOS M2 fast typical slow PMOS M1 I ds I ds 1.2V, 90nm CMOS, 80 C V SEN (V) V SEN (V) 74

75 Superimposed I-V Curves 1.2V, 90nm CMOS, 80 C slow typical fast V SEN =0.93V I ds V SEN (V) X higher V SEN swing than prior-art Process-voltage insensitive design 75

76 6-Channel Leakage Sensor Test Chip W P 2W P 3W P 4W P 6W P 9W P I REF + - V BIAS V REF W N - + VSEN1 W N W N W N W N W N - + VSEN2 - + VSEN3 - + VSEN4 - + VSEN5 - + VSEN6 V1 V2 V3 V1 V4 V5 OUT[2] OUT[1] Bubble rejection circuit V2 V4 V6 OUT[0] V1 V2 V3 V4 V5 V6 Incremental mirroring ratio for multi-bit resolution leakage sensing Shared bias generators compact design Process-voltage insensitive I REF, V BIAS gen. 76

77 Multi-Bit Resolution Leakage Sensing V, 90nm CMOS, 80 C Voltage (V) V REF V SEN6 V SEN5 V SEN4 V SEN3 V SEN2 V SEN fast typical slow Process skew Leakage level determined by comparing V SEN1 through V SEN6 with V REF 6-channel leakage sensor gives 7 level resolution 77

78 I REF + - V BIAS V REF Bubble rejection circuit Example: Operation at Fast Process Corner W P 2W P 3W P 4W P 6W P 9W P W N - + VSEN1 W N W N W N W N W N VSEN2 VSEN3 VSEN4 VSEN V1 V2 V3 V4 V5 V VSEN6 Voltage (V) V1 V2 V3 V1 V4 V5 V2 V4 V6 fast typical slow OUT[2] OUT[1] OUT[0] V REF Fast corner: output code

79 I REF + - Example: Operation at Typical V BIAS V REF Bubble rejection circuit Process Corner W P 2W P 3W P 4W P 6W P 9W P W N - + VSEN1 W N W N W N W N W N VSEN2 VSEN3 VSEN4 VSEN V1 V2 V3 V4 V5 V VSEN6 Voltage (V) V1 V2 V3 V1 V4 V5 V2 V4 V6 fast typical slow OUT[2] OUT[1] OUT[0] V REF Typical corner: output code

80 On-Die Leakage Sensor Test Chip current reference compar ators VBIAS gen. NMOS devices current mirrors test interface Technology 90nm dual Vt CMOS V DD 1.2V Resolution 7 levels Power consumption 0.66 Dimensions 83 X 73 μm 2

81 Leakage Binning Results Output codes from leakage sensor

82 Conclusion Statistical Failure Analysis Helps Enhance Yield Post Silicon Tuning/Calibration is Becoming Promising for Si Nano systems Built-In Leakage/Delay Sensors Provide Information on Intra-Die Process Variations