Low-Power Design Under Parameter Variations

Transcription

1 Low-Power Design Under Parameter Variations Kaushik Roy Purdue University Swarup Bhunia Case Western Reserve Univ Embedded Tutorial : ISLPED 08

2 Nanometer Design Challenges :Variation in Process Parameters 1.4 Inter and Intra-die Variations Device 1 Device 2 Channel length Normalized Frequency # dopant atoms 30% 130nm Source: Intel 5X Normalized Leakage (Isb( Isb) Delay and Leakage Spread Technology Node (nm) Random dopant fluctuation Source: Intel Device parameters are no longer deterministic 2

3 Technology Trend Bulk-CMOS V G V S Gate V D Source Floating Body Drain Buried Oxide (BOX) Substrate PD/SOI Fully-depleted body V S V G Gate V D Source Drain Buried Oxide (BOX) Substrate V back FD/SOI Single gate device DGMOS FinFET Trigate Multi-gate devices Nano devices Carbon nanotube III-V devices nano-wires Spintronics Design methods to exploit the advantages of technology innovations

4 Reliability Temporal degradation of performance -- NBTI Failure probability Defects Tech. generation Life time degradation Time

5 Pessimistic Design Hurts Speed/Power Number of dies (150nm CMOS Measurements, 110 C) nominal corner Normalized IOFF worst-case corner Substantial variation in leakage across dies 4X variation between nominal and worst-case leakage Performance determined at nominal leakage Robustness determined at worst-case leakage

6 Variation in Process Parameters & Self-repair Robust Memory Design Failure Mechanisms Read Failure Write Failure Hold Failure Access Failure Memory Self-Repair (nominal supply) Memory Test Methodology Robust Logic Design Low Power Solution Supply Scaling Failure Mechanisms Delay Failure Quality Degradation Design Time Technique Run Time Technique CRISTA RAZOR 6

7 Memory: Process Variation & Tolerance Impact of parametric process variations on memory failure statistics Memory Self-Repair Techniques Memory Test Methodologies 7

8 Robust Design: Process Variations in On-chip SRAMs PL NL PR AXL 1 0 NR WL AXR Parametric failures -Read, Write, Access, Hold Chip Count BL BR High-Vt Low-Vt Yield 33% Fault statistics σ Vt 30mv, using BPTM 45nm technology Simulation example of an 64KB Cache Number of faulty cells (N( Faulty Faulty-Cells Cells) Parametric failures can degrade SRAM yield

9 Inter-die Variation & Memory Failure LVT Nom. Vt HVT Reg. A High RF/HF Reg. B Low Failures Reg. C High AF/WF Failure Probability Cell. Fail. Prob. Mem. Fail. Prob. BPTM 70nm Devices Inter-die Vt shift [V] Memory failure probabilities are high when inter-die shift in process is high 9

10 Memory Self Repair Techniques: Circuit Level Mukhopadhyay, Roy: JSSC June 2007; TCAD Jan. 2008; ICCAD 2004,.. 10

11 Self-Repairing SRAM Array : The Core Idea LVT Nom. Vt HVT Region A LVT Corner Region A Region B Region C Region C HVT Corner Read & Hold failures dominate Access & Write failures dominate Reduce RF & HF Reduce AF & WF Reduce the dominant failures at different inter-die corners to increase width of low failure region 11

12 Memory Self-Repair using Leakage Monitor V DD Bypass Switch Calibrate Signal On-chip Leakage Monitor V out V REF1 V REF2 Comparator SRAM ARRAY V OUT SRAM Array Body bias Body-Bias Generator LVT V REF1 BPTM 70nm Entire array leakage is monitored to detect interdie corner and proper body-bias is applied Nom. Vt V REF2 HVT Nom. Vt LVT Current Monitor Circuit 12

13 Test-Chip of Self-Repairing SRAM Isolated cell VCO 16 KB block Sensor + Ref. gen. VCO 64 KB LVT Array BB gen Ref. and sensor output [V] Silicon Results Leakage sensor (LVT array) High-reference Low-reference Chip numbers Technology : IBM 0.13 μm Dual-Vt Triple-well tech. Number of Trans: ~ 7 million Die size: 16mm 2 On-chip leakage sensor, Reference, & body-bias generators RBB signal Body voltage (Zero bias Body voltage (Reverse Bias) 13

14 Memory Self-Repair: Architecture Level Agarawal, Roy TVLSI 2005

15 Fault-Tolerant Cache Architecture Faulty BIST detects the faulty blocks Config Storage stores the fault information Idea is to resize the cache to avoid faulty blocks during regular operation 15

16 Mapping Issue More than one INDEX are mapped to same block Include column address bits into TAG bits Resizing is transparent to processor same memory address 16

17 Fault Tolerant Capability Chip Count (Nchip) Fault statistics Chips saved by the proposed + redundancy (R=8, r=3) Chips saved by ECC + redundancy ( R=16) More number of saved chips as compare to ECC ECC fails to save any chips N Faulty-Cells Proposed architecture can handle more number of faulty cells than ECC, as high as 890 faulty cells Saves more number of chips than ECC for a given N Faulty-Cells 17

18 CPU Performance Loss % CPU Performance Loss For a 64K cache averaged over SPEC 2000 benchmarks N Faulty-Cells Increase in miss rate due to downsizing of cache Average CPU performance loss over all SPEC 2000 benchmarks for a cache with 890 faulty cells is ~ 2% 18

19 Process Tolerance: Register Files Kim et. al. VLSI Circuit Symposium 2004

20 Process Compensating Dynamic Circuit Technology b[2:0] clk 3-bit programmable keeper W s 2W s 4W s LBL0 RS0 RS1 RS7 N0... D0 D1 D7 LBL1 C. Kim et al., VLSI Circuits Symp. 03 Opportunistic speedup via keeper downsizing

21 Robustness Squeeze Number of dies Noise floor saved dies Conventional This work Normalized DC robustness 5X reduction in robustness failing dies

22 Number of dies Delay Squeeze PCD μ = 0.90 Conventional This work Conv. μ = 1.00 μ : avg. delay Normalized delay 10% opportunistic speedup

23 On-Die Leakage Sensor For Measuring Process Variation current reference 73μm compa rators VBIAS gen. NMOS device current mirrors test interface 83μm C. Kim et al., VLSI Circuits Symp. 04 High leakage sensing gain 90nm dual-vt, Vdd=1.2V, 7 level resolution, 0.66

24 Leakage Binning Results Output codes from leakage sensor

25 Self-Contained Process Compensation Fab Wafer test Process detection Leakage measurement On-die leakage sensor Program PCD using fuses Customer Package test Burn in Assembly

26 Logic: Process Variation & Tolerance Design time technique Statistical Design Dual-V th Assignment under variations Supply scaling & delay failures CRitical path ISolation for Timing Adaptiveness (CRISTA) CRISTA for Digital Signal Processing (DSP) Run time technique Shadow Latches (RAZOR) Adaptive Body Bias (ABB) CRISTA: Ghosh, Bhunia, Roy; TCAD Nov. 2007; ICCAD 2006; CICC 2007 Razor: Ernst, Austin, Mudge; IEEE MICRO Nov.-Dec

27 Statistical Design No consideration for the variation in process parameters Circuit is optimized for the area (power) with designed delay constraint A number of dies have to die due to the variation Worst-case design methodology Assume the worst-case variation for all the transistors Too pessimistic: wastage of resources (area; power) # of dies designed delay delay

28 Statistical Design: Problem formulation Minimize total power Gate size: x i Delay constraint at output: A 0 Yield constraint: γ Subject to Minimize 5 1,..., i U x L P p A D x i i i p i o i i i i = = α Yield γ 0 γ n = 5 (gates) s = 3 (inputs) 2 virtual components

29 Statistical Design: Example Statistical gate sizing for improving yield under area (power) constraint or vice versa Statistical dual-v th assignment under yield constraint Statistical multi-v DD assignment under yield constraint Simultaneous gate sizing and dual V th assignment IF 4ns IF Latches ID ID EX 5ns 5ns 6ns 3ns Throughput = 1 Job / Max(stage delay) = 1 Job / 6ns (a) EX MEM MEM WB WB Incorporating imbalance among pipeline stage delay enhances yield! SD1 SD2 SD3 SD4 SD5 Throughput = 1 Job / Max(stage delay) = 1 Job / Max(SD1, SD2, SD3, SD4, SD5) (b) Datta et al. TCAD06

30 Parameter Variations & Dual-V th Design Agarwal, Kang, Bhunia, Roy; TVLSI

31 Design of High-V t in Nano-Scale Regime Threshold voltage implants/ higher substrate doping were used in sub-µ technologies to design high-v t devices Scaling devices requires (to reduce SCE) High substrate doping Application of halo profiles Supersedes any traditional high-v t implant High-V t devices increasing the strength of (nano-scale regime) halo doping

32 High-V Devices and Different t Leakage Components Subthreshold source gate n+ drain n+ n+ p-sub Halo p+ p+ Gate tunneling Reverse junction BTBT Leakage (na) nm Low-Vt Subthreshold Gate Junction BTBT 90nm High-Vt 50nm Low-Vt 50nm High-Vt Higher halo doping Subthreshold leakage Junction BTBT Reduction in subthreshold leakage in dual-v t design is at the expense of increase in junction BTBT

33 Dual-V th Design Non critical paths (high-v th ) Critical path (Low-V th ) Dual-V th assignment for mainly active leakage reduction Improves dynamic power slightly Increases number of critical paths affects path delay testability

34 Dual-V Design and Process t Variation Dual-V t design utilizes the slack between off-critical and critical paths to assign high-v t Increases the number of critical paths Increases the mean of the circuit delay distribution Moreover, high-v t transistors have large σ variation due to high doping concentration more random dopant fluctuation Increases the delay spread

35 Yield Loss in Dual-V Design under t Process Variation # of Dies 4 x nm ISCAS c Mean delay 2 shift 1 Low V t Dual V t Delay constraint 9.67% Yield loss Circuit delay (ps) Dual-Vt design Increase in mean of circuit delay distribution & delay spread More dies fail to meet the delay constraint resulting in yield loss

36 Yield using CONV, OPT1 and OPT2 CONV results in average 17% and max 59% yield loss in 50nm tech. STAT imposes 95% yield constraint 50nm: STAT ~ 55% leakage savings (average) 25nm: STAT ~ only 11% leakage savings (average) CONV overestimates leakage saving by 36% In scaled technologies, dual-v t optimization results in almost negligible power savings, if the yield constraint is forced

37 Supply Scaling Power Process Variation Delay failures!! Increased Power!! Power T c Path Delay CLK VDD <VDD Power Path Delay CLK VDD >VDD Voltage (a) Scaling Down Supply Voltage Voltage (a) Scaling Up Supply Voltage V 1 V 2 V V 3 V 4 CLK VDD Multi- VDD Power (b) Multi-Voltage/Multi-Vt Design Frequency (b) Gate Sizing Low power and robustness do not go hand-in-hand 37

38 CRISTA Design Framework Nominal Conventional System Scaled # of paths delay target S # of paths delay target Complete Failure path delay path delay CRISTA Design Nominal Graceful Degradation In Performance Scaled # of paths delay target S # of paths delay target Predictable and rare by design path delay path delay Best performance possible at lowest power with parametric error tolerance 38

39 CRISTA Design Principle evaluate evaluate based on prediction T c 2T c CLK CLK VDD<1V non-critical path activation VDD<1V critical path activation CRISTA Design Principle: Scale down the supply while making delay failures predictable Avoid failures by adaptive clock stretching at rated frequency Ensure that critical paths are activated rarely 39

40 Case Study: Adder P 0 G 0 P 1 G 1 P 2 G 2 P 3 G 3 C in Cout FA FA FA FA Interesting features: Single critical path (activated by P 0 P 1 P 2 P 3 =1 & C i,0 =1) Low activation probability of critical path Timing slack between critical and longest off-critical path VDD = 1V, TCLK = 260ps Crit. path delay=260ps longest off-crit. path delay=165ps P = 13uW (1-cycle) VDD = 0.8V, TCLK = 260ps Crit. path delay=330ps longest off-crit. path delay=260ps P = 7.4uW (rare 2-cycles, decoder) 44% power saving by reducing supply voltage and adaptive clocking 40

41 CRISTA for Random Logic Original Circuit X i = 1 CF11 X i = 0 (X i, X j )= (1,1) CF32 (X i, X j )= (1,0) CF42 x i x j x k (X i X j X k )= (1,0,1) CF53 (X i X j X k )= (1,0,0) CF63 MUX Network PO CF21 Inputs Inputs LEVEL1 (50%) LEVEL2 (25%) LEVEL3 (12.5%) Stopping conditions: area, delay constraints delay target Average power saving = 60% Avg performance penalty=5.9% (with 4 control variables) Average area overhead = 18% # of paths path delay S 1 41

42 Application of CRISTA to Pipeline* CRISTA Pipeline CLK LFSR fixed vectors VDD m 4:1 mux TM1TM2 CLK FFs Stalling Logic freeze Predecoder Carry-Lookahead Adder Predecoder FFs gclk Comparator Conventional Pipeline TM1 TM2 FFs Outputs Clock generator Regular pipeline GDS Layout Test logic CRISTA pipeline Test logic fixed vectors VDD o 2:1 Mux TM1 FFs Carry-Lookahead Adder FFs Comparator FFs Outputs Power saving ~40% Performance loss ~13% Area overhead~9% S Ghosh, P Batra,, K Kim and K Roy, Low-power and process tolerant pipeline design in scaled technologies, CICC,

43 Application of CRISTA in Thermal Mgmt Can we maintain rated frequency during thermal management? Key contributions: Adaptive systems for dynamic thermal management 43

44 Temperature Aware Design using CRISTA* # paths S # paths Secondary critical (it will run with twocycles at V DDL2 ) Critical (it will run with two-cycles at V DDL1 and V DDL2 ) 2 cycle bound path delay path delay S 3 S 2 S 1 Scale down the supply at elevated temperatures while making delay failures predictable Maintain rated frequency Avoid the failures by adaptive clock stretching Ensure that critical paths are activated rarely Tradeoff between temperature and performance loss S Ghosh, S Bhunia and K Roy, Low overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling, DATE

45 Simulation Results MCNC benchmarks, 70nm devices, Nominal supply = 1V, T amb = 100 o C Org(VDDH), freq=f Org(VDDL), freq=f/2 CRISTA(VDDL1), freq=f(adaptive) CRISTA(VDDL2), freq=f(adaptive) Temperature( o C) cht sct pcle mux cmb alu2 cm150a decod Similar temperature reduction as conventional technique (i.e. supply scaling with half frequency) Avg performance penalty=5.9% (at V DDL1 ) and 15.2% (at V DDL2 ) compared to 50% in conventional technique Avg area overhead ~14% 45

46 Micro-Architectural Implementation T REF1 T REF2 Sel Temp sensor freeze CLK Predecoder 0 1 V DDH V DDL IF ID EX MEM WB Applied to execution stage (adders and multipliers) of in-order pipeline Can be an add-on to standard DVFS S Ghosh, J Choi, P Ndai, and K Roy, O2C: Occasional Two-Cycle operations for dynamic thermal management in high performance embedded In- Order microprocessors, ISLPED

47 DTM Policies Temperature threshold CRISTA: Case 1 Temperature threshold for DVFS T REF2 T REF2 Temperature threshold for CRISTA T REF1 CRISTA Triggered CRISTA released T REF1 CRISTA: Case 2 DVFS T REF2 T REF2 DVFS triggered CRISTA released DVFS Triggered T REF1 T REF1 CRISTA Triggered DVFS released DVFS released 47

48 Max. Temp (C) Max. Temp (C) Simulation Results SPEC CINT benchmarks (gcc) No DTM 70 DVFS triggered Time (sec) DVFS triggering 65 avoided in CRISTA Time (sec) Avoids requirement of full-chip DVFS DVFS CRISTA DVFS: Dynamic Supply and Frequency Scaling CRISTA : Occasional 2-Cycle Operation V f (GHz) DVFS CRISTA No DTM

49 Simulation Results Peak Temperature (TREF1=75 o C, TREF2=80 o C) No DTM DVFS CRISTA T(degree C) bzip2 crafty eon gap gcc gzip mcf parser perlmk twolf vortex vpr Average reduction in peak temperature ~6.6% ~ with ~3.4% throughput loss and ~4.2% ~ area overhead 49

50 VDD Scaling, Process Variation, and Quality Trade-off: DCT, Color Interpolation, General FIR Filtering Banerjee, Karakonstantis, Roy; Design Automation and Test in Europe (DATE) 2007 Karakonstantis, Banerjee, Roy, Chakrabarti; ICCAD 2007 Banerjee, Roy; ISLPED 2007

51 Basic Idea All computations are not equally important for determining outputs Identify important and unimportant computations based on output sensitivity Compute important computations with higher priority Delay errors due to variations/ Vdd scaling affect only non-important computations Gradual degradation in output with voltage scaling and process variations

52 DCT Based Image Compression Process 8 8 blocks Source image X JPEG Encoder Block Diagram FDCT Round Z T Z T ' Q Quantizer V Entropy Encoder Compressed Image Data image Z = T X T ' X W Transpose Y Z 1D DCT 1D DCT Memory DCT is used in current international image/video coding standards - JPEG, MPEG, H.261, H.263

53 Energy Distribution of a 2D-DCT Output High energy components (important outputs 75% energy) Low energy components (less important outputs) Can important components be computed with higher priority?

54 Design Methodology x 0 w 0 w 8 w 16 w 24 w 32 w 40 w 48 w 56 x 1 x 2 x 3 x 4 T.x t 1D-DCT w 1 w 2 w 3 w 4 Faster Computation x 5 x 6 w 5 w 6 Slower Computation x 7 (a) Input Block (b) w 7 1D- intermediate DCT outputs z 0 z 1 z 2 z 3 z 4 Faster Computation Slower Computation 1D-DCT y 0 y 1 y 2 y 3 y 4 y 5 y 6 y 7 Faster Computation Slower Computation (d) Final DCT outputs (c) Transpose Memory

55 ( x 0 + x 7 ) d ( x + x ) d 3 4 ( x 2 + x 5 ) d ( x + x ) d 1 6 ( x 0 - x 7 ) a ( x- x ) a 1 6 ( x - x ) e ( 1 x - 6 x ) e 2 5 ( x- x ) f 1 6 ( x - x ) f 3 4 ( x - x ) e 2 ( x 2 - x 5 ) a ( x - x ) a ( 3-4 x x ) f 2 ( x - x ) f Path Delays for 1D-DCT outputs << >> + << + << >> w 0 w (2 adders delay) 4 << (3 adders delay) w 1 (3 adders delay) w 7 (4 adders delay) ( x 0 + x 7 ) e ( x + x ) e 3 4 ( x + x ) f ( 1 x + 6 x ) f 0 7 ( x 2 + x 5 ) f ( x + x ) f 3 4 ( x + x ) f 3 4 ( x + x ) f 1 6 ( x 2 + x 5 ) e ( x + x ) e 1 6 ( x 0 - x 7 ) a ( x - x ) a 2 ( x - x ) e 3 4 ( x - x ) a 3 4 ( x - x ) a 1 6 ( x - x ) f ( 3-4 x x ) f << + << << >> ( x 0 - x 7 ) e ( x - x ) e ( 3 x 0-4 x 7 ) f ( x - x ) f << + << >> + + w 2 (3 adders delay) w 6 (4 adders delay) w 3 (3 adders delay) w 5 (4 adders delay)

56 Proposed DCT under Vdd scaling Proposed Design with high/low delay paths Scaled Vdd: Longer paths under Vdd scaling w 0 w 1 w 2 w 3 Important Computations w 0 w 1 w 2 w 3 w 4 w 5 w 6 w 7 Vdd1 Longer Delays w 4 w 5 w 6 w 7 D2 Paths Not Computed Extreme Scaled Vdd: Shorter paths affected Only DC component Paths Not Computed w 0 w 1 w 2 w 3 w 4 w 5 w 6 w 7 D3 > D4 Vdd3 < Vdd2 < Vdd1(nominal)

57 1D-DCT Path Delay Comparisons Conventional DCT Proposed DCT Path1(w0) Path2(w1) Path3(w2) Path4(w3) Path5(w4) Path6(w5) Path7(w6) Path8(w7) Computation Paths Delay(ns)

58 Effect of Vdd Scaling Different Architectures at Nominal Voltage Convention al WTM DCT CSHM DCT (2 alphabet) Proposed DCT 1.0V CSHM DCT (2 alphabets) DCT with WTM Proposed DCT 1.0 V Power (mw) Delay (ns) Area (um 2 ) V FAILS FAILS PSNR (db) Proposed Architecture at Reduced Voltage 0.8 V FAILS FAILS Proposed DCT Vdd=0.9V Proposed DCT Vdd=0.8V Power (mw) 17.53(41.2%) 11.09(62.8%) PSNR (db) Graceful degradation of proposed DCT architecture under Vdd scaling ( Vdd can be scaled to 0.75V) Conventional architectures fails

59 CRISTA for DSP Systems Design Principle Scale down supply voltage Design/algorithm such that failures can only occur in less critical section -- minimal quality degradation Robust under process variations possible delay failures are confined in non-critical components Graceful degradation in quality of service 59

60 CRISTA for DSP Systems 2. Finite Impulse Response (FIR) 3. Color Interpolation critical coefficients less-critical coefficients Gi 1, j >>2 Gi, j 1 G 1 Gi+1, j G 2 Gi, j+1 Vdd >>2 Ri, j >>1 M1 Ri, j -2 Ri, j+2 Ri+2, j Ri -2, j G 3 Power(mW) Vdd M Power at Nominal/Scaled Voltage FAILS Conv. 33.6% FAILS Voltage(V) 1.0 V 0.9 V 0.8 V 21.6% Bilinear component is critical and gradient component is less-critical Design architecture such that failures can only occur in gradient term Conv FAILS FAILS LCCSE Proposed 60

61 Runtime Techniques RAZOR: Dan Ernst et. al., MICRO Tschanz et al., JSSC02.

62 A Runtime Compensation Technique : Shadow Latch (RAZOR) Standard Latch D CLK Q Shadow Latch Delay E RAZOR: Dan Ernst et. al., MICRO Post-Silicon technique for dynamic supply scaling and timing error detection/correction Energy consumption can be reduced by ~42% with performance hit of less than 1% Error correction overhead is 1% for a 10% error rate 62

63 Post-Si Adaptive Body Bias (ABB) Used as an effective tool for process compensation RBB is effective to reduce leakage FBB is effective to improve operating frequency of a design in active mode Bidirectional ABB can be used to compensate for die-to-die process parameter variations Optimal PMOS/NMOS bias needs to be selected Die count 100% Accepted 80% 110C dies: 60% 1.1V NBB 40% 20% S-ABB 0% Normalized frequency Norm leakage Circuit Block PD PD PD PD Bias Gen. PD PD PD PD Tschanz et al., JSSC02.

64 Summary Low power and process tolerance typically impose contradictory design requirements Statistical design suffers from reduced effectiveness under large process variations Variation-resilient techniques such as CRISTA can be very amenable for low-power design Process compensating design techniques both for memory and logic can be very effective to minimize power dissipation while compensating for variations. Design methodologies targeting different levels of design abstraction is necessary to achieve high performance, low power, and higher yield 64