Process-Tolerant Low-Power Design for the Nano-meter Regime

Transcription

1 Process-Tolerant Low-Power Design for the Nano-meter Regime Kaushik Roy Electrical & Computer Engineering Purdue University

2 Exponential Increase in Leakage µm 1 µm 100 nm 10 nm Silicon Micro- electronics Source n+ I I ON OFF Subthreshold Leakage = 6 10 Gate Leakage Bulk Gate n+ Junction leakage Drain Silicon Nano- electronics ION 3 10 I Leakage Power (% of Total) OFF 50% 40% 30% 20% 10% 0% Must stop at 50% Technology (µ) Non-Silicon Technology ON 2~6 = OFF ~ 10 A. Grove, IEDM I I

3 2003 Technology Trend Bulk-CMOS V G V S Gate V D Source Floating Body Drain Buried Oxide (BOX) Substrate PD/SOI Fully-depleted body V S V G Gate V D Source Drain Buried Oxide (BOX) Substrate V back FD/SOI Single gate device DGMOS FinFET Trigate Multi-gate devices Nano devices Carbon nanotube III-V devices nano-wires Spintronics Design methods to exploit the advantages of technology innovations

4 Variation in Process Parameters Inter and Intra-die Variations Device 1 Device 2 Channel length 3 0 % 1 30nm Source: Intel 5X Device parameters are no longer deterministic Normalized Frequency # dopant atoms N o rm alized L eakage e (Isb( Isb) Delay and Leakage Spread Source: Intel Technology Node (nm) Random dopant fluctuation

5 Reliability Temporal degradation of performance -- NBTI Failure probability Tech. generation Time Defects Life time degradation

6 Pessimistic Design Hurts Performance Number of dies (150nm CMOS Measurements, 110 C) nominal corner Normalized IOFF worst-case corner Substantial variation in leakage across dies 4X variation between nominal and worst-case leakage Performance determined at nominal leakage Robustness determined at worst-case leakage

7 7 Global and Local Variations Random Dopant Fluctuation δv t LOCAL σ LOCAL intra-die V t GLOBAL σ GLOBAL inter-die δ V = V + δ V t t GLOBAL t LOCAL

8 8 Process Tolerance: Memories S. Mukhopadhaya, Mahmoodi, Roy VLSI Circuit Symposium 2006, JSSC 2006, TCAD

9 Parametric Failures: Read Failure 9 WL AXL V TRIPRD V L = 1 + PL NL PR NR V R = 0 - V READ AXR Voltage WL V L V R =V READ Time -> - + BL BR Voltage WL V R ( V ) P = P V > RF READ TRIPRD Read failure => Flipping of Cell Data while Reading V L Time ->

10 Parametric Failures in SRAM 10 WL PL PR AXL 1 0 NL NR AXR BL High-Vt Low-Vt BR Parametric failures Read Failures Write Failures Access Failures Hold Failures Test & Repair using Redundancy Faulty chips Working chips Parametric failures can degrade SRAM yield

11 Process Variations in On-chip SRAM 11 Chip Count Yield 33% Fault statistics σ Vt 30mv, using BPTM 45nm technology Simulation of an 64KB Cache A. Agarwal, et. al, JSSC, Number of faulty cells (N( Faulty Faulty-Cells Cells) 1049 Parametric failures Yield degradation

12 Inter-die Variation & Cell Failures Low Vt Corners Read failure Hold failure σ GLOBAL High Vt Corners Access failure Write failure inter-die Vt shift ( V th-global )

13 Inter-die Variation & Memory Failure 13 LVT Nom. Vt HVT BPTM 70nm Devices Memory failure probabilities are high when inter-die shift in process is high

14 Self-Repairing SRAM Array 14 LVT Nom. Vt HVT Region A LVT Corner Region A Region B Region C Region C HVT Corner Read & Hold failures dominate Access & Write failures dominate Reduce RF & HF Reduce AF & WF Reduce the dominant failures at different inter-die corners to increase width of low failure region

15 Post-Silicon Repair: Proposed Approach 15 σ σ L O C A L L O C A L intra-die intra-die σ GLOBAL inter-die Apply correction to the global variation to reduce number of failures due to local variations

16 Self-Repairing SRAM Array 16 LVT Nom. Vt HVT Region A Region B Region C RBB ZBB FBB Reduce the dominant failures at different inter-die corners to increase width of low failure region

17 How to identify the inter-die Vt corner under a large intra-die variation? 17 WL VDD BL GND BR Monitor circuit parameters, e.g. leakage current Effect of inter-die variation can be masked by intra-die variation

18 Array Leakage Monitoring 18 Y σ = => = 1 σ N Y X X i i= 1 µ Y N µ X Adding a large number of random variables reduces the effect of intra-die variation Leakage of entire SRAM array is a reliable indicator of the inter-die Vt corner

19 Self-Repair using Leakage Monitoring 19 V DD Bypass Switch Calibrate Signal On-chip Leakage Monitor V out V REF1 V REF2 Comparator SRAM ARRAY V OUT SRAM Array Body bias Body-Bias selection FBB ZBB RBB Entire array leakage is monitored to detect inter-die corner and proper body-bias is selected

20 Yield Enhancement using Self-Repair 20 Self-Repairing SRAM using body-bias can significantly improve design yield

21 Test-Chip of Self-Repairing SRAM 21 VCO Isolated cell 16 KB block VCO 64 KB LVT Array Sensor + Ref. gen. BB gen Technology : IBM 0.13 µm 128KB SRAM Dual-Vt Triple-well tech. Number of Trans: ~ 7 million Die size: 16mm2 VLSI CKT Symp. 2006, ITC 2005 Simulation results for 1MB array designed in IBM 0.13µm

22 Continuous vs Quantized Body Bias 22 Quantized (3 Level: FBB, ZBB, RBB) body bias scheme is a cost effective solution with good yield enhancement possibility

23 Process Tolerance: Register Files Kim et. al. VLSI Circuit Symposium 2004

24 Process Compensating Dynamic Circuit Technology Conventional Static Keeper clk LBL0 RS0 RS1 RS7 N0... D0 D1 D7 LBL1 Keeper upsizing degrades average performance

25 Process Compensating Dynamic Circuit Technology b[2:0] clk 3-bit programmable keeper W s 2W s 4W s LBL0 RS0 RS1 RS7 N0... D0 D1 D7 LBL1 C. Kim et al., VLSI Circuits Symp. 03 Opportunistic speedup via keeper downsizing

26 Robustness Squeeze Number of dies Noise floor saved dies Conventional This work Normalized DC robustness 5X reduction in robustness failing dies

27 Number of dies Delay Squeeze PCD μ = 0.90 Conventional This work Conv. μ = 1.00 μ : avg. delay Normalized delay 10% opportunistic speedup

28 On-Die Leakage Sensor For Measuring Process Variation current reference 73μm compa rators VBIAS gen. NMOS device current mirrors test interface 83μm C. Kim et al., VLSI Circuits Symp. 04 High leakage sensing gain 90nm dual-vt, Vdd=1.2V, 7 level resolution, 0.66

29 Leakage Binning Results Output codes from leakage sensor

30 Self-Contained Process Compensation Fab Wafer test Process detection Leakage measurement On-die leakage sensor Program PCD using fuses Customer Package test Burn in Assembly

31 Self-Repair: Architecture Level Agarawal, Roy TVLSI 2005

32 Fault-Tolerant Cache Architecture Faulty BIST detects the faulty blocks Config Storage stores the fault information Idea is to resize the cache to avoid faulty blocks during regular operation

33 Mapping Issue More than one INDEX are mapped to same block TAG INDEX Column Address INDEX New TAG Off Off Include column address bits into TAG bits Resizing is transparent to processor same memory address

34 Fault Tolerant Capability Chip Count (Nchip) Fault statistics Chips saved by the proposed + redundancy (R=8, r=3) Chips saved by ECC + redundancy ( R=16) More number of saved chips as compare to ECC ECC fails to save any chips N Faulty-Cells Proposed architecture can handle more number of faulty cells than ECC, as high as 890 faulty cells Saves more number of chips than ECC for a given N Faulty-Cells

35 CPU Performance Loss % CPU Performance Loss For a 64K cache averaged over SPEC 2000 benchmarks N Faulty-Cells Increase in miss rate due to downsizing of cache Average CPU performance loss over all SPEC 2000 benchmarks for a cache with 890 faulty cells is ~ 2%

36 Logic: Process Tolerance

37 37 Logic: A New Paradigm for Low-Voltage, Variation Tolerant Circuit Synthesis Using Critical Path Isolation (CRISTA) Ghosh, Bhunia, Roy -- ICCAD 2006

38 Razor Approach 38 Standard Latch D CLK Q Shadow Latch Delay E RAZOR: Dan Ernst et. al., MICRO Post-Silicon technique for dynamic supply scaling and timing error detection/correction Error correction overhead is 1% for a 10% error rate

39 Vdd Scaling and Process Tolerance: Conventional Solutions Low power: Reduce the supply voltage Error rate increases Dual-Vt/dual-VDD assignment Number of critical paths increases 39 Robustness: Increase supply voltage Power dissipation increases Upsize the gates Switching capacitance increases Low power and robustness: conflicting requirements

40 CRISTA: Basic Idea 40 evaluate evaluate based on prediction T c 2T c CLK VDD=1V VDD<1V non-critical path path activation activation Important points: Scale down the supply while making delay failures predictable Avoid the failures by adaptive clock stretching Ensure that critical paths are activated rarely

41 Design Considerations for CRISTA 41 Number of paths predictable and restricted to a logic section having low activation probability CLK Design A Design A: conventional design Design B: proposed design Design B S 2 +S S 3 1 S 2 S 3 T c S 1 VDD=1V VDD=1V path delay Design B VDD<1V Few predictable critical paths Low activation probability of critical paths Slack between critical and non-critical paths under variations

42 Case Study: Adder P 0 G 1 P G 1 P 2 G 2 P 3 G 3 Co,3 42 P 0 G 1 P 1 G 1 P 2 G 2 P 3 G 3 C i,0 C o,0 C o,1 C o,2 C o,3 FA FA FA FA Interesting features: Single critical path (activated by P 0 P 1 P 2 P 3 =1 & C i,0 =1) Low activation probability of critical path VDD = 1V, TCLK = 260ps VDD = 0.8V, TCLK = 260ps Crit. path delay=260ps longest non-crit. path delay=165ps P = 13uW (1-cycle) Crit. path delay=330ps longest non-crit. path delay=260ps P = 7.4uW (rare 2-cycles, decoder) 44% power saving by reducing voltage and, operating critical path at 2-cycle and other paths at 1-cycle Can we apply same technique to any random logic?

43 Carry Select Adder 43 Long latency path (LLP) Short latency path (SLP1) Short latency path (SLP2) LATENCY PREDICTOR BLOCK A i : i-bit Adder, M k : k-stage MUX A 5 A 4 A 3 A 2 A 2 A 5 A 4 A 3 A 2 A 2 C o0 C i0 =0 C out M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 C o1 C in = 0 C i1 =1 A 5 A 4 A 3 A 2 A 2 A 5 A 4 A 3 A 2 A 2 Stage 10 Stage 6 Stage 1 ~20% power saving with ~6% area overhead

44 Carry Save Multiplier 44 Vector Merging Adder Critical Path Longest off-critical path HA HA HA FA FA FA LATENCY PREDICTOR BLOCK FA FA FA FA HA FA 25% power saving with ~5% area overhead

45 Wallace Tree Multiplier 45 Partial Products Full Adders Half Adder Vector Merging Adder Critical path Longest off-critical path Stage 1 Stage 2 Stage 3 Vector Merging Adder Final Product 29% power saving with ~4% area overhead

46 Simulation Results 46 Ripple Carry Adder Carry Save Multiplier % Power savings ISO Yield = 92% % Area overhead % Power savings ISO Yield = 90% %Area overhead bits 16 bits 32 bits bits 16 bits 32 bits 6 %Power savings Wallace Tree Multiplier ISO Yield = 96% 8 bits 12 bits 16 bits %Area overhead % Throughput penalty Performance penalty (WTM) % Throughput penalty % Area Overhead 6 bits 8 bits 10 bits 12 bits 20 bits % Area Overhead

47 Random Logic: Shannon s Expansion 47 f ( x,..., x,..., x ) = x f ( x,..., x = 1,..., x ) + x f ( x,..., x = 0,..., x ) ' 1 i n i 1 i n i 1 i n = x ' i CF1 + xi CF2 CF = f ( x,..., x = 1,..., x ); CF = f ( x,..., x = 0,..., x ) 1 1 i n 2 1 i n CF 1 (x i =1) f1 Prob =50% MUX f CF 11 Prob =25% MUX f1 CF 2 (x i =0) f2 x i CF 12 Prob =50% Prob =25% x j inputs Activation probability of cofactors can be reduced How to choose Control Variable?

48 Further Isolation and Slack Creation by Sizing 48 CF32 Original Circuit CF11 CF42 CF53 CF63 MUX Network PO CF21 Inputs Inputs Slack creation strategy Lagrangian Relaxation based sizing (B.C. Paul et. al., DAC 2004) is used Non-critical paths are selectively made faster Critical paths are slightly slowed down

49 Simulation Results 49 % Imp. in power MCNC benchmarks, 70nm Process % imp in power with switching activity = 0.2 % imp in power with switching activity = 0.5 Area (x10 3 )um^ MCNC benchmarks, 70nm Process Original design Proposed design 0 cht sct pcle mux decod cm150a x2 alu2 count 0 cht sct pcle mux decod cm150a x2 alu2 count Power Area Average power saving = ~50% Average area overhead = 18% Avg performance penalty=5.9% (with 4 control variables) for signal prob=0.5

50 CLK LFSR fixed vectors VDD m 4:1 mux Two-Stage Pipeline with Test Logic TM1TM2 fixed vectors VDD o 2:1 Mux TM1 CLK SFFs Stalling Logic freeze Predecoder Carry-Lookahead Adder Predecoder SFFs SFFs Low Power Robust Pipeline Carry-Lookahead Adder gclk SFFs Comparator Comparator Conventional Pipeline TM1 TM2 SFFs SFFs Outputs Outputs Clock generator Regular pipeline GDS Layout Test logic Proposed pipeline Test logic Power measurement of proposed pipeline 40% extra reduction using CRISTA ~40% power saving with ~13% performance penalty 20% reduction in conventional pipeline 50

51 VDD Scaling, Process Variation, and Quality Trade-off: DCT Banerjee, Karakonstantis, Roy Design Automation and Test in Europe (DATE)

52 Basic Idea All computations are not equally important for determining outputs Identify important and unimportant computations based on output sensitivity Compute important computations with higher priority Delay errors due to variations/ Vdd scaling affect only non-important computations Gradual degradation in output with voltage scaling and process variations 52

53 DCT Based Image Compression Process 8 8 blocks Source image X JPEG Encoder Block Diagram FDCT Round Z T Z T ' Q Quantizer V Entropy Encoder Compressed Image Data image Z = T X T ' X W Transpose Y Z 1D DCT 1D DCT Memory DCT is used in current international image/video coding standards - JPEG, MPEG, H.261, H

54 Energy Distribution of a 2D-DCT Output High energy components (important outputs 75% energy) Low energy components (less important outputs) Can important components be computed with higher priority? 54

55 Design Methodology x 0 w 0 w 8 w 16 w 24 w 32 w 40 w 48 w 56 x 1 x 2 x 3 x 4 T.x t 1D-DCT w 1 w 2 w 3 w 4 Faster Computation x 5 x 6 w 5 w 6 Slower Computation x 7 (a) Input Block (b) w 7 1D- intermediate DCT outputs z 0 z 1 z 2 z 3 z 4 Faster Computation Slower Computation 1D-DCT y 0 y 1 y 2 y 3 y 4 y 5 y 6 y 7 Faster Computation Slower Computation (d) Final DCT outputs (c) Transpose Memory 55

56 ( x 0 + x7 ) d ( x + x ) d 3 4 ( x 2 + x5 ) d ( x + x ) d 1 6 ( x 0 - x 7 ) a ( x - x ) a 1 6 ( x - x ) e ( 1 x - 6 x ) e 2 5 ( x - x ) f 1 6 ( x - x ) f 3 4 ( x - x ) e 2 ( x 2 - x 5 ) a ( x - x ) a ( 3-4 x x ) f 2 ( x - x ) f Path Delays for 1D-DCT outputs << >> + << + << >> + + w (2 adders delay) + w 4 (3 adders << delay) 0 w 1 (3 adders delay) w 7 (4 adders delay) ( x 0 + x 7 ) e ( x + x ) e 3 4 ( x + x ) f ( 1 x + 6 x ) f 0 7 ( x 2 + x 5 ) f ( x + x ) f 3 4 ( x + x ) f 3 4 ( x + x ) f 1 6 ( x 2 + x 5 ) e ( x + x ) e 1 6 ( x 0 - x 7 ) a ( x - x ) a 2 ( x - x ) e 3 4 ( x - x ) a 3 4 ( x - x ) a 1 6 ( x - x ) f ( 3-4 x x ) f << >> << + << + ( x 0 - x 7 ) e ( x - x ) e ( 3 x 0-4 x 7 ) f ( x - x ) f << >> << w 2 (3 adders delay) w 6 (4 adders delay) w 3 (3 adders delay) w 5 (4 adders delay) 56

57 Proposed DCT under Vdd scaling Proposed Design with high/low delay paths Scaled Vdd: Longer paths under Vdd scaling w 0 w 1 w 2 w 3 Important Computations w 0 w 1 w 2 w 3 w 4 w 5 w 6 w 7 Vdd1 Longer Delays w 4 w 5 w 6 w 7 D2 Paths Not Computed Extreme Scaled Vdd: Shorter paths affected Only DC component Paths Not Computed w 0 w 1 w 2 w 3 w 4 w 5 w 6 w 7 D3 > D4 Vdd3 < Vdd2 < Vdd1(nominal) 57

58 1D-DCT Path Delay Comparisons Conventional DCT Proposed DCT 58 Path1(w0) Path2(w1) Path3(w2) Path4(w3) Path5(w4) Path6(w5) Path7(w6) Path8(w7) Computation Paths Delay(ns)

59 Effect of Vdd Scaling Different Architectures at Nominal Voltage Convention al WTM DCT CSHM DCT (2 alphabet) Proposed DCT 1.0V CSHM DCT (2 alphabets) DCT with WTM Proposed DCT 1.0 V Power (mw) Delay (ns) Area (um 2 ) V FAILS FAILS PSNR (db) Proposed Architecture at Reduced Voltage 0.8 V FAILS FAILS Proposed DCT Vdd=0.9V Proposed DCT Vdd=0.8V Power (mw) 17.53(41.2%) 11.09(62.8%) PSNR (db) Graceful degradation of proposed DCT architecture under Vdd scaling ( Vdd can be scaled to 0.75V) Conventional architectures fails 59

60 Temporal Degradation: NBTI Kang, Roy, et. al. TCAD, DAC-07

61 Temporal Reliability Issues in CMOS Technology HCI Hot Carrier Injection NBTI Negative Bias Temperature Instability Increase in V T of PMOS with time The dominant reliability factors in scaled tech. TDDB, etc.

62 NBTI: Negative Bias Temperature Instability Interface trap generation due to Si-H bond breaking Interface trap (N IT ) generation at the channel interface due to the Si-H bond breaking, when negative gate bias is applied With time, V T increases, subthreshold slope (S) increases, mobility degrades, Drive current (I DS ) reduces and affect the PMOS speed Overall reduces the lifetime of PMOS

63 NBTI: Experimental Data 10-1 Experimental Simulation V Th [V] 10-2 ~t 0.17 trend line Stress time [s] PMOS V T degrades as a power of time due to NBTI Fixed exponent of 1/6 matches the simulation data* * V. Huard and M. Denais, IRPS 2004

64 Power-law V T degradation Model N H (0) N H Reaction rate: dn IT = k [ N N ] k N N R dt (0) F 0 IT IT H 0 D H t k k F R [ N N ] = N N 0 (0) IT IT H 0 Distance into oxide y Conservation of hydrogen: IT D t H ( 0 ( ) ) (, ) N t = N y t dy 0 H 1 ( 0) NIT = NH DH t 2 V = T q N C OX IT k N NIT t D t 2k F ( ) = ( ) H R NBTI degrades in time of exponent 1/6

65 Mobility degradation factor Mobility degradation due to NBTI is expressed in an additional V T shift, noted as m Overall temporal V T shift model is expressed as, ox VT = (1 + m) qχ E e C OX E0 t 0.25 E ox

66 Impact of NBTI on circuit performance

67 Circuit Performance Degradation % change Vt Inverter Delay ROSC delay time (s) 10 9 Performance (delay) degradation also follows the power trend with same 0.17 exponent In CMOS logic, only the rising (L2H) delay s are affected

68 Circuit Performance degradation cont. % Change S i = 1 (worst case) S i < 1 (with activity) V th Time (s) Delay degradation in ISCAS c432 Activity factor (switching activity) does not affect much on the delay degradation In reality, activity factor s are balanced in the normal operations

69 Design method considering the NBTI degradation

70 NBTI-aware design method NBTI-aware over-design Reduced lifetime due to NBTI degradation Required lifetime of the design max ckt. delay time Delay Constraint Over-design is required to guarantee a lifetime stability of the circuit LR sizing is used to optimize the circuit Size the circuit considering the worst-case V T degradation over the lifetime

71 LR Sizing considering NBTI 1. Delay Constraint (D MAX ) 2. Required Lifetime (T Life ) Lifetime Constraint A new design constraint Calibrate switching activity s (S i ) in each node Compute V T shift in each node considering S i Power-law V T model LR sizing with delay constraint D MAX Optimal sizing from Lagrangian Relaxation* NBTI-aware Design * C. Chen et. al., TCAD 1999 Guarantee a lifetime stability under NBTI degradations

72 Simulation results 1. Delay degradation in ISCAS85 benchmark circuits after 10 years Circuit No. of Trans. Nominal delay (ps) % delay degrad. (10 yrs) S i = 1 S i < 1 c c c c c c c c74l * All benchmarks are synthesized in BPTM 70nm technology

73 Simulation results cont. 2. Area overhead in NBTI-aware sizing Circuit Nominal delay (ps) Nominal area (um) % Area overhead S i = 1 S i < 1 c c c c c c c c74l * All benchmarks are synthesized in BPTM 70nm technology

74 V S = 0V P+ Negative Bias Temperature H H H H x x x x H H x H Si Si Si Si V GS < 0V H 2 H 2 H 2 H 2 H 2 P+ n-sub V BODY = 0V GATE OXIDE DRAIN Instability V D = 0V After NBTI degradation PMOS specific Aging Effect Generation of (+) traps Reaction-Diffusion (RD) model* Time exponent ~ 1/6 *M. A. Alam, IEDM 03 k N NIT t D t 2k F ( ) = ( ) 1 V = T q 0 6 H R N C OX IT

75 NBTI in Digital Circuits WL i o 1 BL B BL i o 2 V L V R i Logic Circuits f MAX decreases Timing failure with time Memory Circuits Static Noise Margin (SNM) Read & Write Stability Parametric Yield Temporal V Th increase in PMOS affects critical performance factors of digital VLSI circuits

76 NBTI: Random Logic Circuits Delay Degrad. STD cells Logic Cell INV NAND NAND NOR NOR fanin t= Delay (ps) 3 years Δ (%) f MAX reduction (%) ISCAS 85 Benchmark Circuits, PTM 65nm Gate delay: analytical delay model considering NBTI Circuit delay: NBTI-aware Static Timing Analysis (STA) Circuit f MAX time exponent n ~ 1/ c2670 c5315 c1908 c499 c3540 c % f MAX decrease n~1/6 PTM 65nm ISCAS 85 Benchmarks Time (s) 3 years Lifetime

77 NBTI: 6T SRAM Cell Degradation in SNM (%) Static Noise Margin (SNM) PTM 60nm, 125 C CR = 1.33 PR = /6 trend line Time (s) CDF Distribution in Write Margin t=0 t=10 8 t=10 7 t=10 6 WM improves with time Write Margin (V) SNM degrades by more than 10% in 3 years % SNM Degradation time exponent n ~ 1/6 WM improves with time under NBTI

78 Design for Reliability under NBTI ps c1908 Area (um) INIT TR-Based Cell-Based Cell-based Area Saving From TR-based Simulation Setup Synthesized in PTM 65nm 1/6 V Th degradation model 125 C Stress temperature 50% Signal Probability at PI s Delay (ps) Gate Sizing applied to guarantee lifetime functionality of design 11.7% overhead for Cell-based sizing 6.13% overhead for TR-based sizing 45% improvement in area overhead Runtime complexity for TR-based sizing is identical to that of Cell-based sizing

79 I DDQ based NBTI Characterization Microphotograph Layout Inverter Chain V DD V in Technology Die Size I/O Pin T ox V DD CMOS 130nm 20 (mm 2) (nm) 1.2 (V) 1000 stages I DDQ Measurement Test Circuit Fabricated 1000 stage INV chain DC Stress in I DDQ

80 Correlation between I DDQ & f MAX % I DDQ (V in =0.0) degradation I DDQ (V in =0.0) I DDQ (V in =1.7) n > 1/6 S 1 S 2 V stress = C MAX MIN < 1.2% Time (s) n ~ 1/ % I DDQ (V in =1.7) degradation I DDQ reduction (%) c2670 c5315 c1908 c499 c3540 c Linear relationship C, 65nm PTM ISCAS Benchmarks 10 0 f MAX reduction (%) D M < 3ms, Temp=125 C, V stress =1.7V I DDQ degradation n~1/6 during Clear signature of NBTI Correlation between I DDQ and f MAX can be used to predict circuit performance degradation under NBTI % I DDQ decrease % f MAX increase n~1/6 I ( t) f ( t) leak 1/ 6 MAX Rleak = t = R freq Ileak (0) fm AX (0) R = K R ( K :constant) freq leak

81 I DDQ based Characterization Technique Initial Characterization Compute R leak, R fmax Compute KfMAX = Rleak / RfMAX Reliability Extrapolation For each I DDQ measurement sample, Rleak is computed R fmax = K fmax X R leak Estimate f MAX degradation Lifetime Projection Project I DDQ using KfMAX Temp. Dependency Design phase Post-silicon phase Circuit-level NBTI Reliability Characterization I DDQ test is used Expensive f MAX testing is avoided (or minimized) Accurate circuit level performance degradation can be predicted IC specific burn-in to qualify the target produce Efficient way of field monitoring: dynamic local signature of produce usage Possible usage in other reliability sources; HCI NBTI Characterization Report

82 Conclusions Process Variation and Process Tolerance is becoming important There is a need to optimize designs considering power/performance/yield 82