VLSI Design I. Defect Mechanisms and Fault Models

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1 VLSI Design I Defect Mechanisms and Fault Models He s dead Jim... Overview Defects Fault models Goal: You know the difference between design and fabrication defects. You know sources of defects and you can estimate yield. You can handle fault models at different abstraction levels. MicroLab, VLSI-19 (1/32)

2 Design Defects Design? Specification it helps to have a specification to compare against! if specification is written in a hardware description language from which the design is synthesized then the design should be defect-free free (modulo bugs in the synthesis software!) Of course the specification may be buggy... everyone feels better if the design/specification are run in the environment in which they will be used. For example, in testing a processor chip, one might boot the operating system and run some key programs, all under simulation. This leads to the need for lots of simulation cycles, e.g., as provided by a hardware emulation system.. Now-a-days these are built using a small army of FPGA s. Other choices: in-circuit emulation, cycle-based simulators. MicroLab, VLSI-19 (2/32)

3 Manufacturing Defects Goal: verify every gate is operating as expected Defects from misalignment, dust and other particles, stacking faults, pinholes in dielectrics, mask scratches & dirt, thickness variations layer-to to-layer shorts, discontinuous wires ( opens ), circuit sensitivities (V TH, L CHANNEL ). Find during wafer probe. Defects from scratching in handling, damage during bonding to lead frame, manufacturing defects undetected during wafer probe (particularly speed-related problems). Find during testing of packaged parts. Defects from damage during board insertion (thermal, ESD), infant mortality (manufacturing defects that show up after a few hours of use). Also noise problems, susceptibility to latch-up... Find during testing/burn-in of boards. Defects that only appear after months or years of use (metal migration, oxide damage during manufacture, impurities). Found by customer (oops!). Cost of replacing defective component increases by an order of magnitude with each stage of manufacture. MicroLab, VLSI-19 (3/32)

4 Production defects in CMOS circuits a lot of complex processing steps are used to manufacture a chip -> defects defects and their effect depend on circuit topology and process knowledge of chemical and physical mechanisms who lead to defects are essential circuit complexity and surface determine testability and yield testability and yield are key factors for future VLSI technologies MicroLab, VLSI-19 (4/32)

5 VLSI fabrication process fabrication process consists of a sequence of well defined process steps 50 wafers form a batch each wafer contains 100's or 1000's of chips specific test chips are distributed on the wafers test chips allow to monitor process parameters between a set of process steps the test structures are measured process control parameters geometrical chip's structurs measure conditions tolerances controlling layout tolerances wafer for futher processing process steps monitor steps disturbances wafer not futher processed environment changing MicroLab, VLSI-19 (5/32)

6 VLSI fabrication process (con t) chip fabrication tests: process parameters oxide thickness, distances of structures, etc electrical parameters currents, resistances, threshold voltages,... chip test on wafer packaged chip test controlling layout disturbances wafer fabrication parameter measuring of test-chips bonding packaging parameter and function test of packaged chips measuring of process parameters parameter and function test of chips on wafer MicroLab, VLSI-19 (6/32)

7 VLSI fabrication process (con t) parameter test test of electrical parameters: current consumption, quiescent currents, voltage levels, delay times, etc. function test test for logical faults: binary test sequences are applied to the device under test (DUT) MicroLab, VLSI-19 (7/32)

8 Defect classification defects occur at different fabrication steps: defects at wafer fabrication defects at chip packaging defects during chip lifetime MicroLab, VLSI-19 (8/32)

9 Defects at wafer fabrication 50% of all defects reason: changes in fabrication environment substrate inhomogenities inhomogenities,, mask misalignment dust particles, photolithography defects local or global effects electrical effects depend on layout topology changes in delay, current consumption shorts, opens MicroLab, VLSI-19 (9/32)

10 Defect at chip packaging reasons: bonding problems mechanical stress effect: normally occur at primary inputs or outputs easy to detect MicroLab, VLSI-19 (10/32)

11 Defects during lifetime time dependant mechanisms lead to defects early defects: high defect rate (burn-in) middle life phase: low defect rate wear defects: defect rate climbs with time defect rate early defects middle life phase wear defects time MicroLab, VLSI-19 (11/32)

12 Yield modeling defects can produce faults yield is percentage of fault free chips yield influences chip cost yield models are necessary to predict chip cost local defects produce most faults assumption: local defects are statistically independent and occur with probability p binominal distribution Pr{K=k} = Pr{k from n areas are faulty} due to Bernoulli n n k k Pr{ K = k} = ( 1 p) p k with n to infinity and p to zero k λ λ Pr{ K = k} = e k! ( ) np = λ we find MicroLab, VLSI-19 (12/32)

13 Yield modeling (con t) expectation value E { } K = = k 0 ke λ = λ probability that a chip is fault free Pr Murphy normalized density function f(d) AD Y = e 0 (for low yield) f(d) 1/D 0 1/(2 D 0) Y DA { K = 0} = e = 0 f 2 e AD f 1 f ( D)dD calculation of yield with Murphy's density function f(d) Y 2 Y 1, Y 2, Y 3? (for high yield) 1 e = AD AD Seed's yield model D 0 2D 0 f 3 MicroLab, VLSI-19 (13/32)

14 Yield modeling (con t) the bigger the circuit the higher the probability for a faulty chip example: 2 wafers with the same 17 defects wafer with total 44 chips yield 61% wafer with total 316 chips yield 95% MicroLab, VLSI-19 (14/32)

15 VLSI fabrication process: conclusion defects occur during wafer fabrication, chip packaging and during chip lifetime local and global defects local defects dominate at mature process local defects are hard to find and costly MicroLab, VLSI-19 (15/32)

16 Fault models for integrated circuits complex circuits need more test time test time with expensive equipment leads to high test cost per chip to reduce test time fault models for structured test approaches are required if a system behaves not as expected, faults are present faults can be modeled at different electrical levels faults can be caused by defects they occur during fabrication or life time design errors produce design-faults for example faulty logic implementation of functions design validation is necessary MicroLab, VLSI-19 (16/32)

17 Fault models: Testing approaches Plan: supply a set of test vectors that specify an input or output value for every pin on every cycle. Tester will load the program into the pin cards, run it and report any discrepancies between an observed output value and the expected value XXXX LLLL LLLL HLHL input to chip = {0, 1} output from chip = {L, H} tri-state/no compare = { X } cycle # program for 11 pins How many vectors do we need? n combinational logic n m combinational logic m 2 n inputs required to exhaustively test circuit If n=50, m=25, 1ns/test then test time > 10 6 years 2 n+m inputs required to exhaustively test circuit Exhaustive testing is not only impractical, it s not necessary! Instead we only need to verify that no faults are present which may take many fewer vectors. MicroLab, VLSI-19 (17/32)

18 Fault models: abstraction level circuits are treated at different abstraction levels analog or memory circuits are treated at transistor level medium size digital circuits are treated at logic level complex digital circuits or microprocessors are normally treated at functional level example of fault manifestation: missing polysilicon material layout level: ex. missing polysilicon electrical level: ex. open interconnection transistor level: ex. permanently short-circuited transistor (if missing polysilicon gate) logic level: ex. permanent logic level "1" functional level: ex. register not resetable... MicroLab, VLSI-19 (18/32)

19 Fault models (con t) fault dependencies faults are layout dependent fault are technology dependent goals of fault models fault models should be realistic and thus depend on physical defect mechanisms fault models should be simple and treatable MicroLab, VLSI-19 (19/32)

20 Hard to detect faults transient (intermittent) faults occur only from time to time due to environment changing no satisfactory strategy to search them repeating search built-in in test: self-checking circuits, error-correcting correcting- circuits redundant use of several identical circuit-blocks benefits of redundant circuits redundancy for higher functionality security redundancy to eliminate hazards disadvantages of redundant circuits faults not detectable (masking effect) MicroLab, VLSI-19 (20/32)

21 Logic level fault models historical perspective Eldred proposed 1959 methods how to test computers with relays, diodes, tubes, which behaved like switches stimulation of development of fault models on logic level stuck-at fault model signal can be stuck at "0" or "1" independent of process technology does not model technology dependant characteristics mathematical calculus exists very useful for TTL technology (or other old "current" technologies, but not for "charge" technologies like CMOS) MicroLab, VLSI-19 (21/32)

22 Logic level fault models (con t) Traditional model, first developed for board-level tests, assumes that a node gets stuck at a 0 or 1, presumably by shorting to GND or V DD. DD stuck at 0 = S-A-0 = node@0 stuck at 1 = S-A-1 = node@1 ABC D X Z = ABCD Z B@1 = ACD Z B@0 = 0 B@0 example of TTL NAND gate with many defects describable with stuck-at fault model R 1 R 2 R 4 I 1 I 2 T 1 T 2 R 3 T 4 T 3 O MicroLab, VLSI-19 (22/32)

23 Fault reduction fault collapsing fault equivalence fault dominance single faults, multiple faults fault detection fault free function: f(x) with fault α: f α (x) test vectors x detect fault, if condition is fulfilled: f x f x = ( ) ( ) 1 α fault equivalence f β x = fα fault dominance T ( ) ( x) β T γ fault β dominates γ A B A B fault classes 0 0 α/1 <=> β/1 <=> γ/1 0 1 β/0 => γ/0 1 0 α/0 => γ/0 1 1 γ/0 C α/1 A stuck-at-1 <=> equivalence => dominance MicroLab, VLSI-19 (23/32)

24 Logic level fault models fault dominance T α represents test vector set to detect fault α fault α dominates fault γ under condition T α T γ for test generation only tests for fault α are necessary multiple faults: fault masking problems MicroLab, VLSI-19 (24/32)

25 Transistor level fault models introduced due to imperfection of logic level fault models, especially for CMOS technology dependant and thus more realistic more complex to handle and thus not useful for large circuits transistor level fault models: Wadsack's model Hayes' switch level model Reddy's restrictions due to static discharge robust test sets MicroLab, VLSI-19 (25/32)

26 Transistor level fault models (con t) Wadsack's fault models for CMOS: defects can lead to memory effects faulty combinational logic may behave like sequential logic this effect was modeled by introducing flip-flop's flop's in order to use stuck-at models stuck stuck-at syndrome! A B asop bsop fault free stuck-at stuck-open vddsop A B Y α/0 β/0 γ/0 a b vdd Y MicroLab, VLSI-19 (26/32)

27 Functional level fault models VLSI circuits need simple fault models goal of test: it is sometimes sufficient to know if a sub-function works correctly model of functional faults of sub-circuit each sub-function has its own process dependent faults advantage: fast simulation short test time process dependent good knowledge on important sub-functions (ex. RAM's) disadvantage less accurate not useful for all sub-functions MicroLab, VLSI-19 (27/32)

28 Functional level fault models: example example of CMOS multiplexer with n inputs: behavior under faults: an other input is selected one of the n inputs has a stuck-at fault two inputs are selected (AND or OR result at output) if the complementary value arrives at a selected input, an error occurs at the output if the complementary value of the selected input arrives at a neighbor of the selected input, an error occurs at the output S 0 S 1 S 2 A 0 A 1 A 2 A 3 A 4 A 5 A 6 A to to 1 1 MUX MUX Y MicroLab, VLSI-19 (28/32)

29 Fault models summary fault models are used to model the effects of fabrication defects on abstract levels fault models allow to search directly for circuit defects fault models need to be simple and precise CMOS defects are bad modeled with stuck-at fault model MicroLab, VLSI-19 (29/32)

30 Coming Up... Next topic Test pattern generation and fault simulation Readings for next time Weste: reading 7 through MicroLab, VLSI-19 (30/32)

31 Exercises: VLSI-19 #1 Ex vlsi19.1 (difficulty: easy): Calculate the yield of a circuit of area 5 mm 2 and 1 cm 2 if the defect rate D is 2 defects per cm 2. Result: Y 5mm2 =0.91 (high yield), Y 1cm2 =0.24 (low yield equation), see vlsi-19/13 Ex vlsi19.2 (difficulty: easy): Discuss the circuits function with the introduction of the stuck-open fault F x=open. Can this fault be modeled by a stuck-at fault? C A A B D B C X D F = (A+C)(B+D) X=OPEN = F X=OPEN MicroLab, VLSI-19 (31/32)

32 Exercises: VLSI-19 #2 Ex vlsi19.3 (difficulty: easy): Result: Y 5mm2 =0.91 (high yield), Y 1cm2 =0.24 (low yield equation), see vlsi-19/13 Ex vlsi19.4 (difficulty: easy): Discuss faults due to defects at the TTL nand gate on transparency 22. What kind of stuck-at fault do you have if a) R 1 is an open circuit, b)open at I 1, c) open in R 2 Result: a) O s-a-1, b) I 1 s-a-1, c) O s-a-1 MicroLab, VLSI-19 (32/32)

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