VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects

Transcription

1 VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects Smruti R. Sarangi, Brian Greskamp, Radu Teodorescu, Jun Nakano, Abhishekh Tiwarii and Josep Torrellas University of Illinois at Urbana-Champaign

2 Parameter Variation Parameter Variation P V T Process Supply Voltage Temperature Threshold Voltage: V t Effective Gate Length: L eff 2

3 Process Variation is a Problem Variation of V t and L eff: Chip leakage power Chip frequency 3

4 Chip Frequency Decreases of Logic Paths of Logic Paths Timing errors Number Delay T nom Number T nom Delay T var Distribution of path delays in pipe stage: No variation Distribution of path delays in pipe stage: With variation 4

5 Implications on Design Decisions Unlikely designs will be for worst-case par. values Chips too slow or too costly to design Performance of a generation lost Alternative: design closer to avg. par values Some parts of the chip will be too slow: can we live with timing errors? Some parts of the chip will dissipate too much power: can we push it to other parts of the chip? Multi-tiered solution required: circuits, CAD, microarchitecture, software this talk focuses on μarch. 5

6 Variation components die-to-die within die systematic random spatial correlation 6

7 Modeling Process Variation Process Variation (Not to Scale) Systematic Variation Random Variation Lens aberrations Mask deformities Thickness variation in CMP Photo-lithographic effects Variable dopant density Line edge roughness 7

8 Systematic Variation We divide the chip into a grid of points Each point has one random value of ΔPsys Multivariate normal distribution (μsys, σsys) Characterized by a correlation function: Px r Correlation is position independent and isotropic For ρ(r) we choose the spherical model Random: modeled analytically at transistor granularity Py 8

9 Spherical Model Stronger correlation Weaker correlation Px P Py r Px r Py Matches measured data [Friedberg et al. 05] 9

10 Modeling Systematic Variation Multivariate normal distribution with Spherical Spatial Correlation (μ, σ, Φ) Break into a million cells Example variation map 10

11 Paths in a Pipeline Stage Density df) robability D unction (pd Pr Fu t T nom Timing errors T var Path Delay Err ror Rate (P PE) f var f 1 Frequency f nom Cummulati ive Distrib. Fun nction (cdf f) 1 pdf(t) cdf (t) T nom T var Path Delay Error rate: P E (t) = 1 cdf(t) 1 cdf 1 T nom T var Path Delay 11

12 Error-rate rate vs Frequency Error Rate (PE E) Frequency f var f nom 12

13 Basic Kinds of Structures Logic Memory ALUs, comparators, sense-amps Path delays: heterogeneous SRAMs, CAMs Path delays: homogenous Mixed Renamer, wakeup/select x% memory and (100-x)% logic 13

14 Logic Sample Path 35% Wiring 65% Logic Elmore Delay Model T g Alpha Power Law LeffVDD μ ( T )( VDD Vth ) α 14

15 Logic Delay Distribution of path delays no variation D varlogic = (d wire + η* d gate )* D logic d wire + d gate = 1 wire gate +d gate *D extra Distribution of path delays with variation Relative gate delay due to systematic variation in P,V, T Delay due to random variation Obtain D logic using a timing analysis tool 15

16 Memory Delay WL T mem 1 I Icell Solve for I cell using long channel eqns. I cell = f(vt X,Vt Y,L X,L Y ) Vt X,Vt Y,L X and L Y are gaussian variables I cell X Y V DD BL BR μ vtx, μ vty, μ lx, μ ly are the systematic components σ vtx, σ vty, σ lx, σ ly are the random components 16

17 Memory Delay - II Find a distribution for T mem T mem is a function of four gaussian variables Model T mem as a normal distribution Find the μ and σ for T mem using multi-variable Taylor expansion This is the access time dist. for 1 bit A typical entry has bits Find the max distribution of normal variables Error probability = 1 cdf(t mem ) 17

18 Memory Delay Memory Cell Memory Line Delay dist. Use Kirchoff s equations Long channel trans. equations Multi-variable Taylor expansion max. distribution Delay line = max(delay cell ) 18

19 Combined Error Model We have the delay distributions For each structure per access, P(E) = 1 cdf(t) P(E) per inst = αp(e), α=accesses/inst. Combined error rate per instruction P(E) total = Σ αp(e) CPI penalty per instruction recovery_penalty * P(E) total 19

20 Validation Logic 20

21 Validation Memory 21

22 Finding out the Distributions Using a timing analysis tool ity y Densi pdf) bability nction (p Prob Fun Adding our variation model Path Delay T nom T var 22

23 Adding Up all Pipe Stages Whole processor a + b Er rror Rate (PE) Frequency Er rror Rate (PE) b a f var f nom Frequency P ( f ) = ( αi P ( f E i Ei )) 23

24 Overview Model for Process Variation Model for Timing Errors due to Process Variation Techniques to Tolerate Timing Errors 24

25 Variation Aware Timing Speculation (VATS) Multicore Chip Checker Processor Core Diva Checker L0 Cache Razor Latches L1 Cache 25

26 Performance vs Frequency Perf ( f ) = CPI f CPI comp + stall _ mem + CPI rec P (f) x recovery_penalty E Erro or Rate (P E ) Perf Per rforman nce (Per rf) f opt Frequency 26

27 AMD Athlon-like like Processor 27

28 Conclusion Micro-architects can help solve par variation Cores that assume faults occur all the time Frequency / Power / Error rate are tradeable Techniques to mitigate variation-induced errors Develop models that give insights Work with circuits, CAD, and software folks 28