PHYSICAL ANALYSIS AND DESIGN OF NANOSCALE FLOATING-BODY DRAM CELLS. By ZHICHAO LU

Transcription

1 PHYSICAL ANALYSIS AND DESIGN OF NANOSCALE FLOATING-BODY DRAM CELLS By ZHICHAO LU A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA

2 2010 Zhichao Lu 2

3 To my parents 3

4 ACKNOWLEDGEMENTS This thesis is a collection of my five "memory" years at Gainesville. It is not only my research work, but also advice, encouragement, guidance and unrelenting support from Professor Jerry G. Fossum who served as my advisor during the past five "memory" years. I have my most sincere gratitude to him. His insights, enthusiasm, approaches to problems, and being a role model as a researcher and as a person will set the highest standards that I will be aspiring to always. I would also like to extend my sincere gratitude to the members of my supervisory committee (Professors Robert Fox, Jing Guo, Scott E. Thompson, Amlan Biswas and Art Hebard) for their guidance and willing service. I would like to thank my mentor at IMEC, Dr. Malgorzata Jurczak, for her insightful perspective on research and encouragement. I would like to express my gratitude to my colleagues, Dr. Nadine Collaert and Marc Aoulaiche, for their technical disscusions and friendships. I am grateful to the Freescale Semiconductor Inc., Samsung Electronics and SEMATECH for their technical and financial support. Especially, I thank Dr. Rusty Harris and Dr. Ji-Woon Yang at SEMATECH for providing silicon devices for measurements. I would also like to thank my fellow students, Murshed M. Chowdhury, Weimin Zhang, Seung-Hwan Kim, Vishal Trivedi, Shishir Agrawal, Siddharth Chouksey, Zhenming Zhou, Dabraj Sarkar for their insightful and technical discussions and friendships. I must say I am fortunate to have known all the friends here who have encouraged and cheered me up throughout all the years. Especially, I thank Dr. Weimin Zhang for helping a lot when I first came to Gainesville. 4

5 I would like to thank to my lovely girlfriend Mei Zhao. I am really grateful for her companionship and for her being so kind and supportive. Meeting her could be one of the most wonderful things when I was in Gainesville. This work would not have been possible without the unyielding support of my parents. I am deeply indebted to them for their love and support. 5

6 TABLE OF CONTENTS ACKNOWLEDGEMENTS...4 LIST OF TABLES...8 LIST OF FIGURES...9 LIST OF ABBREVIATIONS...11 ABSTRACT...13 CHAPTER 1 INTRODUCTION page 1.1 Scaling Difficulties with Conventional DRAM Cell Capacitorless DRAM New Physical Insights on "Capacitorless" DRAM Cell TWO-TRANSISTOR FLOATING-BODY/GATE CELL: A NOVEL LOW-POWER NANOSCALE EMBEDDED DRAM CELL Introduction Two-Transistor Floating-Body Cell Concept Performance Evaluation of the Floating-Body/Gate Cell Summary "P + SOURCE" FLOATING-BODY/GATE CELL: A MANUFACTURABLE NANOSCALE EMBEDDED DRAM CELL Introduction "P + Source" Floating-Body/Gate Cell Concept Operation and Performance of the "P + Source" Floating-Body/Gate Cell Experimental Demonstration of the "P + Source" Floating-Body/ Gate Cell Summary PHYSICAL INSIGHTS AND MODELING OF GATE-INDUCED DRAIN LEAKAGE CURRENT IN FLOATING-BODY CELL Introduction Non-Quasi-Static Hole Redistribution and Its Effect on Gate-Induced Drain Leakage Current Body-Bias Dependence of Gate-Induced Drain Leakage Current Model Development for Body Bias-Dependent Gate-Induced Drain Leakage 6

7 Current Summary FLOATING-BODY/GATE CELLS UPGRADED FOR ULTRA-LONG RETENTION TIME AND ULTRA-FAST WRITE TIME Introduction Floating- Body/Gate Cell Upgraded for Ultra Long Retention Time Floating-Body/Gate Cell Upgraded for Ultra Fast Write Time Comparison of the Floating-Body DRAM Cells Summary SUMMARY AND SUGGESTIONS FOR FUTURE WORK Summary Suggestions for Future Work LIST OF REFERENCES BIOGRAPHICAL SKETCH

8 LIST OF TABLES Table page 2-1 Charging/discharging-current comparison between the FBGC and 1T FBCs Performance comparison among the FBGC3, FBGC4 and 1T FBCs

9 LIST OF FIGURES Figure page 1-1 Predicted operation (with I Gi body charging) of the IG-FinFET FBC Predicted hole density along the back surface Sketch of the perturbation of the energy-band diagram The 2T floating-body cell (FBC) in a DRAM array Schematic cross-sectional view of a 2T (n-channel) FBC fabricated UFDG/Spice3-predicted transient sequential operation of a 2T FBC Transient sequential operation of a 2T FBC The FBGC structure in a DRAM array Transient sequential memory operation of an FBGC as depicted in Fig UFDG/Spice3-predicted transient sequential memory operation of a 2T FBGC UFDG/Spice3-predicted transient sequential memory operation of the 2T FBGC Worst-case data retention/disturb characteristics of the 2T FBGC in Fig UFDG/Spice3-predicted BL2 read-voltage and T2 read-current The simplified FBGC structure, on SOI, in a DRAM array with two bit lines Transient sequential memory operation of the new FBGC structure Cross-section TEM of the FinFET structure used for both T1 and T Measured current-voltage characteristics of the p + p - n + gated diode Measured current-voltage characteristicsof the double-gate nfinfet Circuit configuration of the measurement setup Measured transient sequential write/hold/read operations for 1 and Measured transient sequential write/hold/read operations for 1 and Drain current-gate voltage characteristics of T1 and holes distribution

10 4-2 Measured dependence of the GIDL current on the body voltage Cross section of gated diode Band diagram at the overlap region along the vertical direction Band diagram along the vertical direction with accumulation and depletion The FBGC3 structure, on SOI, in a DRAM array with two bit lines SenTaurus-predicted BTB tunneling current in T BTBT currents with different G-D underlap predicted by SenTaurus I D -V D characteristics of T1 predicted by SenTaurus I D -V G characteristics of T2 predicted by SenTaurus Transient sequential memory operation of a FBGC3 cell Worst-case charge/data retention characteristics of the FBGC Transient sequential memory operation of the FBGC3 with BL1 and BL2 tie together Transient sequential memory operation of the FBGC3 with optimal pulses Transient sequential memory operation of the FBGC3 with no spacer of T Data retention characteristics of FBGC Sense margin, I D of T2, and max. number of cells vs. gate work-function of T The FBGC4 structure in a DRAM array with two BLs Transient sequential memory operation of a FBGC4 cell

11 LIST OF ABBREVIATIONS 1T FBC 2T FBC BJT BTBT CMOS DG DIBL DOS DRAM FB FBC one-transistor floating-body cell two-transistor floating-body cell bipolar junction transistor band to band tunnelling complementary metal-oxide-semiconductor double-gate drain-induced barrier lowering density of states dynamic random access memory floating body floating-body cell FBGC1 floating body/gate cell Ver. 1 FBGC2 floating body/gate cell Ver. 2 FBGC3 floating body/gate cell Ver. 3 FBGC4 floating body/gate cell Ver. 4 FD FET GIDL ITFET LOP LSTP MOSFET nfet fully depleted field-effect transistor gate-induced drain leakage FinFET-based inverted-t FET low operating power low standby power metal-oxide-semiconductor field-effect transistor n-type field-effect transistor 11

12 nfinfet nitfet nmosfet PD pfet pmosfet SCE SG SOI SRAM SOC UFDG UFPDB UTB n-type FinFET n-type ITFET n-type MOSFET partially depleted p-type field-effect transistor p-type MOSFET short-channel effect single gate silicon-on-insulator static random access memory system-on-chip University of Florida double-gate (MOSFET model) University of Florida partially depleted SOI and bulk (MOSFET model) ultra-thin body 12

13 Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy PHYSICAL ANALYSIS AND DESIGN OF NANOSCALE FLOATING-BODY DRAM CELLS Chair: Jerry G. Fossum Major: Electrical and Computer Engineering By Zhichao Lu December 2010 This dissertation addresses physical analysis and design issues of nanoscale floatingbody cells (FBC), which are also known as capacitorless dynamic random-access memory (DRAM) cells. A novel two-transistor floating-body/gate cell (FBGC), and upgraded versions of it, are proposed and experimentally demonstrated. As the conventional one-transistor and one-capacitor (1T/1C) DRAM technology is aggressively scaled, novel device structures and materials have to be introduced to meet International Technology Roadmap for Semiconductors (ITRS) performance requirements. Novel device structures and materials bring a lot of processing and integration challenges to current complementary metal-oxide-semiconductor (CMOS) technology. To avoid these challenges, capacitorless DRAM, which is based on silicon-on-insulator (SOI) CMOS including partially depleted (PD) and fully depleted (FD) MOS transistors (MOSFETs), is attracting a lot of interest. This technology, which uses the floating body of the SOI MOSFET as the storage element, can potentially replace the conventional 1T/1C DRAM cell in the near future. The basic working principle of the FBC is to utilize the floating-body effect inherent in the PD/SOI MOSFET; the FD/SOI MOSFET also shows the floating-body effect when the substrate, or back gate is biased for accumulation. However, the physical explanation of the floating-body effect in the FD/SOI device is not clear. Based on 13

14 numerical simulations, physical insights are gained on the effect and on FBC performance, e.g., the sense margin. Relying on the physical insights of the floating-body effects, a novel two- transistor (2T) FBC is proposed. By using the first transistor s (T1) body to directly drive the second transistor s gate, the 2T FBC eliminates the body-factor limitation on the sense margin. The memory performance is demonstrated with the University of Florida physics-based compact double-gate MOSFET model (UFDG). The predicted results show that the common impact ionization-based write method produces too much power dissipation. To resolve this problem, the 2T-FBC is refined to Ver. 1 of the floating-body/gate cell (FBGC1). The major feature of FBGC1 is the source tied source to the drain in T1. To improve the manufacturability of FBGC1, Ver. 2 (FBGC2) is proposed, which in essence is a gated diode (T1) plus a conventional transistor (T2). Gate-induced drain leakage (GIDL) current is used to write 1 in FBGC2. The performance is demonstrated by 90nm FinFET technology and also by numerical simulation. One issue with FBGC2 is the short retention time with bit-line (BL) disturbs. Hence Ver. 3 (FBGC3) is proposed to the resolve this problem. Unlike FBGC2 which accumulates the channel to get GIDL charging current, FBGC3 inverts the channel and introduces tunneling current at the source side for charging, thereby separating the charging mechanisms for write and hold. By optimizing the device structure, FBGC3 demonstrates ~10s retention time with worst-case disturb. To make FBGC3 operate faster, Ver. 4 (FBGC4) is proposed. In FBGC4, T1 reverts back to a normal transistor. However, special designs are made at the source side; n + and p + regions are used to tie the source to the body. The performance, with ~100ps write/read times, is analyzed by the University of Florida physics-based compact SOI MOSFET model (UFPDB). 14

15 CHAPTER 1 INTRODUCTION 1.1 Scaling Difficulties with Conventional DRAM Cell The conventional dynamic random access memory (DRAM) cell, which consists of one transistor and one capacitor (1T/1C), has been the workhorse memory cell in the high-density memory arena for more than three decades [1]-[2]. With the innovations in DRAM structures, and utilization of new materials, the conventional 1T/1C DRAM cell is evolving to the 60nm technology node and 4Gb capacity [3]-[6]. Scaling the DRAM cell to sub-60nm technology nodes, as demanded by high-density storage and low bit cost, is very challenging. Scaling issues are directly related to the requirement of storing a critical amount of charge on the capacitor for a certain time. To guarantee proper DRAM cell operation, the sensing signal should be larger than sensing noise to ensure the correct sensing in the noise environment. Generally, the requirements of the access transistor and the storage capacitance can be summarized as follows [5][7][8]: C s V DD mV, (1.1) C s + C BL 2 C s 25 ff/cell, (1.2) I on a few µa/cell, (1.3) I off few fa/cell, (1.4) 15

16 where C S is the storage capacitance, C BL is the bit-line (BL) parasitic capacitance (the typical value is 75fF for one bit line [9]), and V DD is the supply voltage. With regard to the scalability of the access transistor, maintaining relatively high threshold voltage (V t ), e.g., 1V, is an effective way to get less than a fa/cell leakage current and several µa/cell oncurrent simultaneously. So-called Localized Asymmetric Channel Doping (L-ASC) [10] and Recessed Channel Array Transistor (RCAT) [11] are the two approaches that were proposed to solve this problem. L-ASC can eliminate the junction leakage current at the storage node by decreasing the doping concentration only at the storage node while maintaining the V t. RCAT can significantly suppress short-channel effects (SCEs) by increasing the effective channel length without area penalty due to its recessed-channel geometry structure. Beyond 50nm technology node, a body-tied bulk FinFET or a vertical surrouded-gate transistor could be utilized due to their excellent immunity of SCEs, relatively low junction leakage (undoped body), and high transconductance. But, the disadvantage of these approaches is less compatibility to the conventional planar CMOS logic technology. These approaches inevitably require extra fabrication steps which increase the cost of fabrication [12]. Compared with the scalability issues of the access transistor, the scaling difficulties with the storage capacitors are more serious and ambiguous. Since the DRAM storage area becomes physically smaller with scaling, the effective oxide thickness (EOT) must scale down sharply to maintain non-scalable storage capacitance (~25fF/Cell). This will lead to extraordinary large aspect ratio for trench capacitors or larger cell size in stacked capacitors. Moreover, dielectric thickness cannot be reduced excessively because of concern over high tunneling leakage current. High-k material, such as H f SiO, Al 2 O 3, ZrO 2, or Ta 2 O 5 [13], with new capacitor structure, such as Metal-Insulator-Metal [13], could be 16

17 ways to resolve this problem. Many efforts have been made to investigate these new materials and structures. But, these methods involve challenges in low-temperature processing, good adhersion/deposition properties, and sufficiently low tunneling leakage current [14]. In addition, these new materials and structures are not compatible with the conventional CMOS technology and will increase the bit cost [14]. These unresolved problems with the 1T/1C DRAM cell have lead to uncertainty in industry over how far conventional 1T/1C DRAM technology can go. 1.2 Capacitorless DRAM To overcome the difficulties in scaling the conventional 1T/1C DRAM cell, 1T capacitorless DRAM [15]-[17] has been proposed. The capacitorless DRAM cell, which is simply a MOSFET with a floating body, i.e., a floating-body cell (FBC), offers several advantages: (1) no complex capacitor integration technology, which implies better scalability beyond 50nm technology node; (2) full compatibility of memory and logic technology, and 4F 2 cell area; and (3) better electrical performance, such as low power dissipation, high speed, and better sense margin. Initially, there was considerable interest in the FBC based on the partially depleted (PD) SOI MOSFET [18] [19], and on the bulk-si MOSFET [20]. Recently, the interest moved to fully depleted (FD) SOI MOSFETs [21]-[23] and FD double-gate (DG) FinFETs [24]-[26], which have more potential scalability. For the FD (n-channel) cells, it is pervasively acknowledged [22][25]-[28] that a hole accumulation layer must be induced by substrate or back-gate bias (V GbS ) to form a deep potential well for hole storage, as thought to exist naturally in the PD cell [17][23]. The published descriptions of the capacitorless FBC operation based on the notion of a potential well, and the cell-design 17

18 implications of it, are inadequate and misleading. Later in this chapter, using numerical device simulations and analytical modeling, we physically overview the basic operation of the FBC, clarify the misleading "hole well" concept and revealing new insights that could lead to optimal cell design. The advanced CMOS technology, e.g. FinFET technology, could enable scaling of the 1T FBC to gate lengths (L g ) less than 10nm [27][29]-[31]. The basic current-signal margin of the 1T FBC, defined by the threshold-voltage difference corresponding to the body-voltage (V BS ) variation due to body charging/discharging, is fundamentally restricted: V t =-r V BS where the body factor r ~ 0.3 [32] when SCEs are controlled. This restriction, and other issues, e.g. sophisticated current sensing circuits [33], have led to our conception of a 2T FBC, in which the floating charged/discharged body of one transistor (T1) directly drives the gate of a second transistor (T2), thereby removing the r-factor restriction in the signal margin. In Chapter 2, we first present a novel 2T-FBC concept, and then demonstrate a new 2T-FBC configuration, which in essence is a floating-body/gate cell (FBGC) [34]. That yields dramatic reduction in power dissipation, in addition to better signal margin, comparable data retention time, and higher density. The simulations done in Chapter 2 demonstrate that floating-body/gate DRAM cell (FBGC) which we call Ver. 1 (FBGC1), on SOI [34][35], can potentially yield better signal margin, less power dissipation, and higher effective density than all other 1T floatingbody DRAM cells (FBCs). However, an issue with FBGC1 is the process integration for tying the body of T1 to the gate of T2, which undermines cell area and memory density [35]. We address this issue in Chapter 3, where we propose a simplified, easily manufacturable version of the FBGC, the so-called "P + Source" FBGC [36], or Ver. 2 (FBGC2), which is 18

19 compatible with conventional, planar SOI and DG-FinFET CMOS technology with ~8F 2 cell area. In essence, the simplified "P + source" FBGC is a gated diode connected to the gate of a conventional MOSFET through the P + region. Numerical simulations and measurements of a fabricated prototype of the new cell demonstrate the basic memory concept, and also imply significant performance superiority over the 1T FBCs as well as the original version of the FBGC in Chapter 2. Since the writing scenarios in FBGC [35] [negative gate (word line) voltage is used to write 1, and positive gate voltage is used to write 0 ] are different from the conventional impact ionization-based write methods, the holding conditions under disturb become complicated. Word-line (WL) disturb should be carefully taken care of in both 1 - state and 0 -state holding. In Chapters 2 and 3, we reveal two facts: (1) 0 state under disturb is more tenuous than 1 state under disturb; (2) GIDL current in the holding conditions is the major killer of the 0 retention time. Even though we get longer 0 retention time under disturb with the "P + Source" FBGC (FBGC2), we find that the absolute value of retention time is still much shorter than the 64ms as required by ITRS [7]. We also find that the non-quasi-static hole redistribution is significant in the memory transient operation. In Chapter 4, we seek to gain physical insights of the transient GIDL current due to the non-quasi-static effect and body-bias dependence of GIDL current, which will determine the worst-case 0 -state retention time. Based on our physical insights, we develop an analytical GIDL current model and use it to predict the 0 -state retention time with the "P + Source" FBGC. With better understanding of the dependence of transient GIDL current on V B gained in Chapter 4, we propose to modify the design, and optimize the performance of the "P + Source" FBGC (FBGC2), including acceptable retention time. We address the key issue 19

20 for FBCs using GIDL current for charging, i.e., the current ratio corresponding to the charging operation and the 0 holding state with disturb. This ratio must be very large to achieve 100ms retention time with reasonable write time and sense margin. We investigate two new FBGC design modifications to get the desired performance in Chapter 5. To resolve the shorter worst-case retention time problem, Ver. 3 (FBGC3) is proposed and demonstrated with numerical simulations. Then, exploiting the design flexibility which is offered by the 2T FBGC cell, we upgrade FBGC3 to Ver. 4 (FBGC4) for faster speed. Besides maintaining the excellent retention time characteristics in FBGC3, FBGC4 can improve write speed, including write 1 and 0, to less than 1ns. These characteristics mean FBGC4 could be a good candidate to replace the cache memory cell in CMOS logicchip design. 1.3 New Physical Insights on "Capacitorless"DRAM Cell Basic FBC Operation As noted, the integration problems associated with the capacitor of the conventional DRAM cell in nanoscale CMOS technology have stimulated the research interest in capacitorless DRAM cells. The binary states of the 1T floating-body cells (FBCs) are defined by charging and discharging the body of an SOI MOSFET. The stored data is sensed via a difference, or signal margin, in the channel current (I DS ) corresponding to the V t variation that results from the body charging/discharging, i.e., from the varying bodysource junction voltage (V BS, the quasi-fermi potential separation) [22][37]. The charging (e.g., by impact-ionization current I Gi ) and discharging (e.g., by body-drain (B-D) junction forward bias V BD ) of the (n-channel with grounded source) FBC are defined by the floating- 20

21 body nodal, or (hole) current-continuity equation, which involves discernible intrinsic, dynamic capacitors: I G I R dq dv p BS = = C dt B dt (1.5) where C B represents the composite body capacitance that couples the body to other terminals of the MOSFET; Q p is the hole charge in the body, and I R (generally defined by the B-S/D p-n junctions [38]) and I G are hole recombination (removal) and generation (injection) currents linked to the body. In the PD/SOI cell (with thick BOX) during charging by I G =I Gi, for example, C B comprises the B-S/D junction capacitances defined by the body doping density (N B ) [38]. Generally, the V BS -dependent B-S capacitance is predominant, including both depletion and diffusion components [37][38]. However, if I G is GIDL current [23], with the front surface accumulated, C B is augmented by the body-gate capacitance, or ~CoxWgLg. During write- 1 charging (dq p /dt > 0), C B in (1.5) governs a transient increase in V BS ( V BS ) related to Q p : Q p = Q p0 + Q p = Q p0 + C B dv BS V BS (1.6) where Qp is the injected, stored hole charge associated with V BS as defined by C B ;Q p0 is defined by N B for PD cells (it is the mentioned V GbS -induced accumulation charge for FD cells). For I Gi charging, the transient can reach steady state, where I Gi = I R (V BS ) defines V BS (which is typically about 0.7V); for GIDL charging, V BS < 0, making I R = 0 (for no gate current), and the steady state is not typically reached [23]. During write- 0 discharging (dqp/dt < 0), I G = 0 and I R can be defined by V BS > 0 as well as V BD > 0; the transient is 21

22 thus relatively fast, yielding V BS ~ 0 (<0 when V DS < 0 is applied for faster discharging) in the steady state. Note that during the I G = I Gi charging transient, the gate, or word-line voltage (V GfS ) is raised to induce a channel, and the drain, or bit-line voltage (V DS ) is raised to drive I DS and I Gi. Thus, excessive power is consumed as has been generally noted; use of GIDL for I G, without a channel, dramatically reduces this power [23]. However, during the discharging transient, with V GfS > 0 and V DS < 0 as typically used, the write- 0 power dissipated by the MOSFET in the inverse mode can be excessive too, and this is not generally noted. For FD FBCs, with very low N B, C B in (1) is not so clearly defined; a depleted body renders very small B-S/D junction capacitance. For the FD/SOI MOSFET with thick BOX, the body substrate capacitance is very small too, and there is no significant holestorage element. (Note that using GIDL for I G in this case, which would require G-S/D overlap, could make C B the oxide capacitance as noted above.) For I G =I Gi charging then, (1.5) and (1.6) show that the steady-state V BS is reached very quickly, but with virtually no Q p. However, we note that if the substrate is biased negatively to induce strong hole accumulation charge (Q p0 ) near the body-box interface, as typically done [21][22][27], large B-S/D junction capacitance is created within the accumulation layer. Indeed, this capacitance emulates that of the p + -n + junction [38] in the PD/SOI cell, and is typically the predominant component of C B. For the FD DG FinFET, the substrate can be biased to form the accumulation layer [25] and create C B in the same way. However, if the two gates are made independent (IG) [26], the back gate can be biased instead [Okh05][Ban06]. For the IG FinFET though, we wonder whether such bias is really needed for C B ; could the thin back oxide (t oxb = t oxf ~ 2nm) yield an adequate B-Gb capacitance without any V GbS -induced accumulation? 22

23 We answer this question later, but irrespective of C B, we note that the V GbS - induced accumulation is still needed for two other reasons. First, the Q p -defined data in the cell cannot be sensed without it because V t is not dependent on V BS. Indeed, without strong accumulation charge, Poissons equation in the FD body shows that the Gf-Gb coupling defines V t (V GbS ), and there is no significant V t dependence on V BS [39]. We show later that this need persists even though an accumulation layer tends to form as I Gi (or GIDL) injects holes ( Q p ) into the body and V BS increases. Second, the V GbS -induced accumulation charge increases the stored- 0 V t to V ta (via dv t /dv GbS = -r d ~ -C b C oxb / [C oxf (C b +C oxb )] for depletion [39], where C b = ε Si /t Si,C oxf = ε ox /t oxf, and C oxb = ε ox /t oxb ) such that the V BS -defined lowering of it [22], V ta = r a V BS (1.7) for accumulation, where r a = C b /C oxf ~ 3t oxf /t Si, yields a stored- 1 V t that is sufficiently lower than the stored- 0 V t for data (current) sensing. Without the V GbS -induced accumulation, the 0 -state V t =V t (V GbS ) is low, and, even though the stored 1 -state Q p creates an accumulation layer, the 0 versus 1 V t margin is prohibitively small, as we now show Simulations and Discussion We demonstrate our new insights regarding the general operation of FBCs via 2- D numerical device simulations done with Taurus [40]. We present here results of simulating the FBC operation of an FD IG FinFET, illustrated in the inset of Fig The FinFET has a 28nm gate length, with t oxf =t oxb = 2nm, undoped fin-body with thickness t Si = 14nm, and midgap gates; the default fin height, or gate width, is 1µm. In Fig. 1.1 we show 23

24 predicted I DS (t), defined by V t (t), reflecting the transient sequential operation of the cell (i.e., write 1 (charge body by I Gi ), hold data, read 1, hold data, write 0 (discharge body with V DS < 0), hold data, and read 0 as depicted in the figure) for two cases: V GbS = -1.0V, which induces a back-surface accumulation layer, and V GbS = 0V, which leaves the unbiased body fully depleted. For the first case, the predicted FBC operation is normal, albeit with a small signal margin ( I DS as defined by V ta in (3)) that typifies FBCs since r a < 1. The stored data, sensed via I DS, reflects the charging/ discharging of C B, i.e., Q p (t) as indicated by the predicted hole densities in Fig Note here that C B includes the accumulation-defined B-S junction capacitance, as in the FD/SOI FBC, plus the B-Gb capacitance (~C oxb W g L g ), which is comparable to the junction capacitance. Note also the excessive power was implied by I DS during the write- 0 as well as the write- 1 operations. However, for the V GbS = 0V case in Fig. 1.1, note that I DS (t) does not reflect any stored data, in accord with our discussion above, and the transients are very fast, implying much less Q p stored on the B-Gb capacitance. The predicted hole densities in Fig. 1.2 confirm the small, but finite Q p. Since the write- 1 I DS for this case implies a relatively high I Gi,we infer, from (1), an effectively low C B even though t oxb is thin. These results can be explained with reference to the back-surface energy-band diagrams sketched, in accord with the simulation results, in Fig. 1-3, for this case and for the V GbS = -1.0V case. In the latter case, the valence band E v is pinned to the hole quasi-fermi level E Fp via the high hole density, and hence the back-surface potential varies as φ sb = V BS, yielding (3) [22][39]. However, for the V GbS = 0 case, φ sb ~ 0. This is because the inversion electron density that exists in the body (bulk inversion is prevalent in undoped MOSFETs [41]) during write 1 nearly pins the conduction band E c to the electron quasi-fermi level E Fn as V BS [=(E Fn -E Fp )/q] increases. Only when the injected hole density (which defines Q p ) becomes the 24

25 predominant carrier near the back surface of the body does E v begin to follow E Fp, thus increasing φ sb and lowering V t accordingly [22][39]. However, at this point VBS is already near its final, 1 -state value, and so Q p ~ C oxb φ sb is small and V t ~ Summary Using numerical simulations and analytical modeling, we physically and generically explained the operation of FBC DRAM, comprising a PD/SOI or FD/SOI MOSFET, or an FD DG or IG FinFET. The notion of a potential well for charge storage in the body was dismissed, and, for the first time, the predominant intrinsic, dynamic capacitors (bias-dependent C B ) that store the body charge, or data, for the various devices and bias conditions were defined. For FD cells, multiple roles of the V GbS -induced accumulation layer needed for storing and sensing data was physically defined for the first time; it renders a significant V t dependent on V BS, and, in the FD/SOI cell with thick BOX, it creates a significant B-S junction capacitance for the charge storage. For the IG- FinFET cell, the created junction capacitance is augmented by the B-Gb capacitance. For GIDL charging [23], rather than by I Gi,C B is augmented by the B-Gf capacitance. The new insights noted herein imply better designs for optimally trading-off the FBC signal margin ( I DS defined by V ta in (1.7)), data retention time, write speeds, and power. All the noted metrics depend on C B, which has been clearly defined with reference to (1.5) and (1.6) for the various FBC devices and biases. Indeed, a dynamic C B could be optimally tailored by device design. For example, use of GIDL for body charging, which reduces power [23], also makes C B in (1.5) for write 1 different from that for read 1, as we have indicated. During the write- 1 operation, V BS < 0 [23], making I R = 0 in (1.5) and thus increasing Q p for a given write time, irrespective of C B(write). The larger Q p implies longer retention time 25

26 directly, and could also yield improved margin via V BS = Q p /C B(read) in the read- 1 operation; C B(read) is the B-S junction capacitance, dependent on V BS > 0. Also, note from (1.7) that, for a given V BS, V ta can be increased by decreasing t Si or increasing t oxf, but only the former change increases the signal margin, as experimentally shown in [27] and [28], since I DS ~ C oxf V ta ~ 1/t Si. 26

27 Word Line Bit Line V Gb =-1.0V V Gb =0.0V Voltage (V) Write 1 Hold Read 1 Hold Write 0 Hold Read V Gb =-1.0V V Gb =0.0V I DS (µa/µm) Gf (word line) t oxf -150 S n + p - t (body) n + Si D (bit line) -200 t oxb Gb (back gate) Time (ns) Figure 1-1. Predicted operation (with I Gi body charging) of the IG-FinFET FBC with V Gb = -1.0V and V Gb = 0V. The transient pulsings of the word line and bit line of the cell are shown in the top plot, and the transient cell currents, which reflect the stored data, are also shown in the plot, the inset of which illustrates the basic structure of the DG-MOSFET FBC. 27

28 10 21 Hole Density (cm -3 ) Read 1, V Gb =-1.0V Read 0, V Gb =-1.0V Read 1, V Gb =0.0V Read 0, V Gb =0.0V 10 5 Source Channel Drain Position (nm) Figure 1-2. Predicted hole density along the back surface between source and drain of the IGFinFET FBC at the ends of the read- 1 and read- 0 transient operations, for V Gb = -1.0V and V Gb = 0V. For the former case, the hole density reflects (Q p0 + Q p ), while it reflects only Q p for the latter case. Note that Q p is much larger for V Gb = -1.0V than it is for V Gb = 0V. 28

29 E c S qv BS E Fn E Fp q φ sb E v B V GbS = -1.0V S qv BS E Fn E Fp E c q φ sb B V GbS = 0V E v Figure 1-3. Sketch of the perturbation of the energy-band diagram across the bodysource junction at the back surface of the IG-FinFET FBC caused by V BS > 0 associated with write- 1 (via I Gi ) Q p, for V Gb = -1.0V and V Gb = 0V. For the latter case, the surface potential is hardly changed by V BS since E Fp is not pinned to E v as it is for the V GbS = -1.0V. 29

30 CHAPTER 2 TWO-TRANSISTOR FLOATING-BODY/GATE CELL: A NOVEL LOW-POWER NANOSCALE EMBEDDED DRAM CELL 2.1 Introduction The conventional DRAM cell requires a stack capacitor or a deep-trench capacitor for storage, which is leading to prohibitive processing complexity as the memory technology is scaled [1]. So, study and development of "capacitorless" one-transistor (1T) DRAM cells that utilize the floating body of an SOI MOSFET as the storage element have intensified [17][21][22][28][42], mainly for CMOS embedded-memory applications [43]. In such 1T floating-body cells (FBCs), charging (by impact-ionization or GIDL [23] current) and discharging (by forward-biased drain/source-junction current) the MOSFET body define the memory states, and the stored data are sensed via a difference, or signal margin, in the channel current ( I DS ) corresponding to the threshold-voltage variation ( V t ) that results from the body charging/discharging, i.e., from the varying body-source junction voltage (V BS ) [44]. The widespread FBC studies, which began with partially depleted (PD) SOI MOSFETs [17], have recently focused on fully depleted (FD) devices, including planar FD/SOI MOSFETs [21][27][45] and FD double-gate (DG) FinFETs [26][28][46], to avoid body-doping issues [26] and to render the FBC more scalable with the CMOS. The FD devices require a substrate, or back-gate bias to create an accumulation layer that emulates the PD body, and enables effective charge storage and data sensing as explained in Chapter 1 [44]. While FinFET CMOS technology could enable scaling of the 1T FBC to gate lengths (L g ) less than 10nm [29], there are other issues that will tend to inhibit mainstream adaptation of the 1T-DRAM concept: (i) it relies on current-based sensing of the stored data, 30

31 which is less desirable than conventional voltage-based sensing because of varying I DS, and hence more complex sensing circuitry [33], and added power consumption; (ii) it requires the noted bias-induced accumulation, which complicates the cell/chip design, undermines reliability, and sacrifices layout area; and (iii) because the attainable V t is fundamentally limited, wide devices, or several paralleled fins, are needed to increase the current to get acceptable I DS, thus undermining the memory density actually achievable. For example, in [46], with the SOI substrate biased at -30V to get the needed accumulation, 10 fins yielded a current margin of less that 10µA from an L g = 100nm composite n-channel DG FinFET. In this chapter we propose and demonstrate, via process/physics-based device/ circuit simulations supported by numerical simulations, a novel two-transistor (2T) FBC [34] for embedded-dram applications that can yield much better performance with higher density than the 1T cells. The 2T concept is conceived from an insightful understanding of the basic FBC operation [44], which in fact belies its "capacitorless" description. Further, a modification in the 2T-FBC structure enabled by use of GIDL current for body charging, which in essence creates a floating-body/gate cell (FBGC) [34], is shown to yield dramatic reduction in discharging as well as charging [23] power dissipation, in addition to better signal margin, higher memory density, and longer data retention. Design and processing issues that need to be addressed for optimal performance and for sustained FBGC viability in nanoscale CMOS are discussed. 31

32 2.2 Two-Transistor Floating-Body Cell Concept Transient Simulation Our 2T-FBC [34] idea stems from insights into the actual operation of the 1T FBC [44]. First, we note that the variation in V t that underlies the 1T-FBC operation is typically much less than the variation in V BS driven by the body charging/discharging: V t =-r V BS with the body factor r ~ 0.3 [32]. This means that wide devices, and large layout areas are needed for adequate I DS, as mentioned previously. Second, we note that the commonly used "potential well" description [21][22][24] of the body charge storage is misleading. The FBC is not really "capacitorless"; it can actually have more than one intrinsic capacitor (C Bi ) supporting the charge (Q p in an nmosfet) storage [32]: dq p dv Bi I G I R = = C dt Bi i dt (2.1) is the floating-body nodal equation, where C Bi, with i = S, D, Gf, Gb, represents the capacitive coupling of the body to other terminals of the transistor; Q p is the majority-hole charge in the body, and I G and I R are hole generation (or injection) and recombination (or extraction) currents. Third, as noted above, voltage-based sensing is not an option for the 1T FBC. A memory array based on the 2T FBC is illustrated in Fig The cell comprises transistors T1 and T2, with the body (B1) of T1 connected to, or driving the gate (G2) of T2; C bi in (1) is thus augmented by the gate capacitance of T2. The 2T concept is generic, applicable to any SOI technology. However, FinFETs offer the best scalability, and the 2Tcell structure could be fabricated, without area penalty due to the B1-G2 contact, via the DG FinFET-based ITFET technology [44][47] as illustrated in Fig The planar SOI layer, 32

33 doped p +, would be used to make the B1-G2 connection of two n-channel DG FinFETs. The FinFET bodies should be left undoped for scalability [44]. Lateral diffusion of the p-type dopants in the SOI layer during activation would effectively dope the base of the T1 fin, thereby suppressing source-drain leakage current in it. The undoped FinFETs should have near-midgap metal gates, and p + rather than n + polysilicon must be used in the gate stack to enable the B1-G2 connection. As noted in the figure caption, we estimate a unit-cell area of 13.75F 2, which implies that the potential area per signal margin is much smaller than that of a 1T counterpart cell because of the larger margin afforded by the 2T FBC, which we exemplify later, and the need for a wide device, or multiple fins [28][46], in the 1T FBC as noted previously. Alternatively, a stacked 2T structure, with T2 made in polysilicon (as we justify later) is possible. The write/erase operations of the 2T FBC are done by charging/discharging the floating body of T1, as in the 1T FBC. But, the stored data are read via T2 with V GS2 = V BS1 > V t, which implies directly a (1/r)x increase in I, or about a 2x (1/2r) memorydensity increase for the same current-signal margin. No substrate biasing is needed, even when the transistors are designed to be FD, like DG FinFETs which we focus on here. However, two bit lines (per string) are needed: one (BL1) connecting all drain nodes of the T1 transistors in a column of the DRAM array for programing the cells, and the other (BL2) connecting all drain nodes of the T2 transistors in the column for sensing the data. As we discuss later, two bit lines will tend to improve data-retention time, as well as ameliorate read-error issues. The gate of T1 is tied to a word line (WL). The stored data are read by, in essence, driving T2 directly with V BS of T1 (R V B1/G2 with S2 grounded). Data could therefore be sensed via the induced drain-current variation (g m V B1/G2 ) in T2, as in the 1T FBC cells but with much better signal margin 33

34 because V B1G2 > V t as noted. However, preferred voltage-based sensing at the (precharged) drain node of T2 (BL2), similar to the sensing used in the conventional DRAM technology, can be used. In this case, the 2T-FBC cell has to be designed such that T2 will be turned on and off by the charged/discharged T1 body in the 0 and 1 states, respectively. (Note that since T2 inverts, stored 0 and 1 correspond to the T1 body being charged and discharged, respectively.) For voltage-based sensing, the two FinFETs can be designed with only one fin each, implying much less layout area than a FinFET-based 1T FBC [28][46] with multiple fins. We now simulate the basic operation of the FinFET-based 2T FBC using our process/physics-based compact model UFDG [48] in Spice3. UFDG is charge-based, and hence properly accounts for all important transcapacitances, ensuring charge conservation, and is well-suited for dynamic FBC simulation. The I R and I G modeling in UFDG, including impact-ionization current (I Gi ) and GIDL current, is also physical. Note for the T1 body of the 2T FBC that a predominant charging current on the right-hand side of (1) is defined by the gate capacitance of T2: C G2 (dv B1/G2 /dt) where, in general, C G2 is V B1/G2 -dependent. We assume single-fin L g = 28nm DG nfinfets for T1 and T2, with undoped fin-body width and height of 14nm and 56nm, respectively, midgap metal gate, and 1nm gate oxide. (We neglect gate tunneling current and parasitic capacitance for this preliminary demonstration.) We further assume an ideal B1-G2 connection, and the body of T2 is left floating like B1. The UFDG/Spice3-predicted operation [i.e., write 0 (charge T1 body), hold data/precharge BL2, read 0, hold data, write 1 (discharge T1 body), hold data/precharge BL2, and read 1 ], for I Gi charging of B1, is shown in Fig. 2-3; as indicated, we assumed reasonable read/ write times of 10ns including pulse rise/fall times of 1ns. The UFDG model predicts the expected trend of the B1/G2-voltage variation with gate (WL) and drain (BL1) biasing, as 34

35 shown. A typical program window (or V B1/G2 signal margin) of 0.8V is predicted, as indicated by the difference of V B1/G2 between the read- 0 and read- 1 operations. Note that appropriate WL pulsing (to 0.1V here) for read operations is needed to move V B1/G2 sufficiently above or below V t of T2 for stored 0 or 1, respectively, with adequate Q p storage needed for the former. This operation is confirmed by the predicted transient drain (BL2) voltage of T2, which needs to be precharged before reading (to 1.0V here). Indeed, with the T1 body charged (stored 0 ), BL2 drops quickly to 0V, as V B1/G2 turns on T2; this corresponds to a read 0. With the T1 body discharged (stored 1 ), BL2 remains at its precharged value (1.0V) as V B1/G2 remains well below V t ; this corresponds to a read 1. Efficient reads of both 0 and 1 are demonstrated with reasonable WL and BL1 voltage pulsings. Of course there is some uncertainty in the assumed (defaulted) physical model parameters in UFDG, e.g., those defining I G (including I Gi ) and I R. However, this uncertainty should not undermine our demonstration of the basic functionality of the 2T FBC in Fig We do, however, have some concern about the assumed ideal B1-G2 connection and the notion that the floating body of T1 can effectively drive the gate of T2. Thus, for more definitive corroboration, we do a numerical mixed-mode simulation a 2T- FBC structure using Taurus [40]. To allow a 2-D simulation, we define a domain with two 28nm single-gate undoped FD/SOI nmosfets, linked by a p + polysilicon-tin (with midgap work function) connect as shown in the inset of Fig Further, to facilitate the mixed-mode simulation, we simply set V DS of T2 to 0.1V and monitor its current (I DS2 )to check the functionality of the cell. Although the assumed 2T structure is simplified, the simulation results, shown in Fig. 4 for I Gi charging of T1, do corroborate the general operation of the 2T FBC as predicted by UFDG/Spice3. Indeed, the results demonstrate the 35

36 basic operation of the cell with nanosecond-scale write/read processes, showing that the floating B1 of T1 can effectively drive G2 of T2 and yield outstanding signal margin. The margin of the cell, reflected by the predicted I DS2 (t), is substantively larger than that of the 1T counterpart [32], even though it is undermined some because of the unexpected finite read- 1 current. This current is due to the significant Q p stored on the forward-biased B-D junction of T1 during the write- 1 (discharge) process, which is supported by substantive I Gi with T1 in the inverse mode. This undermining of the current-signal margin will occur in any FBC unless the WL voltage is kept well below the MOSFET threshold voltage and/ or the BL voltage is kept near zero during the discharging process. Data retention of the 2T FBC, subject to BL1 and WL disturbs, is expected to be at least comparable to that of the 1T cell, as exemplified for FinFET-based FBCs in [46] and [30]. But, the enabled use of voltage-based sensing instead of current-based sensing can yield better retention in the 2T-FBC array, as we show and explain later. 2.3 Performance Evaluation of the Floating-Body/Gate Cell Operation Simulations Clearly, the 2T FBC affords much more design flexibility for optimizing performance than does the 1T FBC. A good example is the FBGC [35] (Ver. 1), which stemmed from our checking the use of GIDL current for body charging [23] to eliminate the substantive write- 0 (B1-charging) power loss due to T1 channel current, which can be inferred in Figs. 2.3 and 2.4. Note, in fact, that such power loss occurs in the write- 1 (discharging) operation as well. Fordischarging, a forward bias is established on the body-drain junction by V DS < 0 and V GS > V t, and thus high channel current flows in the inverse mode [32]. The body-charging power can be virtually eliminated by using GIDL current [23], rather than 36

37 impact-ionization current, for charging, but the body-discharging power remains high. A key feature of the FBGC is the drain (BL1) of T1 tied to the source, as illustrated in Fig This 2T configuration, with T1 effecting a floating body/gate on T2, totally eliminates T1 channel current, and thus the excessive power dissipation when the body of T1 is discharged. Further, with GIDLcurrent charging, it eliminates the undermined signal margin due to I Gi noted with reference to Fig. 2-4 as well. The FBGC has other advantages. All drain-source leakage currents in T1 are eliminated, meaning reduced standby power. Also, T1 can be designed primarily for GIDL current, i.e., with significant gate-source/drain overlap and L eff < L g, without much consideration of short-channel effects since it is not crucial in the read operations. This is not true for 1T FBCs using GIDL-current charging, for which the shorter L eff will tend to limit L g scalability. And, with T1 now being just a two-terminal (WL and BL1) device, the fabrication process could be simplified, e.g., by using a stacked structure as mentioned previously. We verify and demonstrate the operation of the 2T FBGC, first by numerical simulations using Taurus. The 2-D structural domain used is similar to that in Fig. 2-4, with 28nm FD/SOI transistors. The predicted results for a sequential memory operation, with T2 current used for sensing data, are shown in Fig. 2-6, including the floating-b1/g2 voltage transient, which is V GS (t) applied to T2 (but not now V BS of T1 since S1 is not grounded). The results confirm the basic operation of the FBGC cell based on GIDL-current charging of T1, showing an outstanding signal margin that is about 2.5x higher than that achieved in a 1T FBC counterpart in [23] with the same drain bias (0.2V). Note the negligible write-power dissipation reflected by the transient current in T1, void of any channel current. The B1-discharging current is about four orders-of-magnitude lower than what is typical in 1T FBCs [17]. The charging/discharging-current comparison of the FBGC versus the 1T FBCs in [17] and [23] 37

38 made in Table 2-1 clearly reflects the superiority of the FBGC with regard to power consumption.the 2T FBGC also enables data sensing via the BL2 voltage, for which V B1/ G2 (t) must swing through V t of T2 and the stored charge in B1 must be high enough to image an adequate inversion charge in T2. The latter requirement is dependent on the noted nonquasi-static effect (It will be revisted in chapter 4.), which enables the oxide capacitance of T1, as well as the gate capacitance of T2, to augment C Bi of (1) in the body of T1 [32]. To demonstrate this operation with realistic FinFETs, and to check the data retention/disturb characteristics with reasonable computational efficiency, we use UFDG/Spice3. (UFDG is a quasi-static model, but the noted NQS effect has been accounted for in the GIDL-current modeling.) We assume undoped 28nm single-fin DG nfinfets with a midgap gate. To avoid significant gate tunneling current as well as reduce parasitic gate-source/drain capacitance, a pragmatic gate oxide thickness (t ox ) of 2nm is assumed. The fin width is set to 14nm for SCE control [29], and the height is set to a reasonable 56nm. A 1.5nm G-S/D overlap in T1 is assumed for reasonable GIDL current, and a 3nm underlap [49] in T2 is used to further reduce the parasitic (fringe) capacitance [50]. Such 2T-FBGC design is doable using the previously noted ITFET structure [47]. The predicted operation is shown in Fig Note that the write- 0 WL and BL1 voltage pulses (needed for GIDL current) are high, but the oxide electric field, dependent on t ox, gate-silicon work-function differences, surface potentials, and V B1/G2, is not too excessive anywhere. The memory operation here is more efficient than that in Fig. 2-6 mainly because of the upgraded T2 design. Note that, with BL2 precharged to 0.5V, the fast BL2 voltage transient, going to 0V or 0.5V, faithfully reflects the stored data directly in this case. This solid voltage-signal margin implies higher FBGC memory density, since wide (e.g., multi-fin) devices must be used in the 1T cell for adequate current margin [46]. 38

39 To demonstrate the benefit of the noted T2-design upgrade, we simulated the FBGC operation again, but with T2 identical to T1. In this case, T2, with the G-S/D overlap, has much higher parasitic capacitance, including increased G-S/D fringe capacitance [49] as well as the added overlap capacitance. The UFDG/Spice3-predicted B1/G2 and BL2 voltage transients are contrasted in Fig. 2-8 with those of Fig Although now the added parasitic capacitance of T2 must be charged during the write- 0 process, the larger oxide capacitance of T1, where the predominant Q p is stored, still controls the V B1/G2 charging transient. However, the subsequent read- 0 efficacy is clearly undermined. The WL pulse does not bring V B1/G2 up as much because of the added parasitic capacitance of T2, thereby yielding slower read time. The write/read- 1 (discharging) processes are not significantly affected by the added capacitance. However, the 0-1 signal margin in V B1/G2 is reduced substantially by the noted read- 0 effect, which portends shortened retention time as well. A BL2 capacitance of 20fF, which is a reasonable estimate for a 512-cell BL string in the 28nm-FinFET technology, was assumed for the simulations of Fig In this regard, we have checked the simulation results for possible read errors due to channelleakage currents in unselected cells in the BL string. Looking at the predicted transient currents in the selected and unselected cells, we estimate that ~1000 cells would be needed to cause an error, although that number is reduced when T2 is not optimally designed to minimize the parasitic capacitance, and the V B1/G2 margin is reduced as in Fig These checks also imply reasonable standby power associated with unselected cells, partly because the read and write operations are done via separate bit lines and the source and drain of T1 are tied (to BL1). 39

40 2.3.2 Data Retention/Disturb Characteristics Simulations The data retention/disturb characteristics of the 2T FBGC, governed by GIDL and I R currents in T1, are better than those of the counterpart 1T FBC [23] due to the undoped body, and can be improved by design optimization enabled by the 2T structure. Also, as we mentioned previously, when GIDL current is used for charging, the gate capacitance of T1 augments C Bi in (1), tending to increase the stored- 0 charge and lengthen the retention time. For the FBGC of Fig. 2-7, UFDG/Spice3 predictions of read-v B1/G2 (t) resulting from worst-case, long-time WL and BL1 disturbs to hold 1 and hold 0 are shown in Fig For comparison, the read-v B1/G2 (t) for long-time holds without disturbs is included; these results imply ~1s retention times. The undermining hold- 1 (with B1 discharged) disturbs result in GIDL-current charging of B1, and the undermining hold- 0 (with B1 charged) disturbs result in drain/source-junction I R discharging of B1. The retention times are implied by V B1/G2 (t) relative to V t of T2, which is indicated in the figure. We note that this V t could be tailored to optimize the tradeoff between data-retention times and read/write performance. The worst cases (holding 0 with BL1 disturb and holding 1 with WL disturb) show ~1ms retention times, much longer than the 100ms in [23]. To exemplify the retention time directly, we show in Fig. 2-10, the sensed BL2 voltage versus time corresponding to the worst-case BL1 hold- 0 disturb, contrasted with the sensed T2 current versus time corresponding to the same disturb. These UFDG/Spice3 predictions give interesting insights regarding data retention for voltage- versus current-based sensing. Note the dramatic increase in the retention time afforded by (one-fin) voltage-based sensing versus current-based sensing. The latter time is about an order-of magnitude shorter, reflecting why multi-fin devices are needed for current-based sensing. In this case, the relative loss of the current margin directly tracks the change in V B1/G2 relative to V t of T2 40

41 in Fig However, for voltage-based sensing, the loss of the relative voltage margin depends on the current-voltage characteristics of T2, as well as the BL2 capacitance, and good T2 design with typical capacitance yields a much longer retention time. 2.4 Summary A novel 2T floating-body cell on SOI for embedded-dram was presented, and its operation was demonstrated and verified via process/physics-based device/circuit simulations, supported by numerical simulations. The main novelty is the use of the floating body of one transistor (T1) to directly drive the gate of the second transistor (T2), thereby giving dramatic improvement in signal margin while allowing voltage-based sensing. Physical insight then led to a modification (FBGC [35]) of the basic 2T-FBC structure, enabled by using GIDL current for T1-body charging, in which the source and drain of T1 are shorted, and both tied to the programming bit line (BL1). The FBGC, which is virtually a floating-body/gate cell, totally eliminates the write (T1 charging and discharging)-power dissipation, while yielding better signal margin, longer data retention via voltage-based sensing, and higher memory density. The simulation-based demonstration of the FBGC used undoped nanoscale DG FinFETs, or ITFETs [49], which are potentially scalable to L g < 10nm [49]. We therefore believe that FBGC DRAM is similarly scalable, and much more so than a 1T counterpart for which the gate-source/drain overlap (L eff < L g ) needed for GIDL current will limit its scalability. Because of the design flexibility afforded by the 2T FBGC, the GIDL current can be controlled via optimal design of the G-S/D overlap in T1, which is merely a two-terminal charge-storage structure, with T2 being designed optimally with underlap as discussed herein. We note that scaling L g will tend to reduce the effective storage capacitance of the 2T cell, i.e., the oxide and gate 41

42 capacitances of T1 and T2 which augment the right-hand side of (1) for T1 (although the fin height could be kept high to offset this reduction without undermining the increased memory density). Thus, less Q p will be stored, although the signal margin will not be undermined. However, the scaling of the fin thickness with L g will reduce the S/D-junction I R and I G, implying that the data retention time will not be significantly affected. Hence, we believe that FBGC DRAM can be scaled along with the FinFET-CMOS technology. This optimistic projection cannot be made for 1T-FBC DRAM, even if a DG FinFET is used. 42

43 2T FBC T1 B1/G2 T2 Word Line Bit Line 1 Bit Line 2 (Ground) Figure 2-1. The 2T FBC (T1 and T2 enclosed in the dashed square) in a DRAM array, where B1/G2 represents the floating-body storage node of T1 that is tied to the gate of T2. The 2T-FBC concept is applicable to any SOI technology. 43

44 Metal 3 Metal 2 GND GND BL1 (D1) BL2 (D2) Metal 1 WL T1 T2 Silicide p + Poly TiN Nitride Oxide Silicon p + P BOX Substrate Figure 2-2. Schematic cross-sectional view of a 2T (n-channel) FBC fabricated via ITFET technology [47]. The planar SOI layer, doped p +, provides the contact from the (undoped) body of DG FinFET T1 to the (p + poly/metal) gate of DG FinFET T2, without area penalty. The WL, BL1, BL2, and GND metal vias are indicated, as is the pitch (P = 2F) of the technology node. Lateral diffusion of dopants from the SOI layer to the base of the T1 fin stops any source-drain leakage current there. For L g F/2 (for which t fin L g /2 and h fin 4t Si [29]), we estimate a unit (two-fin) cell area of <14F 2, which implies a potential area per margin much less than that of a 1T counterpart FBC [18]. 44

45 1.5 BL1 1.0 B1/G2 BL2 g ( ) WL Write 0 Write 1 (Charge B1) Read 0 (Discharge B1) Read 1 Hold Hold Hold Time (ns) Figure 2-3. UFDG/Spice3-predicted transient sequential operation of a 28nm DG nfinfet-based 2T FBC comprising single-fin transistors with height 56nm; impact-ionization current was used for charging B1, and gate current and parasitic capacitance were neglected. For the read operations, BL2 was precharged to 1.0V; the effective bit-line capacitance was assumed to be 20fF, which corresponds roughly to a 512-bit line in the technology alluded to. Note that V B1/G2 is V BS of T1 and V GS of T2. 45

46 BL1 (a) Voltage (V) WL BL2 (b) I DS2 (µa/µm) Hold Hold Hold Write 0 Read 0 Write 1 Read T1 n + T2 n + TiN p - p + TiN n + p - n + Word Line Bit Line 1 (0.1V) Bit Line 2 Figure Hold Hold Hold Write 0 Read 0 Write 1 Read Time (ns) Transient sequential operation of a 2T FBC, analogous to the simulation of Fig. 2-3, predicted by a 2-D, mixed-mode simulation using Taurus. The assumed representative cell structure, with 28nm single-gate FD/ SOI nmosfets, is shown in the inset of (b), in which the data storage is reflected by the transient current in T2 driven by V BS of T1. The transient pulsings of the gate (WL) and drain (BL1) of T1, and the T2 drain (BL2) voltage fixed at 0.1V for this simplified simulation are shown in (a). The read- 1 and read- 0 operations show the predicted signal margin, I DS2 40µA/µm. 46

47 T1 WL T2 B1/G2 GND BL1 BL2 Figure 2-5. The FBGC structure in a DRAM array. The gate of T2 is driven by the body of T1. The source and drain of T1 are tied together, thereby eliminating T1-channel and source-drain leakage current, and effecting a floating body/gate on T2. 47

48 (a) Figure 2-6. (b) Voltage (V) Current (µa/µm) Write 0 Hold Read 0 Hold Write 1 Hold Read 1 BL1 B1/G2 BL2 WL T1 Current T2 Current negligible write current Write 0 Hold Read 0 Hold Write 1 Hold Read Time (ns) Transient sequential memory operation of an FBGC as depicted in Fig. 2-5 predicted by a 2-D mixed-mode numerical simulation using Taurus with a structural domain similar to that in Fig. 2-4, with 28nm FD/SOI transistors. The applied WL and BL1 voltage pulses, for GIDL-current charging, are shown in (a), along with the predicted floating-b1/g2 voltage (relative to ground) transient (which is V GS of T2) and the BL2 voltage (V DS2 ) set to 0.2V. The T2 current in (b) reflects the basic memory operation, showing a current margin of about 50µA/µm. The T1 current in (b) reflects the negligible power dissipation during the B1 discharging (write 1 ) as well as charging (write 0 ). Signal Margin 50µA/µm 48

49 1.0 BL1 0.5 BL2 Voltage (V) B1/G2-1.0 WL -1.5 Write 0 Read 0 Write 1 Read 1 Hold Hold Hold Time (ns) Figure 2-7. UFDG/Spice3-predicted transient sequential memory operation of a 2T FBGC designed with undoped 28nm DG single-fin nfinfets with height and width of 56nm and 14nm, respectively, and 2nm gate oxide; T2 is designed with 3nm G-S/D underlap, whereas T1 has 1.5nm overlap to enable GIDL-current charging. The applied WL and BL1 voltage pulses are shown, along with the predicted floating B1/G2 (relative to ground) and BL2 voltage transients; the BL2 capacitance was assumed to be 20fF. The voltage-based sensing, via BL2 with a 0.5V precharge, shows a solid signal margin with fast (<10ns) write/read times. 49

50 BL2 0.2 Voltage (V) B1/G2 Heavy Curves: T2 w/ Overlap Light Curves: T2 w/ Underlap -1.0 Write 0 Read 0 Write 1 Read 1 Hold Hold Hold Time (ns) Figure 2-8. UFDG/Spice3-predicted transient sequential memory operation of the 2T FBGC of Fig. 2-7, but with T2 identical to T1, with G-S/D overlap. The predicted B1/G2 and BL2 voltage transients are compared with those of Fig Note the undermined read- 0 operation due to the added parasitic capacitance of T2. 50

51 0.55 V B1/G2 (V) Stored 0 Holding w/o Disturb / Read Holding w/ WL Disturb / Read Holding w/ BL1 Disturb / Read V t of T2 Stored Time (s) Figure 2-9. Worst-case data retention/disturb characteristics of the 2T FBGC in Fig reflected by UFDG/Spice3 predictions of the read-b1/g2 voltage after lengthy data ( 0 and 1 ) holds subject to continuous WL and BL1 disturbs as indicated. The WL and BL1 disturbs are those that undermine the data storage, as given in the in Fig The data holds without the disturbs are included for comparison. The T2 threshold voltage is superimposed to indicate retention times. 51

52 Holding 0 w/ BL1 Disturb / Read BL2 Voltage (V) Voltage Sensing of 0 (BL2 is precharged to 0.5V) Current Sensing of 0 (V DS2 = 0.2V) Time (s) T2 Current (ma/fin) Figure UFDG/Spice3-predicted BL2 read-voltage (after 8ns read time as in Fig. 2-7) and T2 read-current (with V DS2 = 0.2V applied) of the 2T FBGC in Fig. 2-7 after the lengthy worst-case 0 (B1 charged) holds subject to the continuous BL1 disturb (-0.9V) in Fig Note the much longer worst-case retention time (~1ms) yielded by the voltage-based sensing, which is governed by the current-voltage characteristics of T2 as well as the BL2 capacitance (assumed to be 20fF). 52

53 Table 2-1. Charging/discharging-current comparison between the FBGC and 1T FBCs Impact Current (A/µm) FBGC ionization GIDL Charging 1.3x x x10-8 Discharging 1.2x x10-4 >1x

54 CHAPTER 3 "P + SOURCE" FLOATING-BODY/GATE CELL: A MANUFACTURABLE NANOSCALE EMBEDDED DRAM CELL 3.1 Introduction In Chapter 2, we suggested a novel 2T FBC in which the floating charged/ discharged body of one transistor (T1) directly drives the gate of a second transistor (T2), thereby removing the body-factor limitation of the signal margin inherent in 1T DRAM cells [32]. Via simulations, we demonstrated the superior signal margin of the 2T cell relative to the 1T FBCs, and we showed how the power dissipation is reduced dramatically in a floating-body/gate version of the 2T structure (FBGC1). An issue of the FBGC1 is the process integration for tying the body of T1 to the gate of T2, which undermines cell area and memory density. We address this issue in this chapter, proposing a simplified, easily manufacturable version of the FBGC (FBGC2), which is compatible with conventional, planar SOI and DG-FinFET CMOS technology with 8F 2 cell area. Numerical simulations and measurements of a fabricated prototype of the new cell demonstrate the basic memory concept, and also imply significant performance superiority over the 1T FBCs, as well as the FBGC "P + Source" Floating-Body/Gate Cell Concept The new version of the FBGC is illustrated in Fig The distinguishing feature of this simplified cell is the p + region of T1, which replaces the n + source in the original 2T- FBGC structure [35]; T1 is now a gated diode. The p + "source" enables an easy, direct connection of the T1 body to the gate of the T2 MOSFET as indicated in the figure. The cell can thus be easily processed in any SOI technology, using planar or quasi-planar (e.g., 54

55 FinFET) devices (or even in bulk Si with T1 in polysilicon). GIDL tunneling current in T1, controlled by the word line (WL = G1) and the programming bit line (BL1 = D1), is used to charge the floating body/gate (B1/G2), i.e., write a 1. A forward bias on the diode, defined by BL1 and the B1/G2 voltage (V B1/G2 ), is used to discharge B1/G2, i.e., write a 0. The stored data can be sensed via voltage or current from the read bit line (BL2 = D2) tied to T2. For current sensing, the BL2 voltage can be high for increased margin, unlike in 1T cells subject to read-disturbs. In addition to easing the manufacturing of the FBGC, the p + "source" enhances the transient G1-B1 coupling via the fringe/overlap G1-"S1" capacitance, which can be exploited to improve the cell performance as we show. Indeed, the design flexibility afforded by the new FBGC structure distinguishes it from all the 1T DRAM cells, and can yield superior overall performance. 3.3 Operation and Performance of the "P + Source" Floating-Body/Gate Cell We verify and demonstrate the operation of the new FBGC first by numerical simulation using Taurus [40]. The 2-D structural domain used for the (mixed-mode) simulation is what is shown in Fig We assume 28nm FD/SOI nmosfet structures, with T1 being a gated diode as described above. The p + "S1" is tied directly to G2. The assumed gaussian source/drain lateral doping profile defines about a 2nm G-S/D overlap in both devices; the T2 threshold voltage (V t ) is about 0.2V. Predicted results for a transient sequential memory operation are shown in Fig. 3-2, including the floating-b1/g2 voltage transient. The results, with nanosecond-scale write and read times, demonstrate the basic operation of the cell, showing that the floating body of T1 effectively drives the gate of T2 and yields outstanding signal margin. The predicted T2 current margin (220µA/µm for V BL2 55

56 = 0.2V) is more than 4x-larger than what we predicted for the original 28nm FBGC in a similar simulation [35], and more than 10x-larger than that predicted for the 1T-FBC counterpart [23]. We attribute the dramatic increase in the margin to the added WL-B1 capacitive coupling mentioned above, which is especially significant at times when the intrinsic gate capacitance is small during the transient operation of the cell. It results in a larger read 1 - read 0 margin for V B1/G2 (0.75V vs. 0.41V for the original FBGC [35]), which can be optimally positioned relative to V t of T2. The high margin, which can be made even higher via higher V BL2 as noted, implies high effective density (margin per area) for the new FBGC. With the direct B1-G2 connection, the simplified FBGC cell size is 8F 2, which is much smaller than the original FBGC [35] and comparable to the 1T/1C DRAM cell. Further, the predicted write-power is negligible since there is no T1 channel (or BJT [42]) current, unlike in the 1T DRAM cells. 3.4 Experimental Demonstration of the "P + Source" Floating-Body/Gate Cell Discrete DG nfinfets and FinFET-based gated diodes were fabricated at SEMATECH. The devices have undoped, 20nm fin-bodies, TiN gates, and Hf-based high-k dielectric with EOT = 1.3nm, Which is shown in Fig The FinFET gate length (L g ) is 120nm, and that for the p + -p - -n + gated diode is 500nm. Measured current-voltage characteristics of the gated diode, in Fig show adequate GIDL current, with negligible gate tunneling current (even with the long Lg). Measured current-voltage characteristics of the FinFET with a high Vt of almost 0.5V (as for long Lg [51]) is shown in Fig We demonstrate the memory function of the new FBGC using a prototype created by hard- 56

57 wiring B1 of a gated diode to G2 of a FinFET at a probe station. The circuit configurationis shown in Fig The demonstration is thus based on slow transient measurements because of stray capacitance. We first demonstrate the voltage-based sensing enabled by the FBGC; measured results of sequential write/hold/read operations for 1 and 0, which correspond to Fig. 3-2, are shown in Fig The functionality of the new cell is clearly exhibited; the T1 body effectively drives the T2 gate, and the T2 drain (~BL2) voltage transient indicates the stored data with a solid margin set by the supply voltage. Such voltage sensing is perhaps the preferred option for the new FBGC because of longer retention times [33], (which can be generally optimized due to design flexibility afforded by the 2T cell) and lower power, as well as less sophisticated sensing circuitry. Also in Fig. 3-8 we show measured results of a current-sensing operation of the new FBGC prototype. We have used a higher bit-line voltage (V BL2 ) for high margin, enabled by the 2T cell as noted above. The FD body of T2 prevents any read-induced V t shifts, e.g., due to impact ionization-current charging. The results in Fig. 3-8 show a very high signal margin of 340mA/mm, even with the high V t. This is a record current margin, even higher than that reported for the BJT-based FBC [42]. 3.5 Summary We have demonstrated a simplified, superior version of the FBGC, by numerical simulation and fabrication/measurement. The new 2T cell offers very high signal margin and ultra-low power dissipation. Retention times are anticipated to be comparable to, or longer than, those of 1T FBCs. The eased fabrication process of the new 57

58 FBGC makes it compatible with planar or quasi-planar CMOS technology, with high effective density. It can thus enable manufacture of embedded DRAM in the near future, at low cost and with superior performance. 58

59 WL BL1 p + p - n + T1 B1/G2 BL2 n + p - n + T2 Figure 3-1. The simplified FBGC structure, on SOI, in a DRAM array with two bit lines. The p + "source" of T1 (now a gated diode) facilitates the B1-G2 connection in the technology, and it improves the cell performance because of additional WL-B1 capacitive coupling. 59

60 Voltage (V) WL V BL2 = 0.2V Write 1 Hold Read 1 Hold Write 0 Hold Read Time (ns) Figure 3-2. Transient sequential memory operation of the new FBGC structure (FD/ SOI-based with undoped thin bodies, midgap work function (TiN) gates.)in Fig. 3-1 predicted by a 2-D mixed-mode numerical simulation using Taurus. The applied WL and BL1 voltage pulses, for GIDL charging, are shown in (a), along with the predicted floating-b1/g2 voltage transient; the BL2 voltage is set to 0.2V for current sensing. The T2 current in (b) reflects the basic memory operation, showing a signal margin of 220µA/µm. T2 Current (µa/µm) Write 1 Hold Read 1 Hold Write 0 Hold Read 0 BL1 B1/G2 Signal Margin 220µA/µm 60

61 Figure 3-3. Cross-section TEM of the FinFET structure used for both T1 (gated diode) and T2 (standard diffused DG transistor) of the new-fbgc prototype. The fin dimensions are 20nm wide by 80nm tall. The inset is a high-resolution TEM of the gate stack showing the scaled Hf-based dielectric with ALD TiN metal. 61