From Physics to Power, Performance, and Parasitics
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1 From Physics to Power, Performance, and Parasitics The GTS-Team Global TCAD Solutions GmbH, Böserndorferstraße 1/12, 1010 Vienna, Austria O. Baumgartner et al. (GTS) GTS 1 / 25
2 Scales, methods, hierarchies Abstraction level Transistors Description Quantity System level Behavioral Message Register transfer level (HDL) Gate level Signal state 0/1 Transistor level (SPICE) ODE I Classical TCAD 100 PDE (DD) J(x, y, z) Nano TCAD 1 PIDE (SBTE) J n (x, y, z, E) Quantum transport 1 NEGF Atomistic < 1 DFT O. Baumgartner et al. (GTS) GTS 2 / 25
3 Introducing TCAD in design Fab/foundry Designer/customer Process TCAD models Design rules Compact models Characterization PDK Standard cells O. Baumgartner et al. (GTS) GTS 3 / 25
4 Introducing TCAD in design Fab/foundry Designer/customer Process TCAD models Design rules Compact models Characterization incomplete information TCAD models Standard cells Potential benefit: More spot-on designs; fewer, shorter iterations Problem for TCAD in design: Where to start from? No calibrated device models (mobility) No detailed process information O. Baumgartner et al. (GTS) GTS 3 / 25
5 Our solutions Nano-scale TCAD Single-device TCAD Large-scale TCAD Path finding Process to device to cell to circuit variability Design-technology co-optimization (DTCO) O. Baumgartner et al. (GTS) GTS 4 / 25
6 Modules Layout-based structrue generation Rapid prototyping Process-flow awareness Device simulation Steady-state, transient, AC Reliability What about calibration? Parasitics extraction R/C-network topology extraction Self-heating Quasi-transient simulation Thermal network extraction O. Baumgartner et al. (GTS) GTS 5 / 25
7 Layout-based structure generation Layout Technology 3D Cell M2 M1 M0 FEOL BP Technology Layout O. Baumgartner et al. (GTS) GTS 6 / 25
8 Process emulators Voxel-based topographical process emulators Coventor SEMulator3D Synopsys Process Explorer Valuable tools for process exploration and integration Lacking features of a full-fledged process simulator Require detailed knowledge about process Combination with device simulation poses difficulties Voxel-based topography contains step-like surfaces Layer thicknesses? Requires repair procedure May contain artifacts High number of surface points Large mesh size, excessive device simulation times O. Baumgartner et al. (GTS) GTS 7 / 25
9 Process emulators Combination with device simulation poses difficulties Voxel-based topography contains step-like surfaces Layer thicknesses? Requires repair procedure May contain artifacts High number of surface points Large mesh size, excessive device simulation times O. Baumgartner et al. (GTS) GTS 7 / 25
10 Process emulators Combination with device simulation poses difficulties Voxel-based topography contains step-like surfaces Layer thicknesses? Requires repair procedure May contain artifacts High number of surface points Large mesh size, excessive device simulation times O. Baumgartner et al. (GTS) GTS 7 / 25
11 What is Layout-Based Structure Generation? Built on a Constructive Solid Geometry (CSG) kernel Human-readable/writeable script (Tech file) directs CGS kernel based on layout (GDSII file) No process details required Process-flow aware Integrated meshing, high-quality mesh output, no repairs 2 less mesh points than process emulation 5 faster device simulation 100 % successful convergence O. Baumgartner et al. (GTS) GTS 8 / 25
12 Layout-based structure generation FEOL TechX based on IMEC in14 Fin tapering Rounded corners Conformal dielectric layers Realistic epi-shapes Process-flow awareness: Self-aligned processes Doping distribution O. Baumgartner et al. (GTS) GTS 9 / 25
13 Layout-based structure generation BEOL TechX based on IMEC in14 Realistic interconnect geometries Conformal TiN-barriers Cu-fill O. Baumgartner et al. (GTS) GTS 10 / 25
14 Variability: line-edge roughness (LER) GDSII layout Technology description Analytic rounding Lithography effects Imported from GDSII Imported device geometry Imported stress 3D cell Doping Variability Analytic Imported Implant, diffusion, activation LER Mask misalignment O. Baumgartner et al. (GTS) GTS 11 / 25
15 Adding LER to gate lines O. Baumgartner et al. (GTS) GTS 12 / 25
16 Doping with LER closeup O. Baumgartner et al. (GTS) GTS 13 / 25
17 Doping with LER closeup doping follows roughness O. Baumgartner et al. (GTS) GTS 13 / 25
18 Doping with LER closeup doping follows roughness correlated O. Baumgartner et al. (GTS) GTS 13 / 25
19 Adding LER to fin patterning mask (SADP) O. Baumgartner et al. (GTS) GTS 14 / 25
20 Variability: mask misalignment GDSII layout Technology description Analytic rounding Lithography effects Imported from GDSII Imported device geometry Imported stress 3D cell Doping Variability Analytic Imported Implant, diffusion, activation LER Mask misalignment O. Baumgartner et al. (GTS) GTS 15 / 25
21 Mask misalignment R increase C increase O. Baumgartner et al. (GTS) GTS 16 / 25
22 Device simulation steady-state characteristics V DS = 0.6 V V DS = 0.7 V V DS = 0.7 V HP PMOS NMOS LP PMOS NMOS PMOS parasitic channel PMOS NMOS VSS VDD O. Baumgartner et al. (GTS) GTS 17 / 25
23 Transient device simulation power vs. performance V DD =0.8 V V DD =0.5 V FinFET NS NW CFET O. Baumgartner et al. (GTS) GTS 18 / 25
24 Calibration & prediction Hardware Data Performance Predictions with Process and Design Variations NMOS Simulation Measurement FF N14 NW N10 FF N14, FF N10, FF N7 NW N7, NW N5, NW N3 NS N5, NS N3, NS N2 PMOS Simulation Measurement O. Baumgartner et al. (GTS) GTS 19 / 25
25 Automated parasitics extraction O. Baumgartner et al. (GTS) GTS 20 / 25
26 BEOL resistances & capacitances O. Baumgartner et al. (GTS) GTS 21 / 25
27 FEOL resistances O. Baumgartner et al. (GTS) GTS 22 / 25
28 Multi-scale self-heating O. Baumgartner et al. (GTS) GTS 23 / 25
29 Modules summary Layout-based structrue generation Rapid prototyping Process-flow awareness Device simulation Steady-state, transient, AC Reliability What about calibration? Parasitics extraction R/C-network topology extraction Self-heating Quasi-transient simulation Thermal network extraction O. Baumgartner et al. (GTS) GTS 24 / 25
30 Our solutions Nano-scale TCAD Single-device TCAD Large-scale TCAD Path finding Process to device to cell to circuit variability Design-technology co-optimization (DTCO) O. Baumgartner et al. (GTS) GTS 25 / 25
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