Quarter-micrometre surface and buried channel PMOSFET modelling for circuit simulation

Transcription

1 Semicond. Sci. Technol ) Printed in the UK Quarter-micrometre surface and buried channel PMOSFET modelling for circuit simulation Yuhua Cheng, Min-chie Jeng, Zhihong Liu, Kai Chen, Bin Yu, Kiyotaka Imai and Chenming Hu Department of Electrical Engineering and Computer Science, University of California at Berkeley, Berkeley, CA 94720, USA Cadence Design Systems, Inc., 555 River Oaks Parkway, San Jose, CA 95134, USA BTA Technology Inc., 4633 Old Ironsides Drive, Santa Clara, CA 95054, USA Received 18 June 1996, accepted for publication 16 July 1996 Abstract. The modelling of PMOSFETs, with surface channels SC) and buried channels BC) down to deep quarter-micrometre, in BSIM Berkeley short-channel IGFET model) is discussed for analogue/digital circuit simulation. Based on physical mobility, velocity saturation, threshold voltage and series drain/source resistance models with some special considerations for PMOSFETs, a unified I V model describes the electrical characteristics of both NMOSFET and PMOSFETs, with surface channel and buried channel types. Because the model includes the major physical effects in state-of-the-art MOSFETs and contains many important process and geometry parameters, it can fit the measured data well and has a good scalability for both SC and BC PMOSFETs. 1. Introduction As CMOS technology develops, P-channel MOSFETs play very important roles in circuit design. VLSI circuit designers need a physical and accurate model of P-channel MOSFETs for use in circuit simulation. P-channel MOSFETs and N-channel MOSFETs are complementary, and operate on similar basic physical principles. However, many studies have shown that there exist some specific physical effects in P-channel MOSFETs, such as soft velocity saturation, enhanced short-channel effects and so on [1, 2], compared with the N-channel MOSFETs. Special considerations for these specific physical effects are needed. In this paper, we present the modelling of P-channel MOSFETs, which allows BSIM3 Berkeley short-channel IGFET model) to model both N-channel and P-channel MOSFETs with a unified equation. The model is verified with measured data of the PMOS devices with different channel types, i.e. surface channel and buried channel. 2. Physical analysis and modelling The modelling of N-channel MOSFETs in BSIM3v3 has been reported [3], and the model has also been verified with some benchmark tests for the N-channel MOSFETs for a wide range of channel lengths and widths from different technologies to check its accuracy, scalability and continuity [4]. However, there are some differences between N-channel and P-channel MOSFETs. Special care is taken to account for these differences when modelling the P-channel devices Mobility and velocity saturation models It is well known that an accurate I V model is strongly based on physical and accurate mobility and velocity saturation models for both N-channel and P-channel devices. It has been confirmed that both electron and hole mobility can be empirically described by a unified expression for arbitrary channel doping density and oxide thickness T ox [5, 6], µ 0 µ eff = 1) 1 + E eff /E 0 ) λ where µ 0 is the low-field mobility of the carrier, E eff is the effective field and E 0 is a constant which is different for electrons and holes. Based on the unified expression 1) for both electrons and holes, a Taylor expansion to second order) of equation 1) is used to describe the mobility characteristics of both electrons and holes in the BSIM3 model to improve the computational efficiency: µ eff = µ 0 ) ) Vgsteff+2V 1 + U th Vgsteff+2V 2 2) a T ox + U th b T ox + Uc V bs /96/ $19.50 c 1996 IOP Publishing Ltd 1763

2 Yuhua Cheng et al where µ 0,U a,u b,u c are parameters to be extracted from the measured data. T ox is the thickness of gate oxide. V th is the device threshold voltage. V bs is the body bias. V gsteff is a function which becomes V gs V th in the strong inversion region, and follows exp[ V gs V th V off )/nv t ]inthe subthreshold region [3], where V th is the thermal voltage, and the parameter n will be discussed later in this section. According to the above, we can use a unified mobility model for both electrons and holes but with different extracted values for the parameters such as µ 0,U a,u b and U c. Holes do not exhibit a velocity saturation effect as prominent as electrons. As a result, it is very difficult to identify the saturation voltage in the I V curve of a PMOSFET, especially at high gate voltage, because the current keeps increasing and saturates very slowly. This may be called soft saturation. This specific effect makes the modelling of the PMOSFET difficult, especially in the region of drain voltage close to the saturation voltage V dsat. Generally, different empirical expressions are used to describe the velocity field relationships for N- and P-channel MOSFETs [7], v Ey) = µ eff E y. 3) [1 + E y /E sat ) m ] 1/m Here, m 2 for electrons and m 1 for holes. E y is the absolute value of the longitudinal electric field in the channel, v sat is the saturation velocity and µ eff is the effective mobility, which considers the influence of the transverse electric field; E sat = v sat /µ eff is called the critical or saturation) field. It has been reported that 3) matches the experimental results well for both the electron and hole velocity in bulk silicon over a wide range of impurity concentrations and temperatures [7]. Because it is difficult to get an analytical solution for N-channel MOSFET model development based on 3), another approximation that can give a similar velocity field relationship to that of 3) for electrons was proposed for N-channel MOSFETs [8], v Ey) = µ effe y 1 + E y /E sat 4) where E sat = 2v sat /µ eff instead of v sat /µ eff given in 3). Equation 4) can be used to describe the velocity field relationship for N-channel devices, but cannot be used directly for the P-channel devices because of the different E sat values needed for N- and P-channel devices according to 3) and 4). To use a unified velocity field relationship for both electrons and holes, a term A 2, which essentially has the effect of modifying E sat in equation 4) to A 2 E sat, is introduced into the I V expression in BSIM3. A 2 is an extracted parameter, which is expected to have value close to 1 for N-channel devices, and close to 0.5 for PMOSFETs. The following expression is used to account for the drift current in the linear region: I dy) = W eff Q ch y)ve y ) 5) where W eff is the effective channel width and Q ch y) is the charge density in the channel [3]. Based on the above considerations and 5), a unified single expression is obtained with continuity for all of V gs,v ds and V bs in the following I ds0 I ds = 1 + V ) ds V dseff 1 + R ds I ds0 /V dseff V A ) 1 + V ds V dseff V ASCBE 6) here I ds0 is the intrinsic I V equation for R ds = 0 [3], R ds is the parasitic series drain/source resistance, V ds is the drain source bias, V dseff is a function that equates to V ds when V ds < V dsat and approaches to V dsat when V ds >V dsat. V ASCBE is the early voltage for the substratecurrent-induced body effect and V A is the early voltage contributed by channel length modulation and drain induced barrier lowering effects [3, 9] Short-channel effects To achieve a high drive current in P-channel MOSFETs, it is necessary to make the threshold voltage of a MOSFET as low as possible with the minimum value limited by subthreshold leakage. A so-called buried-layer PMOSFET structure is formed by boron ion implantation into the channel to adjust the threshold voltage. Because of the large depletion region width X dep ) due to the buried layer in the channel, the electric field emanating from the drain can penetrate further into the channel toward the source end) so that the short-channel effects are stronger in a buried channel PMOS than in an NMOS device. The analysis of two-dimensional effects is needed to account for the shortchannel effects in the buried channel PMOS devices such as threshold voltage roll-off, increased subthreshold swing and so on. Based on a quasi-two-dimensional analysis, a threshold voltage model, which can describe the non-uniform doping, short-channel and narrow width effects in small-size MOSFETs as well as the influence of p + and n + polysilicon gates, can be obtained [10]. Figure 1 shows that this model applied well to PMOSFET, both surface channel and buried channel devices. L t is larger in BC devices than SC devices because l t X 2/3 dep. A modified expression is used in this paper to improve the fit with the measured data for both N- and P-channel MOSFETs, especially for the narrow width/short channel devices: V th = V th0 + K 1 s V bs s ) K 2 V bs +K N lx 1 ) s T ox +K 3 + K 3b V bs ) s W eff + W [ 0 ) D VT0w exp D VT1w 2l tw )] +2 exp D VT1w V bi s ) l tw [ ) D VT0 exp D VT1 2l t )] +2 exp D VT1 V bi s ) l t 1764

3 PMOSFET modelling for circuit simulation modelling the deep-submicrometre devices for the circuit simulation. The resistances caused by the LDD structure can be divided into two parts; one part is modulated by the gate and body biases and another one independent of the bias. In BSIM3v3, the parasitic resistance R ds is modelled as R ds = R dsw[1 + P rwg V gsteff + P rwb φ s V bs φ s )] W eff Wr 9) where R dsw is the resistance per unit width and can be extracted from the measured data together with the parameters W r, P rwg and P rwb. 3. Test results and discussion Figure 1. Modelled and measured curves of log V th ) versus for PMOSFETs with surface and buried channels. [ ) )] exp D sub + 2 exp D sub 2l t0 E ta0 + E tab V bs )V ds 7) where V th0 is the threshold voltage for a long-channel device, V bi is the built-in potential of the drain/sourcebody junction, l t and l tw are functions of T ox, channel doping concentration and body bias. D VT0, D VT1, D VT0w, D VT1w, D sub, E ta0, E tab, W 0, K 1, K 2, K 3, K 3b and N 1x are parameters to be extracted from the measured data. The subthreshold swing in this paper is given as v t Ln 10 n), where n is in the following form: C d n = 1 + N factor + C dsc + C dscd V ds + C dscb V bs C ox C [ ) ox )] exp D VT1 + 2 exp D VT1 + C it. 2l t l t C ox 8) Here C d is the depletion width capacitance in the channel, N factor, C dsc, C dscb, C dscd and C it are parameters to be extracted from the measured data. Equation 8) has accounted for the influence of biases such as V bs and V ds on the subthreshold swing, which become more serious in PMOSFETs Bias-dependent parasitic series resistance To suppress the short-channel effects, an LDD lightly doped drain) structure is commonly used to achieve a shallow junction in a PMOS device [11]. The LDD structure may also increase the hot carrier resistance of the device [12]. However, the resistance caused by the LDD region, which is a function of V gs and V bs, will reduce the current drive current. The effects of parasitic series drain/source resistance should be considered accurately in l t0 PMOS device structures with both surface channels and buried channels are used to verify the model in accuracy, scalability and continuity. As an example, this paper gives some results for the devices with channel lengths down to the 0.25 µm range. P + polysilicon gates are used for the surface channel PMOSFETs, and N + polysilicon gates are used for the buried channel devices. The oxide thickness of all devices with both SC and BC is about 6.5 nm. Unless indicated in the figures, symbols represent measured data and full curves represent the results of the model calculations. All parameter extraction in this paper was performed with BSIMPro [13]. The modelled and measured V th characteristics versus device channel length for surface channel and buried channel devices are given in figures 2a) and b). It can be seen that the V th model can describe the roll-off characteristics of threshold voltage well for both surface channel and buried channel PMOS devices down to deepsubmicrometre range. To show the model accuracy further, comparison of the results of I d V d and I d V g between the model simulation and the measured data for devices with surface and buried channels is shown in figures 3 and 4 respectively. As can be seen in these figures the model can fit the measured data very well in both the current and output resistance characteistics. The maximum error between the model and data is 4.2% for the current characteristics of devices with two different channel types. Also, it can be seen that the soft saturation effect can be described well by the present model, and the model can match the data accuract in a wide V ds range. As shown in figures 5a) and b), the R out characteristics can also be modelled accurately in the saturation region for both surface and buried channel devices, down to the deep-submicrometre range, which shows again that the soft saturation effect in PMOS devices can be described well by the present model equation. As mentioned in section 2.1, the model can guarantee the continuities of current and its derivatives for all V ds,v gs and V bs by using a unified single equation in both linear and saturation regimes as well as in both subthreshold and strong inversion regimes. The good continuities and smooth tansition of current characteristics from subthreshold to strong inversion, and from linear to saturation regimes have 1765

4 Yuhua Cheng et al Figure 2. a) Modelled curves) and measured symbols) characteristics of threshold voltage versus effective channel length for PMOSFETs with a surface channel. T ox =6.5 nm. b) Modelled curves) and measured symbols) characteristics of threshold voltage versus effective channel length for PMOSFETs with a buried channel. T ox =6.5 nm. Figure 3. a) Modelled curves) and measured symbols) I d V d curves for SC PMOSFETs of W /L =50/0.25 T =25 C, V b = 0 V). b) Modelled curves) and measured symbols) I d V d characteristics for BC PMOSFETs of W /L =50/0.35 T =25 C, V b = 0 V). been shown in figures 3 and 4. Furthermore, the output conductance g ds versus V ds ) curves is shown in figure 6. Figure 6 shows that not only can the model match the measured data acurately, but that it can also ensure a smooth transition of the conductance g ds from the linear to the saturation regions, which should improve the computational efficiency of the model in the circuit simulation. The g m /I d ratio, a very important criterion to test a model for circuit simulation [14] is given in figure 7 for the devices with a surface channel. A continuous transition can also be seen for the g m /I d curves at different bias conditions. In figures 8 and 9, the I ds V gs and I ds V ds characteristics of the buried channel devices of different W/L are given to show the scalability of the model. It can be seen that 1766

5 PMOSFET modelling for circuit simulation Figure 4. a) Modelled curves) and measured symbols) I d V g curves for SC PMOSFETs of W /L =50/0.25 T =25 C, V d =0.05 V) in log scale). V bs =0,0.5,1.0,1.5,2.0,2.5 for curves from top to bottom. b) Modelled curves) and measured symbols) I d V g curves for BC PMOSFETs of W /L =50/0.35 T =25 C, V d =0.05 V) in log scale). V bs =0,0.5,1.0,1.5,2.0,2.5 for curves from top to bottom. the model can fit the data well for devices of channel lengths from the deep sub-micrometre range to longchannel devices with one set of model parameters extracted from the measured data. The maximum error is less than 4.25% for both types of devices throughout the W/L range. This demonstrates that the BSIM3v3 model can describe Figure 5. a) Modelled curves) and measured symbols) R out V d characteristics for SC PMOSFETs of W /L =50/0.25 T =25 C, V b = 0 V). b) Modelled curves) and measured symbols) R out V ds characteristics for BC PMOSFETs of W /L =50/0.35 T =25 C, V b = 0 V). the device characteristics well over a wide range of W/L with the same set of parameters because physical effects and process parameters are built into the model. 4. Summary Based on physical considerations of the mobility, velocity saturation, V th and R ds models, a continuous and scalable 1767

6 Yuhua Cheng et al Figure 8. Modelled curves) and measured symbols) I d V gs characteristics of BC devices with different W /L T ox =7nm,V ds =50mV,V bs = 0 V). Figure 6. Modelled curves) and measured symbols) g ds V ds characteristics for SC PMOSFETs of W /L =50/0.25 T =25 C, V b = 0 V). Figure 9. Modelled curves) and measured symbols) I d V ds characteristics of BC devices with different W /L T ox, V ds, V bs as figure 8). and its derivatives for all V ds,v gs from the subthreshold to the strong inversion regions, and from the linear to the saturation regions, whcih should improve the computational efficiency of the model in the circuit simulation. With the built-in dependence on process parameters, the present model is also suitable for use in statistical modelling. The present model has been implemented in HSPICE, SmartSpice, Spectre and SPICE3e2. Figure 7. Modelled curves) and measured symbols) g m /I d V gs characteristics for SC PMOSFETs of W /L =50/0.25 T =25 C, V d =0.05 V). V bs =0,0.5,1.0,1.5,2.0,2.5 for curves from bottom to top. I V model is presented for PMOSFETs with both surface and buried channels in circuit simulation. The accuracy, scalability and continuity of the present model are verified with measured data for the devices with both surface and buried channels down to the 0.25 µm range. The results show that the model can not only match the measured data from the two different channel type PMOS devices accurately, but can also ensure a smooth transition of I d Acknowledgment This work was supported by SRC grant 96-SJ-417. References [1] Assaderaghi F, Chen J, Ko P and Hu C 1992 Measurement of electron and hole saturation velocity in silicon inversion layers using SOI MOSFETs IEEE Int. SOI Conf. New York: IEEE) p 112 [2] Wolf S 1995 Silicon processing for the VLSI Era vol 3 The Submicron MOSFET Sunset Beach, CA: Lattice Press) [3] Cheng Yuhua, Hu Chenming, Chen Kai, Chan Mansun, Jeng Minchie, Liu Zhihong, Huang Jianhui and Ko Ping 1995 A unified BSIM I V mode for circuit simulation 1768

7 PMOSFET modelling for circuit simulation 1995 Int. Semiconductor Devices Research Symp. University of Virginia) pp [4] Cheng Yuhua, Jeng Minchie, Liu Zhihong, Chen Kai, Chan Mansun, Hu Chenming and Ko Ping 1996 An investigation on the robustness, accuracy and simulation performance of a physics-based deep-submicronmeter BSIM model for analog/digital circuit simulation CICC 96 New York: IEEE) pp [5] Liang M S, Choi J Y, Ko P K and Hu C 1986 Inversion-layer capacitance and mobility of very thin gate-oxide MOSFETs IEEE Trans. Electron Devices [6] Fang F and Fowler X 1969 Hot-electron effects and saturation velocity in silicon inversion layer J. Appl. Phys [7] Talkhan E A, Manour I R and Barboor A I 1972 Investigation of the effect of drift-field-dependent mobility on MOSFET characteristics part I and II IEEE Trans. Electron Devices [8] Sodini C G, Ko P K and Moll J L 1984 The effect of high fields on MOS devices and circuit performance IEEE Trans. Electron Devices [9] Huang J H, Liu Z H, Jeng M C, Ko P K and Hu C 1992 A physical model for MOSFET output resistance Int. Electron Device Meeting December [10] Liu Z H, Hu C, Huang J H, Chan T Y, Jeng M C, Ko P K and Cheng Y C 1993 Threshold voltage model for deep-submicrometer MOSFETs IEEE Trans. Electron Devices [11] Schmitz A and Chen J Y 1986 Design, modeling, and fabrication of submicron CMOS transistors IEEE Trans. Electron Devices [12] Hu C, Tam S, Hsu F C, Ko P K, Chan T Y and Kyle K W 1985 Hot-electron induced MOSFET degradation model, monitor, improvement IEEE Trans. Electron Devices [13] BSIMpro Manual 1995 BTA Inc., Santa Clara, CA, USA [14] Tsividis Y and Suyama K 1993 MOSFET modeling for analog circuit CAD: problems and prospects Tech. Digest CICC-93 New York: IEEE)