NONLOCAL effects are becoming more and more

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1 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 44, NO. 5, MAY Modeling Effects of Electron-Velocity Overshoot in a MOSFET J. B. Roldán, F. Gámiz, Member, IEEE, J. A. López-Villanueva, Member, IEEE, and J. E. Carceller, Member, IEEE Abstract A simple analytical expression to account for electron-velocity overshoot effects on the performance of very short-channel MOSFET s has been obtained. This new model can be easily included in circuit simulators of systems with a huge number of components. The influence of temperature and low-field mobility on the increase of MOSFET transconductance produced by electron-velocity overshoot as channel lengths are reduced can be easily taken into account in our model. The accuracy of this model has been verified by reproducing experimental and simulated data reported by other authors. I. INTRODUCTION NONLOCAL effects are becoming more and more prominent as MOSFET dimensions shrink to the deepsubmicrometer regime. Velocity overshoot is one of the most important effects from the practical point of view as it is directly related with the increase of current drive and transconductance experimentally observed in short-channel MOSFET s [1] [4]. Some authors [1] [4] have shown that experimental measurements of submicron MOSFET transconductances are higher than the theoretical maximum transconductance that can be reached in the case where electrons drift in equilibrium with the lattice, with their electron velocity being limited by the saturation velocity [1], [5]. This result has been shown for channel lengths under 0.15 m, which means that the electron velocity along the channel is higher than the saturation one; therefore, if velocity overshoot can be controlled, the performance of very short-channel MOSFET s can be improved with respect to the performance of long-channel transistors. This effect is also reasonably well understood from the theoretical point of view [6], [7]. It has been shown that an electric field step causes the electron velocity to overshoot the value that corresponds to the higher field for a period shorter than the energy relaxation time [6], [7] (the time needed by the electron to once again reach equilibrium with the lattice [8]). Therefore, as the longitudinal electric field increases, the electron gas starts to be in disequilibrium with the lattice [9]. There is an insufficient number of phonon-scattering events experienced by the electron during its flight, with the result that electrons can be accelerated to velocities higher than the saturation velocity, thus approaching ballistic transport conditions. This effect is due to the nonequivalence of momentum and energy-relaxation times and can be observed for a period shorter than the energy relaxation time. Hence, overshoot is Manuscript received October 1, The review of this paper was arranged by Editor D. P. Verret. This work has been carried out within the framework of research project TIC , supported by the Spanish Government (CICYT). The authors are with the Departamento de Electrónica y Tecnología de Computadores. Universidad de Granada, Granada, Spain. Publisher Item Identifier S (97) a clear nonequilibrium effect and cannot be predicted with simple drift-diffusion simulators, it being instead necessary to use more sophisticated simulators capable of dealing with nonequilibrium transport, such as the hydrodynamic [7] or Monte Carlo (MC) [9] [11] simulators. In fact, the high value of the transconductance for transistors with channel lengths under 0.15 m in an MC simulation [9] has been explained as being a consequence of nonequilibrium transport in the source edge. The same results were achieved by a drift-diffusion simulation augmented to account for velocity overshoot by means of a mobility model that depends on the electron temperature obtained under energy conservation conditions [12]. The need for more sophisticated device simulations is becoming an easily solvable problem, as computer speed and storage capacity are rapidly increasing. Nevertheless, for this same reason it is easy to foresee that simple drift-diffusion simulators will likely be included in circuit computer-aideddesign tools instead of the simpler analytical models in the near future in order to increase simulation accuracy. In addition, the simple analytical model can still be used for simulation of systems including a huge number of components. In short, there is still a need for accurate models at different levels, but as the trend of MOSFET technology is toward sub-0.1 m [1], [13], it is desirable to be able to predict velocity-overshoot effects at these different modeling levels. The aim of this study is to model velocity-overshoot effects on MOSFET transconductance. MOSFET transconductance,, is known to be the most important figure of merit in dealing with the large-signal switching performance of logic devices, as the time constant for a small MOSFET to charge a load is proportional to, where is the node capacitance. That is why accurate modeling of this parameter is essential in circuit simulators of state-of-the-art MOSFET s [14]. We have used an augmented drift-diffusion velocity model reported previously by several authors [15] [18] to obtain a simple analytical expression to model the MOSFET transconductance increase that has been experimentally observed [1] [4] as MOSFET effective channel lengths shrink. The results will be compared to the experimental and the MC simulated transconductances obtained by G. A. Sai-Halasz et al. [1] and M. R. Pinto et al. [19], respectively. Low-field mobility and temperature effects can be easily taken into account, as will be shown. II. TRANSCONDUCTANCE CALCULATION We suppose that the source is located at and the potential at that point is zero; the drain is assumed to be at (where is the effective channel length, henceforth we /97$ IEEE

2 842 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 44, NO. 5, MAY 1997 will mean effective channel length wherever we use channel length) at a potential The drain current can be calculated as a product of the mobile channel charge, the channel width, and the electron velocity along the axis, from source toward the drain. Rearranging this relationship to obtain a term multiplied by and a term multiplied by, and integrating these terms along the channel, from 0 to and from 0 to, respectively, yields an expression for the drain current. The drift velocity in inhomogeneous electric field can be expressed approximately as [16] where is the drift velocity in a homogeneous field. The parameter was supposed by Thornber [16] to be dependent on the longitudinal-electric field. Artaki also studied this dependence in detail [17]. In both cases, this dependence was shown to be important at low-longitudinal-electric fields. However, the higher values of the longitudinal-electric-field gradient are located near the drain edge in short-channel MOSFET s, where high longitudinal fields can also be found under normal operation conditions. The dependence of the parameter on the longitudinal field is not very important for these high-field gradients. In order to check this fact, we have performed many MC deep-submicron MOSFET simulations including inversion layer quantization by changing the channel length and bias. The results showed that the parameter can be regarded as a constant for the usual longitudinal field range found in short-channel MOSFET s. The reduced complexity of (1) when the term connected to the longitudinal-field gradient is taken as a constant allows us to obtain a closed analytical expression for the transconductance. A useful expression (2) has been given for the drift velocity in homogeneous field [20] At this stage some simplifying assumptions are made: we take an average value for the low longitudinal-electric-field mobility corresponding to an average value of the transverseelectric field along channel, which is not a rough approximation for low- and medium-drain voltages. We also take, which simplifies the algebra below. This approximation is along the lines of a series expansion of the denominator in (2) proposed by N. D. Arora [21], and has also been reported by other authors [22], [23]. The electron-velocity expression under the reported assumptions has been put into the drain-current equation [5]. Integrating from source to drain along the channel we get (1) (2) We integrated the above expression making use of the meanvalue theorem for the second term in brackets and a simple variable change for the rest. The result is given by where the mean value is shown in angles for the expression above, and the function is the integral of the inversion charge in the channel On one hand, the expression in angles is very high near the drain compared to the value of this expression in other zones of the channel. On the other hand, the value of the inversion charge which multiplies this value in the integral is higher near the source than in the rest of the zones closer to the drain, so there is no zone of the channel where the integrand is clearly dominant. Therefore, we will use a semiempirically modified mean value along the channel for the expression in angles. To do so, we approximate the first and second derivative of the electrostatic potential as follows: where is a constant that could be dependent on the operation voltages and the technological features of the MOSFET s such as the low-field mobility. An expression similar to the first part of (6) can be found in [24]. The approximations shown in (6) and some others explained above have to be considered within the first-order approximation empirical approach we are dealing with in order to obtain a closed analitycal expression to model electron-velocity-overshoot effects in short-channel MOSFET s. As can be seen, both the and parameters contribute to increase the second term in the same way, so the dependencies of both parameters can be merged in a single one,, which will be used henceforth. The final result we obtained for the drain current after the previous considerations was given by Making use of (7), the MOSFET transconductance can be calculated as (4) (5) (6) (7) (8) (3) (Henceforth transconductances adjusted for width normalization will be used.) In accordance with the above calculation, it is obvious that the quotient of the transconductance, accounting and

3 ROLDAN et al.: MODELING EFFECTS OF ELECTRON-VELOCITY OVERSHOOT 843 Fig. 1. Room-temperature ratio between experimental and simulated intrinsic transconductances versus channel length for a sample of MOSFET s reported by G. A. Sai-Halasz et al. [1] is shown in squares for a bias of V GS 0 V T = 0:6 V, V DS = 0:8 V. The same ratio calculated analytically by (9) with the following values: V DS =0:8 V, m =390cm 2 /Vs;v sat = cm/s; and a = cm 3 =Vs is shown in solid line. not accounting for the effects of velocity overshoot, can be calculated as III. RESULTS AND DISCUSSION In order to check this expression, we have calculated the ratio between experimental intrinsic transconductances measured for a sample of MOSFET s fabricated by G. A. Sai- Halasz et al. [1] and the same transconductances calculated by these authors using a classical drift-diffusion simulator with V, V, cm Vs cm/s at K. The ratio provided in reference [1] has been plotted in Fig. 1 in squares. The same ratio, calculated using (9) for the same parameters, is shown in solid line for cm Vs and the constant values given by Sai- Halasz et al. An excellent agreement is reached throughout the range of effective channel lengths. Value is coherent with the significant increase of the saturation velocity reported in [1] that the authors needed to use in the drift-diffusion simulator to reproduce the experimental transconductances; a significant increase of the saturation velocity for both room temperature and low temperature was needed, mostly for channels shorter than 0.1 mm. Examining (1), the first term corresponding to the homogeneous transport regime is found to saturate at high longitudinal-electric fields, so a value of 25 40% of the saturation velocity is expected for the second term of the equation in order to obtain the same velocities reported by the authors at the lowest channel lengths. To get an average increase of 25 40% in the electron velocity along the channel, particulary for the saturation velocity, a value of times has to be introduced in (1) in place of, and therefore the value found for parameter is suitable. The same verification procedure was repeated for K in Fig. 2. A perfect fit, as before, was obtained using the parameters reported in [1] for the simulation of the MOSFET s at low temperature, which were V, V, cm Vs, cm/s (9) Fig. 2. Low-temperature (T = 77 K) ratio between experimental and simulated intrinsic transconductances versus channel length for a sample of MOSFET s reported by G. A. Sai-Halasz et al. [1] is shown in squares for a polarization of V GS 0 V T =0:6 V, V DS =0:8 V. The same ratio calculated analytically by (9) with the following values: V DS =0:8 V, = 720 cm 2 =Vs;v sat = cm/s, and a = cm 3 =Vs is shown in solid line. cm Vs An increase of the value is coherent as we reduce temperature since as temperature goes down electronphonon interaction is lower than at room temperature [25]. As can be observed in Fig. 2, the ratio of experimental and drift-diffusion simulated transconductances is higher at low temperatures for all channel lengths for the same devices, which supports the explanation given above. The same reasoning used to determine the appropriate value for parameter, taking into account similar values for the longitudinal-electricfield derivative (the same bias is used at both temperatures), can be applied in this case. The increase of saturation velocities used in the drift-diffusion simulator to fit the experimental transconductances is higher than at room temperature, which is why a higher value of is expected, again, to account for this additional increase. We have also tried to reproduce the experimental intrinsic transconductances by applying (8). To do so, we fitted the measurements by G. A. Sai-Halasz et al. using (8) and an estimated value for the partial derivative of To get this estimated value we took as a starting point a general expression for the absolute value of the inversion charge per unit area in MOSFET s [5] (10) where is the oxide capacity per unit area, is the flatband voltage, is the surface potential and the depletion charge per unit area. The voltage between substrate and source was zero. Therefore, we can substitute by In strong inversion, the surface potential can be approximated by along the channel, where equals is the difference between the Fermi level and the intrinsic Fermi level in the bulk in ev, and being Boltzmann s constant). If we substitute this value of the surface potential in strong inversion (which is the case here, in (10) if is represented only by its value at the source, if its variation along the channel is neglected, and if the definition of threshold voltage is used [5], we obtain (11)

4 844 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 44, NO. 5, MAY 1997 Fig. 3. Experimental intrinsic transconductances versus channel length for a sample of MOSFET s reported by G. A. Sai-Halasz et al. [1] are shown in squares for a polarization of V GS 0 V T = 0:6 V, V DS = 0:8 V at T = 300 K and T = 77K. Intrinsic transconductances calculated making use of (8) with the following values: V DS = 0:8 V, =390 cm 2 =Vs;v sat = cm/s; a = cm 3 GS ;V DS )=@V GS =5: C/cm 2 at T = 300 K (dashed line) and = 720 cm 2 =Vs;v sat = cm/s; a = cm 3 GS ;V DS )=@V GS =5: C/cm 2 at T =77K (solid line). So, regarding the definition of function estimated value of the partial derivative of be easily obtained, (5), an can (12) The value given by G.A. Sai-Halasz et al. for the oxide width was 4.5 nm, so for the biases reported above V, V the estimated value of the partial derivative of is C/cm The values used to fit the experimental intrinsic transconductances for the partial derivative for were C/cm at K and C/cm at 77 K. A perfect fit can be observed in both cases (Fig. 3). The value obtained here is a useful estimation of the partial derivative of, but some dependences have been neglected as the reduction of the channel-inversion charge in the pinch-off region in the saturation operation region regime, and other dependences related to application of the meanvalue theorem. These relative errors are comparable to those reported by G. A. Sai-Halasz et al. in determining channel lengths due to the difficulty they had in accurately obtaining them and the series resistance in LDD-like devices with strong two-dimensional effects [26]. So far, the model has been validated by comparison with experimental data reported by Sai-Halasz et al. [1]. However, it is difficult to ascertain the presence of velocity overshoot from experiments on very short MOSFET s. In fact, very critical measurements of gate capacitance and parasitic resistances are required. Therefore, the quantitative estimation of velocity overshoot from experimental data is likely to present uncertainties. The intrinsic transconductances are calculated from the experimental transconductances by using the source and drain series resistances [27], the uncertainties involved in the series resistance and effective channel length extraction procedure explained in [26] can significantly reduce the real transconductance value. In addition, the calculation of Fig. 4. Simulated intrinsic transconductances versus channel length for a MOSFET for three different constant channel mobilities reported by M. R. Pinto et al. [19] are shown in squares ( e = 125 cm 2 =Vs); circles ( e = 250 cm 2 =Vs); and triangles ( e = 500 cm 2 =Vs) for a polarization of V GS = V DS = 1:5 V. Intrinsic transconductances calculated making use of (8) with the following values: v sat = 10 7 GS ;V DS )=@V GS = C/cm 2 and a =15;30; cm 3 =Vs for e = 125;250;500 cm 2 =Vs, respectively, are shown in solid line. the theoretical maximum transconductance can be affected by the separation of the inversion charge centroid from the oxide surface (quantum effects), mostly in short-channel devices such as the ones fabricated by Ono et al. [13] where the oxide thickness was 30 Å and the distance of the inversion charge centroid from the Si/SiO surface can be more than 25% of the oxide thickness. That might be the reason for the absence of velocity overshoot reported in devices as short as 40 nm [13]. On the other hand, the value of the saturation velocity of the carriers in the channel is not well known since reported experimental and simulated values are very different [11], [28] [31]. The above discussion reveals it to be desirable to validate the model by comparison with the results of accurate simulations such as those reported by Pinto et al. [19]. The intrinsic transconductance versus channel length curves given by Pinto et al. were calculated by using accurate simulators including electron-velocity overshoot effects. A common NMOSFET device was used and a different value for the low-field mobility was selected for each transconductance curve (Fig. 4). We have reproduced the curves of Pinto et al. (symbols) by employing (8) (solid line) and the following parameters: V, cm/s (given in [19]) and C/cm (the same for all the curves, due to the use of the same device in all cases). Pinto et al. used different values of the effective mobility in the channel for their simulations, each different value corresponding to different technological features in MOSFET s. Different values for each assumed mobility value have to be employed. The values employed were cm Vs for cm Vs, respectively. It is clear that technological variations play an important role on the impact of electron-velocity overshoot effects. As can be seen, these variations can be easily included in our model. The expressions deduced for the transconductance (8), and particularly the term used in (1) to complete Expression

5 ROLDAN et al.: MODELING EFFECTS OF ELECTRON-VELOCITY OVERSHOOT 845 (a) Fig. 5. Terms A and B described in (13) are shown versus channel length at (a) T = 300 K and (b) T =77K for the same constant values used in Fig. 3 at each temperature. Term A (white squares), Term B (full squares). (b) 2 accounting for velocity-overshoot effects, can be seen as a functional approach to the behavior of deep-submicron MOSFET s as dimensions shrink to channel lengths under 0.1 m To attempt to see more clearly what the contribution of the new term to the previous one is as the MOSFET channel length is reduced, we have plotted them versus channel length, as they appear in (8), adjusting for channel width and normalization. The results for (a) K and (b) K are shown in Fig. 5 for the constant values used in Fig. 3, where Terms A and B are Term A Term B (13) As can be observed, Term B is not worth taking into account for channel lengths over 0.2 m at both temperatures. Velocity overshoot, as expected, does not affect the transconductance for these lengths. The increase in the saturation-velocity value needed to simulate the experimental transconductance using the drift-diffusion simulator reported by G. A. Sai-Halasz et al. was less than 5% for these lengths; however, as channel length is reduced, Term B rises, which shows the effects of velocity overshoot in MOSFET transconductance. Higher modifications to the saturation velocity were needed to reproduce experimental transconductances using the drift-diffusion simulator for shorter channel lengths [1]. An obvious greater increase is expected for saturation velocity needed at K due to the higher parameter (higher low-field mobility) we have used at this temperature, also reported by G. A. Sai-Halasz et al. A noticeable increase in MOSFET transconductance has also been found by other authors in the channel length interval m [9], [12], which is the range where Term B starts to be important compared to Term A. It has been shown that the influence of the parameters that contribute to enhancing velocity-overshoot effects, such as the longitudinal-electric-field gradient in the MOSFET channel, temperature, low-field mobility, etc, can be taken into account by means of (8). Dependences of the parameter on the temperature and the low-field mobility are clear; however, the lack of both experimental and simulated data for a single technology at different biases do not allow bias dependence on the parameter to be demonstrated. IV. CONCLUSIONS A simple analytical model to account for electron-velocityovershoot effects on submicron MOSFET transconductance has been provided. It has been shown that as channel dimensions shrink to under 0.15 m, a term inversely proportional to the square of the MOSFET channel length accurately describes the transconductance increase produced by electronvelocity overshoot. This model can be easily included in circuit simulators of systems with a huge number of components. Experimental and simulated data were used to check the accuracy of our model and to account for the temperature and low-field mobility dependence of the transconductance increase due to velocity-overshoot effects. It has been demonstrated that the lower the temperature and the higher the low-field mobility, the higher the correction needed to reproduce experimental and simulated results. REFERENCES [1] G. A. Sai-Halasz, M. R. Wordeman, D. P. Kern, S. Rishton, and E. Ganin, High transconductance and velocity overshoot in NMOS devices at the 0.1-m gate-length level, IEEE Electron Device Lett., vol. 9, p. 464, [2] S. Y. Chou, D. A. Antoniadis, and H. I. Smith, Observation of electron velocity overshoot in sub-100-nm-channel MOSFET s in silicon, IEEE Electron Device Lett., vol. EDL-6, p. 665, [3] G. G. Shahidi, D. A. Antoniadis, and H. I. Smith, Electron velocity overshoot at room and liquid-nitrogen temperatures in silicon inversion layers, IEEE Electron Device Lett., vol. 9, p. 94, [4] F. Assaderaghi, P. D. Ko, and C. Hu, Observation of velocity overshoot in silicon inversion layers, IEEE Electron Device Lett., vol. 14, p. 484, [5] Y. P. Tsividis, Operation and Modeling of the MOS Transistor. New York: McGraw-Hill, [6] J. G. Ruch, Electron dynamics in short channels field-effect transistors, IEEE Trans. Electron Devices, vol. ED-19, pp. 652, [7] G. Baccarani and M. R. Wordeman, An investigation of steady-state velocity overshoot in silicon, Solid-State Electron., vol. 28, p. 407, [8] K. Seeger, Semiconductor Physics: An Introduction, 5th ed. Berlin, Springer-Verlag, [9] E. Sangiorgi and M. R. Pinto, A semi-empirical model of surfacescattering for Monte Carlo simulation of silicon N-MOSFET s, IEEE Trans. Electron Devices, vol. 39, pp. 356, 1992.

6 846 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 44, NO. 5, MAY 1997 [10] S. E. Laux and M. V. Fischetti, Monte Carlo simulation of submicrometer Si N-MOSFET s at 77 and 300 K, IEEE Electron Device Lett., vol. 9, p. 467, Sept [11] M. V. Fischetti and S. E. Laux, Monte Carlo study of electron transport in silicon inversion layer, Phys. Rev. B, vol. 48, pp. 2244, [12] T. Kobayasi and S. Kazuyuki, Two-dimensional analysis of velocity overshoot effects in ultrashort-channel Si MOSFET s, IEEE Trans. Electron Devices, vol. ED-32, pp , [13] H. Ono, S. Masanobu, Y. Takashi, C. Fiegna, O. Tatsuya, and H. Iwai, A 40-nm gate-length n-mosfet, IEEE Trans. Electron Devices, vol. 42, pp , [14] M. V. Fischetti, S. E. Laux, and W. Lee, Monte Carlo simulation of hotcarrier transport in real semiconductor devices, Solid-State Electron., vol. 32, p. 1723, [15] P. J. Price, On the flow equation in device simulation, J. Appl. Phys., vol. 63 p. 4718, [16] K. K. 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Nelson, High-field drift velocity of electrons at the Si-SiO 2 interface as determined by a time-of-flight technique, J. Appl. Phys., vol. 54, p. 1445, [29] A. Modelli and S. Manzini, High-field drift velocity of electrons in silicon inversion layers, Solid-State Electron., vol. 31, pp. 99, [30] F. Fang and A. B. Fowler, Hot electron effects and saturation velocities in silicon inversion layers, J. Appl. Phys., vol. 41, p. 1825, [31] D. K. Ferry, Transport of hot carriers in semiconductor quantized inversion layers, Solid-State Electron., vol. 21, p. 115, F. Gámiz received the degree in physics in 1991, and the Ph.D. degree in 1994 from the University of Granada, Granada, Spain. Currently, he is an Associate Professor at the University of Granada. Since 1991, he has been working on the charge carriers in semiconductor heterostructures. He has studied electron mobility in silicon inversion layers by the Monte Carlo method. His current research interests include the effects of many-carriers on the electron mobility and the theoretical interpretation of the influence of high longitudinal electric fields on the electric properties of MOS transistors. His current interests are also releated to SiGe, SiC, and SOI devices, and quantum transport. He has coauthored several papers in all these subject areas. J. A. López-Villanueva received the degree in physics in 1984, and the Ph.D. degree in 1990 from the University of Granada, Granada, Spain. His thesis was on the degradation of MOS structures by Fowler Nordheim tunneling. Currently, he is an Associate Professor at the University of Granada. Since 1985, he has been working on deep-level characterization and mainly, MOS device physics, including Fowler Nordheim and direct tunneling, quantum effects, 2-D transport, effects of nonparabolicity, scattering mechanisms, and Monte Carlo simulation of charge transport. He has coauthored several papers in all these subject areas. His current research interest includes the characterization, simulation, and modelling of electron devices, with emphasis on the MOS transistor. His educational activities also include analog systems for electronic instrumentation and power electronics. J. E. Carceller received the degree in physics in 1975, and the Ph.D. degree in 1979 from the University of Barcelona, Barcelona, Spain. He has been a Professor at the Universities of Barcelona and Granada. He was engaged in the research and characterization of deep levels in semiconductors. His current research interest includes degradation of MOS structures and characterization of electron mobility in the channel of MOS transistors. J. B. Roldán received the degree in physics from Granada University, Granada, Spain, in Currently, he is a Teaching Assistant at the University of Granada. Since 1993, he has worked on the MOS device physics including 2-D transport, nonlocal effects, and Monte Carlo simulations. His current interests are also related to SiGe and SiC devices.