PHYSICAL ANALYSIS, MODELING, AND DESIGN OF NANOSCALE DOUBLE-GATE MOSFETS WITH GATE-SOURCE/DRAIN UNDERLAP MURSHED M. CHOWDHURY

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1 PHYSICAL ANALYSIS, MODELING, AND DESIGN OF NANOSCALE DOUBLE-GATE MOSFETS WITH GATE-SOURCE/DRAIN UNDERLAP By MURSHED M. CHOWDHURY A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2006

2 Copyright 2006 by Murshed M. Chowdhury

3 -To- My parents and Rono

4 ACKNOWLEDGMENTS It has been an honor to work for, and with, my supervisor, Professor Jerry Fossum. Without his patient and inspiring guidance, encouragement, and support, this work would not have been possible. I would like to take this opportunity to express my gratitude to him. I would also like to thank members of my supervisory committee, Professors Scott Thompson, Jing Guo, and Kevin Ingersent, for their guidance and interest in this work. I would like to acknowledge Semiconductor Research Corporation, Freescale Semiconductor, and the National Science Foundation for their financial support. I would also like to thank Freescale Semiconductor and AMD Inc. for measured data. I am grateful to Bich-Yen Nguyen for giving me an opportunity to gain industry experience at Freescale Semiconductor. I have greatly benefited from the interactions with the Novel Device, CMOS and MICA group members. I was extremely lucky to have Leo Mathew and Chip Workman as my mentors there, both of whom patiently suffered my constant demand of data and modeling-tips. Also, I am thankful to Aaron Thean and Ben Gu for numerous discussions. I was fortunate to work with fellow group mates, Lixin Ge, Ji-Woon Yang, Vishal Trivedi, Weimin Zhang, Seung-Hwan Kim, Zhichao Lu, Siddharth Chouksey, and Shishir Agarwal. I have had many illuminating discussions with them, especially with Vishal, working with whom was an intriguing and beneficial experience. I iv

5 would like to thank my friend Saif Uz Zaman, and Khairul Alam for riveting conversations on many aspects of device physics. In addition, I would like to thank Saif, and Syed Hussain Rana for reading this manuscript. I acknowledge the unconditional help I received from Tipu bhai, Boro Dulabhai, and Sheuli khala. I was fortunate to have such relatives and friends who are always there when needed. Likewise, my stay here in Gainesville is made easier by the presence of an accommodating community, whose good fellowship helped me to keep my morale high all these years. In particular, I would like to thank Maksudur Rahman, Shahed Nejhum, Sayed Hasan, Avijit Kar, Ziad Saleh, Naheen Aden, Shahed Reza, Reza Nabi, Mustaque Ahmed, and Amas Khan for their camaraderie. Finally, I am indebted to my parents, and siblings, Appi, Rono, Shetu, Rana, Meru and Moury, for their constant encouragement and support. My deep gratitude goes to my parents for their many sacrifices for my education. This work is dedicated to them, and to my selfless brother. v

6 TABLE OF CONTENTS page ACKNOWLEDGMENTS iv LIST OF TABLES ix LIST OF FIGURES x KEY TO ABBREVIATIONS xiv ABSTRACT xv CHAPTER 1 INTRODUCTION Double-Gate MOSFETs; FinFETs Compact Model for the DG MOSFET Dissertation Outline PHYSICAL INSIGHTS ON DESIGN AND MODELING OF NANOSCALE FINFETS Introduction UFDG Calibration Methodology Calibration of UFDG to AMD nfinfets Calibration of UFDG to Freescale Poly-Gate nfinfets Calibration of UFDG to Freescale Metal-Gate pfinfets Device Design Implications Summary UFDG UPGRADES FOR NANOSCALE FINFETS WITH UNDERLAPS Introduction Calculation of Weak-Inversion Current in UFDG Review of Weak-Inversion Current Model in UFDG Source/Drain-Body Junction Potential Weak-Inversion Model Verification for DG MOSFET vi

7 3.3 Upgrades in Weak-Inversion Model for FinFET with Underlaps Model Upgrades Verification and Utility Upgrades in Strong-Inversion Model for FinFET with Underlaps Effective Channel Length Parasitic Resistance Conclusion CARRIER TRANSPORT IN NANOSCALE FINFETS Introduction Carrier Mobility in the Channel Electron Mobility in nfinfet Hole Mobility in pfinfet Ballistic-Limit Current Effects of Parasitics, and Design Implications Effects of Parasitic Resistance Effects of Parasitic Capacitance Summary SENSITIVITY OF FINFET PERFORMANCE TO GATE-SOURCE/DRAIN UNDERLAP PROPERTIES Introduction Reference FinFET Effects of Variation of Film Thickness Effects of Variation of Gate Length Effects of Variation of Lateral Straggle Effects of Random Doping N SD (y) Randomness N SD (x) Randomness Random UTB/Channel Doping Worst-Case Scenario Summary GATE TUNNELING CURRENT IN NANOSCALE FINFETS Introduction Compact Model for Gate Tunneling Current in FinFET Tunneling Current Components Tunneling Current Model Tunneling in Asymmetric-Gate Devices Drain Bias Dependence of Tunneling Current Model Implementation and Verification Effects of Gate Tunneling Current on FinFET-CMOS Performance Summary vii

8 7 CONCLUSIONS AND RECOMMENDATIONS APPENDIX 7.1 Summary and Conclusion Recommendations for Future Work MISCELLANEOUS UFDG UPGRADES A.1 Refining the Moderate-Inversion Spline A.2 Incorporating NBODY= 0 Option A.3 Refining the Charge Modeling A.3.1 Accumulation Charge A.3.2 Weak-Inversion Charge A.4 Refinement of the Velocity Overshoot Model A.5 Weak-Inversion QM Model REFERENCES BIOGRAPHICAL SKETCH viii

9 LIST OF TABLES Table page 2.1 Key UFDG model parameters with brief description UFDG-predicted ring-oscillator delay for an 18nm-FinFET Key UFDG model parameters extracted from the calibration SCHRED-predicted subband occupation properties Key UFPDB model parameters used in the study MEDICI- and UFDG-predicted characteristics of FinFETs UFDG-predicted variation of performance of FinFET-CMOS ix

10 LIST OF FIGURES Figure page 1.1 Double-Gate MOSFET structures Measured SCEs vs. L g of CMOS FinFETs Partial UFDG calibration to an L g = 105nm nfinfet Partial UFDG calibration to an L g = 17.5nm nfinfet Partial UFDG calibration to an L g = 100nm nfinfet Calibration of UFDG to metal-gate pfinfets Calibration of UFDG to a 75nm metal-gate pfinfet Variation of TiN gate workfunction (Φ M ) with drawn length Schematic cross section (top view) of an undoped FinFET Effects of underlaps on the subthreshold characteristics of FinFET MEDICI-predicted variation of I ON and I OFF MEDICI-predicted variation of FinFET performance Boundaries for the solution of Poisson s equation in the DG-MOSFET Lateral potential profile in weak inversion in the channel Schematic of variation of lateral potential Comparison of the variation of boundary potential Comparison of UFDG predictions with that of MEDICI in weak inversion MEDICI-predicted surface potential variation between S and D x

11 3.7 UFDG calibration to a MEDICI-simulated mid-gap FinFET MEDICI- and UFDG-predicted potential profile, φ(y) Recalibration of the 18nm-FinFET Calibration of UFDG to a MEDICI-simulated 15nm-thick fin FinFET MEDICI-simulated electric field vector in the x-y plane Comparison of UFDG predicted LES + LED MEDICI-predicted electron velocity along the channel Extracted linear resistance of an 18nm-FinFET Comparison of MEDICI- and UFDG-predicted I-V characteristics UFDG-predicted variation of ring-oscillator delay Calibration of UFDG to weak-inversion characteristics Calibration of UFDG to measured g m /I 2 D vs. V GS UFDG-predicted strong-inversion I D -V GS characteristics MEDICI-predicted variation of g m /I 2 D with polysilicon doping SCHRED-predicted average distribution of carriers Calibrated UFDG-predicted variation of effective electron mobility Results of calibrating UFDG to an L g = 10mm pfinfet UFDG calibration to the I D -V GS characteristics of the 10mm-pFinFET UFDG-predicted effective hole mobility UFDG-predicted current-voltage characteristics Effects of parasitic resistance on the on-sate current Predicted propagation delays versus parasitic source/drain resistance Predicted propagation delays versus parasitic capacitance xi

12 5.1 The lateral S/D-extension doping concentration, N SD (y) Partial calibration of UFDG to MEDICI-predicted characteristics FinFET-CMOS circuits used in the sensitivity study Sensitivity of FinFET performance-parameters with the variation of t Si Sensitivity of FinFET performance-parameters with the variation of L g Effects of varying L g, but keeping L ext constant Effects of variation of lateral straggle on the sensitivity of FinFET Various lateral doping profiles Localization of lateral dopants, N SD (y) at different x Medici-predicted I D -V GS characteristics Taurus-Device-predicted effects of uncontrolled doping on I D -V GS Leakage current components in a CMOS-inverter Tunneling current components in an nfinfet Dominant tunneling component in a metal-gate Tunneling from semi-classical picture SCHRED-simulated conduction band profile Comparison of distance between classical turning points Variation of ground-state electron velocity with bias Schematic of variation of E c (x) in weak inversion in a MIGFET Variation of I GS /I G with drain bias Updated UFDG network diagram Significance of the higher subbands in FinFET Comparison of UFDG gate leakage model s prediction xii

13 6.13 Effects of DREFF on gate leakage current UFDG-predicted tunneling current through the gates UFDG-predicted tunneling current in n- and p-channel FinFETs UFDG-simulated transient response of an FinFET-SRAM cell Gate-current density at three future ITRS nodes Comparison of UFDG-predicted leakage currents in nfinfet A.1 Cartoon depicting a typical I D -V G characteristics A.2 Effects of UFDG model parameter DG A.3 UFDG2.4 simulated I D -V G characteristics A.4 High field region in the channel of a double-gate MOSFET A.5 Comparison of effective saturated velocity A.6 Comparison of weak-inversion quantum-mechanical model xiii

14 KEY TO ABBREVIATIONS MOSFET CMOS SOI FD UTB SG SDG ADG IG UFDG KE PE SCE DIBL QM TEM MC DOS SDE Metal-Oxide-Semiconductor Field-Effect Transistor Complementary MOS Silicon-on-Insulator Fully depleted Ultra-thin body Single gate Symmetrical double gate Asymmetrical double gate Independent gate University of Florida Double Gate Kinetic energy Potential energy Short-channel effect Drain-induced barrier lowering Quantum mechanical Transmission Electron Microscopy Monte Carlo Density of states Source/Drain Extension xiv

15 Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy PHYSICAL ANALYSIS, MODELING, AND DESIGN OF NANOSCALE DOUBLE-GATE MOSFETS WITH GATE-SOURCE/DRAIN UNDERLAP By Murshed M. Chowdhury August 2006 Chairman: Jerry G. Fossum Major Department: Electrical and Computer Engineering This dissertation focuses on the physics and modeling of nanoscale double-gate (DG) field-effect transistors (FETs). The modeling work is incorporated in the University of Florida Double-Gate (UFDG) metal-oxide-semiconductor fieldeffect transistor (MOSFET) model that enables predictive device/circuit simulations of complementary metal-oxide-semiconductor (CMOS) circuits based on DG FETs. Physical insights on the electrostatics of the DG MOSFET, especially the quasi-planar FinFET, are gained from calibration of UFDG to data obtained from industry. The calibration results show that contemporary FinFETs have gate-source/ drain underlap that makes the effective channel length, and parasitic resistance, biasdependent. Insights from the calibrations, along with numerical simulation results, reveal that the noted underlaps could be used beneficially in scaled FinFET design. The study also pinpoints required UFDG upgrades for nanoscale FinFETs, which are subsequently done and implemented in UFDG. xv

16 The upgraded model is then used to gain insights on the transport properties of scaled FinFETs by, again, calibrating UFDG to experimental data. The calibration results show mobilities in both p- and n- channel FinFET are dramatically high compared to those in bulk-si MOSFETs. The high mobilities portend, as shown by UFDG, ballistic-limit current in nanoscale FinFETs, which leads us to the conclusion that channel engineering, like straining the channel, to increase mobility in the FinFET is not needed. The viability of gate-source/drain underlap as a design parameter, in addition to typical device design parameters like gate length, fin thickness, etc., is investigated in terms of the sensitivity of FinFET performance to the variations of process parameters that influence underlap properties; numerical simulators with UFDG aid this investigation. It is found that while variation in the performance of inverter-based circuits, like the ring oscillator, is reasonable, stability of static random access memory (SRAM) shows wide variation in performance for shorter underlap lengths. Finally, a physics-based compact model for gate tunneling current in DG MOSFETs is developed, verified, and implemented in UFDG to enable reliable prediction of static power consumption in nanoscale FinFET circuits. Model predictions corroborate earlier results that for thinner oxides, present-day silicon oxynitride has to be replaced with high-k dielectrics to control static leakage. However, use of underlap can relax the oxide thickness requirement and hence delay the introduction of high-k dielectrics in FinFET technology. xvi

17 CHAPTER 1 INTRODUCTION 1.1 Double-Gate MOSFETs; FinFETs In the past three decades, the number of transistors per chip has gone up to a few hundred million, from a few thousand in the early 70s [Boh03]. Such an astronomical increase of transistors per chip is facilitated by continuous scaling of the bulk-si MOSFET, the workhorse transistor of digital integrated circuits. However, as the feature size is approaching sub-50nm, the scaling of the bulk-si MOSFET faces stiff challenges coming from increased source-drain leakage, increased gate tunneling current, and wide variations in device performance due to uncontrollable channel doping [ITR03]. Hence, researchers are searching for alternatives to the bulk-si MOSFET and its silicon-on-insulator (SOI) counterpart, the partially depleted (PD) SOI MOSFET. Among the alternative devices considered so far, the double-gate (DG) MOSFET [His00] is the most promising candidate to replace bulk-si devices down the roadmap [ITR03]. The DG MOSFET is of the same material as the bulk MOSFET, i.e., silicon, but has a different structure. It offers better control of short-channel effects (SCE) control [Kim01b] arising from the use of two gates with an ultra-thin body (UTB); and high drive current per device width resulting from high mobility due to low transverse electric field and higher inversion carrier density from the two channels. The DG MOSFET need not require drastic changes in the existing CMOS 1

18 2 process technology. Figure 1.1(a) shows a schematic of such a MOSFET. The thin channel is sandwiched between the two gates, one of which is buried in the SOI island. When the properties of both gates (gate workfunction, gate oxide thickness, and bias) are identical, the device is called a symmetric double-gate (SDG) MOSFET; otherwise, it is an asymmetric double-gate (ADG) MOSFET. While the electrical characteristics of the channel of the DG MOSFET are promising, high source/drain resistance (R S/D ) due to the thin silicon and difficulty in aligning the two gates cloud this device s future. An alternate and currently a popular version of the DG device called a FinFET is shown in Figure 1.1(b), where the device of Figure 1.1(a) is basically rotated 90 o. In the FinFET, the gate is "wrapped" over the thin silicon fin that is extended to isolate the gate from the source and the drain. As the gate is one continuous piece, the gate misalignment issue is resolved and the extended fin can be thickened to reduce the high R S/D as well. For SDG design, the two gates remain connected and a thicker oxide layer is used on top of the fin to electrically isolate the top gate from the channel (body). When this is not the case, the device is called a trigate MOSFET [Doy03]. If ADG operation is intended, the top gate is etched off to isolate the two gates, and the device is called an Independent Gate (IG) FinFET, such as the MIGFET [Mat04]. 1.2 Compact Model for the DG MOSFET Whatever form of the DG MOSFET is considered (e.g., ADG, SDG, or IG), for successful advancement of the technology, an accompanying compact model is a prerequisite. A compact model will allow the circuit designers to examine and

19 3 Source Front Gate Drain W y z Substrate Back Gate Oxide (a) Gate Oxide Drain W = h Si x y Source Si- Fin Figure 1.1 (b) Double-Gate MOSFET structures: (a) planar DG structure: body is sandwiched between the two gates [Den96]; (b) FinFET structure: the raised source/drain is isolated from the gate by the thin extension.

20 4 exploit circuits employing DG MOSFETs. This requires the model to be fast enough to simulate large blocks of circuits in reasonable times. At the same time, the model should have sufficient physical basis to allow device engineers to faithfully predict device performance, as well as to obtain reliable insights on the devices fabricated, especially when the technology is still in its infancy. A balance between having a fast and physics-based model is thus imperative; UFDG [Fos04a], a physics/processbased compact model for DG MOSFETs from the SOI group at the University of Florida, eloquently maintains the balance. The model is generic in nature, and can be used for SDG, ADG, and IG MOSFETs, as well as for single-gate fully depleted (FD) SOI devices. In UFDG, the 2D Poisson equation (PE) is solved to get the weakinversion (WI) characteristics [Yeh96]. The 1D PE is combined with the driftdiffusion current equation to obtain the strong-inversion (SI) characteristics [Chi01], and the moderate-inversion (MI) characteristics are obtained using polynomial splines, the coefficients of which are defined by the physical WI and SI solutions at the MI boundaries. In SI, velocity saturation is accounted for by incorporating a simplified form of the Boltzman Transport Equation (BTE) [Ge01]. Quantummechanical (QM) effects are incorporated by solving the 1D PE and effective-mass Schrödinger equation (SE) self-consistently [Ge02a]. The SE is solved using a variational method, and the surface orientation effects are included through properly defining the effective masses and valley degeneracies. The transport formalism has a mobility model [Tri05b] that addresses the different scattering mechanisms, and takes care of thermal injection-limited, or ballistic-like transport. With the

21 5 incorporation of all these physical phenomena, UFDG is evolving as an essential tool for understanding DG MOSFET technology, as well as for predicting circuit performance, and is now in use in industry and academia alike. 1.3 Dissertation Outline In this dissertation, we start with applications of UFDG where device characteristics obtained from industrial collaborators are used to understand and gain physical insights on UTB DG MOSFET operations by systematically calibrating UFDG to them, which then leads to necessary upgrades and enhancements of UFDG. The upgraded model is then used for further calibration, followed by prediction of circuit performances, and their sensitivity to different process parameters. Since UFDG is a physics/process-based compact model, its key model parameters relate directly to device structure and physics. Hence systematic calibration of UFDG requires knowledge of the DG SOI technology. The modelcalibration methodology, which is similar to that of UFPDB [Chi01], a physics/ process-based PD SOI MOSFET model, includes tuning of particular parameters based on only a few electrical measurements of devices. The methodology [Chi01] is expanded and applied in Chapter 2 for preliminary calibration to contemporary FinFET data obtained from two industry collaborators, Freescale Semiconductor and AMD. The insights from the calibrations, along with numerical simulations, are then used in discussing design issues related to nanoscale FinFETs. The preliminary UFDG calibrations to FinFETs done in Chapter 2 reveal new insights into the operation of DG devices, such as different effects of gatesource/drain underlap in weak and strong inversion that necessitate model

22 6 refinements. In Chapter 3, the incorporation of the effects of underlaps in UFDG formalism is discussed. In WI, the underlaps elongate the effective channel length (L eff ) that determines the SCEs, modeling of which hence becomes critical. After a brief description of UFDG WI formalism we thus present a simplified yet physical way of incorporating the effects of underlaps in the WI characteristics. In strong inversion, the underlap does not contribute to the L eff significantly, however it does introduce an additional bias-dependent component to the parasitic source/drain resistance. So, modeling issues and minimizing the effects of such resistance are discussed as well. With proper accounting of the effects of underlaps, the refined version of UFDG, which also has an upgraded QM-based mobility model [Tri05b], is then used for further calibration to contemporary FinFETs in Chapter 4. The focus now, however, is on the carrier transport in the channel of the FinFET, rather than on the electrostatics (as in Chapter 2). Calibration of UFDG to undoped p- and n-channel DG FinFETs shows very high mobilities in contemporary FinFETs, implying smooth {110} fin-sidewall surfaces, and giving new insights on electron and hole mobilities in DG MOSFETs with {110} versus {100} surfaces. The high mobility portends ballistic transport in nanoscale FinFETs, and indeed simulation of 17.5nm DG FinFETs by UFDG shows ballistic-like currents. The high mobility and ballistic-like current indicate low intrinsic channel resistance in FinFET, which indicates FinFET characteristics could be dominated by the parasitic resistances. The effect of parasitics on high intrinsic drive current of the FinFET is thus studied, and compared with that found in bulk-si devices.

23 7 With the needed underlaps in nanoscale FinFETs with undoped UTBs, the sensitivity of device performance gets an added constraint: the source/drain dopants in the extension. In bulk-si technology, the source/drain dopants define virtually bias-independent gate-source/drain overlap length and parasitic resistance. But in FinFET, the bias-dependent effects make the sensitivity of device characteristics to the variations of extension properties, like the lateral source/drain doping profile or the fin thickness, unique. In Chapter 5, the effects of such variations on circuit performances like RO delay and static noise margin (SNM) of SRAM are studied using MEDICI [Med04] and UFDG. In addition, effects of an unintentional dopant (acceptor/donor) in the channel of an extremely scaled device is studied using the 3D numerical simulator, Taurus-MEDICI [Tau04]. While Chapters 2-5 are mainly concerned with the electrostatic and carrier-transport properties in the channel of the DG MOSFET, another important factor, the gate tunneling current, deserves attention. Indeed, the continual increase of gate tunneling leakage with scaling is one of the main factors that initiated the search for a replacement of the bulk-si MOSFET. It is expected that due to the low electric field in the SDG MOSFET the gate tunneling current will be less than that in the bulk-si device. However, with continuous scaling of the oxide thickness, and the unclear direction that integration of high-k dielectrics is taking in CMOS technology, the effects of gate leakage current in SDG MOSFETs requires examination. Besides, the electric field in the ADG MOSFET, unlike that in SDG devices, is not low, and hence gate leakage current in the ADG MOSFET can be a serious issue. In Chapter 6, we thus develop a physics-based compact model for gate tunneling current in

24 8 generic DG MOSFETs. While all the components of tunneling currents in the nanoscale FinFET are considered, only the most dominant component, which is the electron (hole) tunneling current from the conduction (valence) band in the Si of the nfinfet (pfinfet), is modeled physically. The model is verified with experimental data obtained from two different groups, and then is used to examine the effects of tunneling on the static power of scaled DG devices and circuits. The gate leakage model also necessitated a refinement in the UFDG QM model in weak inversion, which is described in the Appendix along with other UFDG upgrades that stemmed from the work of this dissertation. Finally, Chapter 7 provides a summary of the work done in the dissertation, along with recommendations for future work.

25 CHAPTER 2 PHYSICAL INSIGHTS ON DESIGN AND MODELING OF NANOSCALE FINFETS 2.1 Introduction The attractive features of the FinFET, like better SCEs, higher I ON, etc., prompted experimental study of this device and several groups published encouraging results. For example, we show FinFET SCEs as reported in [Yu02] in Figure 2.1, where for a gate length (L g ) of 20nm, and fin thickness (t Si ) of 17-26nm, drain-induced barrier lowering (DIBL) as low as 40mV/V and subthreshold slope, S ~ 75mV/decade are observed. While the excellent SCEs observed with L g /t Si ~ 1 are encouraging, from a device-physics perspective the results are perplexing; mere solution of the PE shows that to have reasonable SCEs (DIBL < 100mV/V, S < 80mV/decade), effective channel length (L eff ) has to be more than twice t Si [Kim01a]. The effective channel length is the length of the channel region, resistance of which is modulated by the gate, and hence, defines the gate-induced variation of MOSFET characteristics, i.e., its switching properties. Ideally, L eff should be equal to the physical gate length, L g. However, from bulk-si experience we know that L eff <L g due to overlaps or encroachment of the source/drain dopants inside the channel [Tau98]; hence the results in Figure 2.1 imply some novel features of the FinFET, including a possible, unique relation of L eff and L g. In this chapter, we attempt to calibrate UFDG to the experimental FinFET data to gain insight into the operation of 9

26 10 Subthreshold Slope (mv/dec) NMOS PMOS W =26nm fin t Si =17-26nm Gate Length (nm) DIBL (mv/v) Figure 2.1 Measured SCEs vs. L g of CMOS FinFETs, reproduced from [Yu02]. Note the extraordinary S and DIBL obtained with L g < 30nm and t Si = 26nm.

27 11 these devices, and to explain the surprising experimental observations. Before discussing the calibration results, we briefly outline the calibration methodology for UFDG. 2.2 UFDG Calibration Methodology Because of UFDG s physical basis, UFDG model parameters are known from process technology, or can be reasonably estimated for initial guesses in the calibration process. The key UFDG model parameters are listed with their default values in Table 2.1. For a complete list of the parameters, please refer to the user guide [Fos05]. Throughout this document, we will show the model parameters in bold face to differentiate them from the corresponding device variables. The parameters not listed here are mostly used with their default values obtained from calibration of earlier-generation SOI technologies [Kris96a], [Chi01] and have not changed with scaling. The evaluation of model parameters starts with setting a preliminary model card based on the technology information. Model parameters, TOXF, TOXB, TSI, NBODY, NSD, WKFG, WKBG, SO, along with gate length (L), and width (W), can be estimated from the process information. However, process variations can significantly change some of the parameters, like NBODY, TSI, etc. One confusion common in literature related to DG devices, especially for FinFETs, is the definition of W (Figure 1.1). In UFDG, the integrated channel charge that naturally includes bulk inversion [Kim04] is used in calculating the drain current. So, width here for a FinFET is simply the height of the FET (h Si ). The more commonly used 2h Si [Yu02], which stems from calculating the current for each channel with the factor 2 taking

28 12 Table 2.1 Key UFDG model parameters with brief description and default values. Model Parameter Description Unit Default TOXF Front-gate oxide thickness m 3.0x10-9 TOXB Back-gate oxide thickness m 3.0x10-9 TSI Si-film (body/channel) thickness m 10.0x10-9 LES Dynamic source-extension length m 0 LED Dynamic drain-extension length m 0 NBODY Si-film (body/channel) doping density cm x10 15 NDS Source/drain doping density cm x10 19 WKFG Front-gate work function V 4.6 WKBG Back-gate work function V 4.6 QMX 1D effective mass parameter for QM 1 UO THETA Low-field mobility for thick TSI (nmos/pmos) Mobility (surface-roughness model) tuning parameter cm 2 V -1 s / VSAT Carrier saturated drift velocity cm s x10 6 VO Velocity overshoot parameter 0 RD Specific drain parasitic resistance ohm m 0 RS Specific source parasitic resistance ohm m 0 SO DG (n-)channel surface-orientation indicator (1: <100>; 2: <110>) Tied-gates indicator (1: Gf and Gb tied; 0: Gf and Gb untied) 1 1

29 13 care of the two FinFET channels, inherently misses an appropriate accounting of the contribution of bulk inversion to the drain current. After setting the preliminary model card, the next step of UFDG calibration is to calibrate the weak-inversion I D -V G characteristics of the device. The short-channel effects are defined by the effective channel length (L eff ), fin thickness (t Si ) and oxide thickness (t ox ), along with body doping. In nanoscale FinFETs, the body is usually undoped and in UFDG L eff is defined by L eff L g L (2.1) where L is the adjustment, usually positive, due to the gate-source/drain overlap, represented by model parameter DL in Table 1. So, by matching SCEs like S and DIBL from the weak-inversion I D -V GS characteristics of nanoscale FinFETs, one can fine-tune the L, DL, TSI and TOXF/TOXB. Once DIBL and S are matched, the WKFG/WKBG can be evaluated by matching the off-state current, I OFF. After evaluating the structural/process-related model parameters from the weak-inversion calibration, calibration of the linear-region, strong-inversion I D -V GS characteristics should follow. At low drain bias there is no velocity overshoot or self-heating effect, so from the strong-inversion, linear-region characteristics, effective mobility, µ eff (defined solely by model parameter UO and THETA) and parasitic resistances, RS and RD, can be extracted precisely. However, as RS/RD can effect the extracted mobility, calibrating the I D -V GS characteristics directly will not yield an accurate effective mobility, especially for a short-channel device. To avoid this, we will

30 14 calibrate g m /I D 2, which is nearly independent of RS/RD [Ghi88], [Kri96]. The total on-state resistance, R ON, in the linear region can be expressed as R ON V DS RS + RD L eff I D W + 2WC of ( V GS V t )µ eff ( UO, THETA) (2.2) where W, C of,v GS, and V t are width, gate capacitance, gate bias and threshold voltage, respectively. The equation is written for symmetric double-gate MOSFETs, but a similar equation can be used for asymmetric DG MOSFETs or bulk MOSFETs as well, by properly changing the gate capacitance value. Differentiating both sides of (2.2) with respect to gate bias, and assuming (V GS -I D RS / W) V GS, we observe that g m /I 2 D is independent of RS/RD. So, by calibrating g m /I 2 D in strong inversion at low V DS the model parameters UO and THETA can be evaluated uniquely. Evaluating RS and RD then becomes straightforward, and can be obtained by simply forcing the model prediction to match the linear region current. (Application of this calibration methodology is illustrated in Chapter 4.) The strong-inversion, saturation-region calibration can be done by tuning VO, VSAT and SELFT in an iterative manner to match I D -V D characteristics. Because of the complex inter-dependence of self-heating on channel current, it s difficult to separate out thermal resistance and capacitances (turned on by SELFT) from velocity-overshoot effects (tuned by VO). However, experience with PDSOI devices show calibration in the above manner is usually effective and less time consuming [Chi01]. The accounting for QM effects, which are gaining importance in shortchannel devices, classical or non-classical CMOS alike, in UFDG usually does not

31 15 need any tuning parameter even though to take care of the uncertainties in effective masses, two model parameters QMX and QMD are left as tunable. However, except for holes in {110} Si, the default values of these two parameters accurately predict the QM effects due to solving the PE and the SE in a self consistent manner [Ge02a]. As the effective masses of holes in {110}-p Si are not conclusively known, the above two parameters require tuning for {110}-p Si. For this purpose, calibration of C-V characteristics is required. The C-V characteristics can also be used to extract TOXF/TOXB; however the advanced gate oxidation process can yield gate thickness with 10% accuracy. For example, if the designed gate oxide is 1nm thick, the maximum variation observed in the thickness after fabrication is ±1Å. As FinFETs are left undoped, such small variation in oxide thickness is not reflected in shortchannel characteristics (unlike bulk-si technology, where large depletion charge, Q D, makes the threshold voltage sensitive to t ox through Q D /C ox ). So, for FinFETs, getting the oxide thickness from the designed value is sufficient, and calibration to simple I D -V G and I D -V D characteristics are enough to evaluate most of the other UFDG model parameters. However, as UFDG does not model polysilicon depletion in the gate, the process is more accurate for metal gate technology, which is the only viable option for undoped-utb DG MOSFETs. With the calibration methodology outlined above, in the next few sections we will present some calibrations of UFDG to both n- and p-channel FinFETs along with insights therefrom.

32 Calibration of UFDG to AMD nfinfets We start our calibration with an AMD fabricated FinFET [Yu02] of L g = 105nm. The body of the device is left undoped and S/D fin extension is doped by 0 o - tilt ion implantation with gate sidewall spacers. The fin thickness varies from 17nm to 26nm, and the extension lengths are of 80nm each. The nitrided gate oxide is 17Å thick with poly silicon used as gate material. The UFDG calibration results are shown in Figure 2.2. Even though a good match in weak-inversion characteristics, subthreshold slope and off-state current, is obtained for L eff = 135nm, which is 30nm longer than L g, the strong-inversion characteristics are not predicted well. Thus, UFDG calibration is only partial. In Figure 2.2(b), the strong-inversion calibration result is shown. With extraordinarily high RS/RD, UFDG predicts the saturationregion characteristics well but underestimates the linear-region current. Although the calibration result in Figure 2.2 is far from perfect, we get two valuable insights from the calibration effort; one is that the effective channel length in the fabricated device is longer than the physical gate length, and the other is that the source/drain resistance (R S/D ) is very high and may be bias-dependent making it impossible to match both linear and saturation-region currents with a constant RS/RD. In Figure 2.3, we show UFDG calibration results for a shorter-channellength device. Again, we find it difficult to match I D (V GS ) in all the regions with constant RS/RD; moreover, in the shorter-channel-length device we observe stronginversion L eff,l eff(st) >L g as well, but it is not equal to weak-inversion L eff,l eff(wk). The observation is in contradiction to that typically observed in bulk-si technology where L eff <L g due to the diffusion of source/drain dopants into the channel. The

33 I D (A) V DS =0.1V measured data V DS =1.2V measured data UFDG (L eff =135nm; R D =R S =200 Ω µm) V GS (V) (a) I D (A) V DS =0.1V measured data V DS =1.2V measured data UFDG (L eff =105nm; R D =R S =675 Ω µm) Figure V GS (V) (b) Partial UFDG calibration to an L g = 105nm nfinfet; t Si = 26nm. In (a) with L eff = L g + 30nm, the measured weak-inversion I D -V GS characteristics are predicted well, but the strong-inversion curves are not. In (b) with L eff =L g, and very high, but constant S/D series resistance, the measured high-v DS strong-inversion I D -V GS characteristic is predicted well, but the low-v DS and weak-inversion curves are not. 1.2

34 L eff = 29.5nm I D (A) L eff =44.0nm V DS =0.1V measured data V DS =1.2V measured data UFDG (R D =100 Ω µm, R S =550 Ω µm) V GS (V) 1.2 Figure 2.3 Partial UFDG calibration to an L g = 17.5nm nfinfet; t Si = 17nm. With L eff =L g nm, the measured weak-inversion I D -V GS characteristics are predicted well; with shorter L eff =L g nm (~2λ D ), and very high source series resistance but low drain resistance, the strong-inversion curves are predicted reasonably well.

35 19 explanation of L eff >L g observed here lies also in the diffusion of source/drain dopants in the channel, however, this time it is due to the lack of it. In FinFET technology, as mentioned earlier, the extensions (Figure 1.1(b)) are not doped directly, rather the ion implanted source/drain dopants are annealed to diffuse them inside the extensions. Apparently, the diffusion is not controlled well enough and an insufficient number of source/drain dopants (N SD ) reach the gate edges leaving the extensions near the gate edges practically undoped. Because of the undoped body and the lightly doped/undoped extensions, the Debye screening length (λ D ) in such FinFETs is long, and gate modulation extends beyond the channel in weak inversion, resulting an L eff, defined as the length over which the gate modulates the carrier, longer than L g. As the channel carrier concentration increases with gate bias, λ D decreases, and carriers beneath the gate screen the carriers in the extensions from the gate-induced electric field. Thus, the L eff shrinks in SI, and hence, even though L eff(st) > L g, L eff(st) < L eff(wk) as found in Figure 2.3. In strong inversion, besides slightly elongating the effective channel length, the lightly doped portion of the extension also increases the series resistance as evident in the high RS/RD obtained in Figure 2.3. However, the uniqueness of this component of parasitic resistance comes from the variation of carrier concentration inside the extension by gate bias, which gives rise to bias dependence of the noted R S/D and renders prediction of strong-inversion current with constant RS/RD ineffective.

36 Calibration of UFDG to Freescale Poly-Gate nfinfets To further corroborate and generalize our insights from AMD FinFET calibration we employed UFDG to calibrate FinFETs fabricated at Freescale Semiconductor. In these devices, the extensions are of 100nm each, physical gate length is 100nm, and from TEM measurements fin thickness is found to be ~ 30nm. The calibration results are shown in Figure 2.4. The weak-inversion characteristics are predicted well with DL = -18nm, i.e., L eff(wk) >L g. The fin thickness is found to be 32nm, 2nm thicker than that is found in TEM measurement. The gate work function inferred from the calibration results in a poly doping density of ~ 4 x cm -3, which is significantly less than what is observed in bulk-si technology. Also the gate-induced drain leakage (GIDL), a common feature in devices with overlaps, is absent in the I-V characteristics of Figure 2.4, which is consistent with the negative DL found from the calibration that indicates instead of overlaps these devices have underlaps. In strong inversion, this time around we tried to observe the evolution of RS/RD with gate and drain biases by incrementally matching the UFDG prediction with the data as shown in Figure 2.4(b). We find that with the increase of gate bias in the linear region, RS/RD gradually decreases due to the fact that an increase of gate bias increases carrier concentration in the underlap regions. At high drain bias, a constant RS/RD results in a good match, indicating a saturation of carriers in the underlap regions. Note that while RS reduces both the effective gate and drain bias, RD only reduces the effective drain bias, and as long as RD is not high enough to

37 V V DS = 50mV I D (A) Measured Data UFDG: L eff = 118nm t Si = 32nm V GS (V) (a) R S =425, R D = V R S =R D =360Ω-µm I D (A) V DS = 50mV Measured Data UFDG: L eff = 100nm Figure V GS (V) (b) Partial UFDG calibration to an L g = 100nm nfinfet; t Si = 32nm, and t ox =2.47nm. (a) Good match in weak inversion is obtained with DL =- 18nm, and (b) the strong-inversion characteristics are predicted well with bias-dependent parasitic resistance.

38 22 drive the channel out of saturation, the saturation region current is independent of RD. The asymmetric RS and RD found from the calibration thus are not necessarily physical. Due to the process symmetry, it is more likely that RS = RD in all bias regions. Also, there is a bit of uncertainty in the magnitudes of R S/D as there might be poly-depletion-induced degradation of the channel current. However, polydepletion effects do not undermine our R S/D (V GS ) conclusions deduced here. Polydepletion effect reduces I D, and it gets worse with increasing V GS [Tau98]. Hence, replicating poly-depletion effect with R S/D will require increasing R S/D with gate bias, which is not the case observed in Figure 2.4(b). So, the trend of R S/D (V GS ) observed here is due to the noted underlaps, and the poly-depletion could only affect the quantitative interpretation of R S/D (V GS ). 2.5 Calibration of UFDG to Freescale Metal-Gate pfinfets In Figure 2.5 and Figure 2.6 calibration results of UFDG to Freescale s metal gate p-channel FinFETs are shown. The gate is TiN and SiON is used as gate oxide in the devices studied. The calibrations are done starting from long-channel devices from which transport parameters are obtained and used for the shorterchannel one, where RS/RD needed tuning to get the strong-inversion calibration. None of the devices have significant SCEs, and the only adjustment needed in weak inversion is for the threshold voltage, which is done by tuning the gate work function. Variation of the TiN gate work function (Φ M ), obtained from the calibration with L g, is shown in Figure 2.7. We find that with decreasing L g, Φ M increases. For the shorter-l g FET, we find Φ M ~ 4.6eV, and for the longer-l g ones,

39 23 I D (A) V V DS = -0.1V Data UFDG L=10 µm, DL=0, TSI=25 nm, UO=275 cm 2 /V.s, RS=RD=0 I D (A) V V DS = -0.1V Data UFDG L=1 µm, DL=0, TSI=25 nm, UO=275 cm 2 /V.s, RS=RD= V GS (V) (a) V GS (V) (b) V V DS = -0.1V V V DS = -0.1V I D (A) Data UFDG L=0.24 µm, DL=0, TSI=25 nm, UO=275 cm 2 /V.s, RS=RD= V GS (V) (c) I D (A) 10-8 Data UFDG L=0.105 µm, DL=-14nm, TSI=25 nm, UO=275 cm 2 /V.s, RS=RD= V GS (V) (d) Figure 2.5 Calibration of UFDG to metal-gate pfinfets with gate length of (a) 10µm, (b) 1µm, (c) 0.24µm, and (d) 0.105µm. All the FinFETs have h Si = 90mn, t ox = 2nm. Key UFDG model parameters are shown in the figure.

40 R S =R D = V 10-6 V DS = -0.1V I D (A) Data UFDG: L eff = 97nm t Si =25nm V GS (V) Figure 2.6 Calibration of UFDG to a 75nm metal-gate pfinfet. Good match in both the weak- and strong-inversion characteristics is obtained with a high R S/ D and UO = 275cm 2 /V.s. The nonzero I D for V GS > 0.0V is due to gate leakage current.

41 Mid-gap gate Φ M (ev) L_drawn (µm) Figure 2.7 Variation of TiN gate work function (Φ M ) with drawn length, (L_drawn) as evaluated from UFDG calibration described in Figure 2.5 and Figure 2.6. For this technology, L_drawn = L g + 10nm 1. The mid-gap gate work function is shown in the dashed line. 1. L. Mathew, private communication, Freescale Semiconductor Inc, 2005.

42 26 Φ M ~ 4.4eV. The findings are consistent with the observations in [Yag98], where it was found that the crystal orientation of TiN varies with the gate length, and for shorter channel length the sputtered TiN has a predominant (100) orientation, whereas for longer channel lengths both (111) and (100) orientations are present. The (100) TiN has a work function of 4.6eV. For the (111) TiN it is eV. So, in shorter-l g devices, the TiN work function it will be ~4.6eV and will be less in the longer-gate-length devices, as observed in Figure 2.7. Note that like the nfinfets, the pfinfets here also have negative DL as found from the calibrations to the shorter-l g devices, and high R S/D. For example, the shortest gate length studied here, L g = 75nm, (Figure 2.6) has DL = -22nm. However, the parasitic resistance is unusually high (RS = 950Ω µm) compared to that found in the AMD devices or the Freescale poly-gate nfinfets. This could be due in part to the lower mobility of holes, and the lesser number of dopants in the extensions compared to that in nfinfets, and/or due to the unoptimized contact formation process. 2.6 Device Design Implications Our calibration of FinFETs fabricated in two different plants shows the presence of underlap instead of overlap in these devices. As the channel is undoped, excessive extension doping measures have to be avoided to prevent punch-through, thus underlap might be a common feature in nanoscale FinFETs. To explore the effects of underlaps on device design, we use the 2D numerical simulator MEDICI [MED04] to simulate the idealized structure in Figure 2.8. The structure is idealized in the sense that we assume there are no dopants in the G-S/D underlap regions (L es/

43 27 t oxf t Si Source Extension y x Front Gate Body Extension Drain t oxb Back Gate L es L g L ed Figure 2.8 Schematic cross section (top view) of the undoped FinFET used in the MEDICI simulations. The undoped portion of the source (drain) extension is defined as L es (L ed ). The devices simulated in this section have midgap gates with L g = 18nm, t Si = 10nm, t oxf =t oxb =t ox = 1nm, unless stated otherwise.

44 28 D ), and N SD (y) goes abruptly to zero in the extension. Energy quantization effects were turned off during the simulation. The default structure is chosen following the ITRS 32nm node MOS structure [ITR03], with L g = 18nm, t oxf = t oxb = 1nm. Figure 2.9 shows the effects of increasing underlaps on (a) subthreshold swing, S, and (b) on gate work function, Φ M, when I OFF is fixed at 0.1µA/µm. As the underlap length increases, the effective channel length increases, which decreases SCEs, and hence S decreases. Also evident in Figure 2.9(a) is (i) that the introduction of underlaps can relax the fin thickness requirements and (ii) that the decrease of S ceases once L es /L ed > 5nm. For example, for S = 85mV/decade, the required t Si = 10nm, with L es /L ed = 0. However, if L es =L ed = 5nm, the same S can be obtained with a thicker fin, t Si = 15nm. Similar conclusions can be made for DIBL as well, as SCEs like S and DIBL vary with t Si t ox /L eff 2 (to first order), for reasonable shortchannel effects [Kim01a]. So, any increase in the effective channel length will allow relaxation of t Si or t ox. As it is difficult to fabricate thin films reliably, underlaps will be a welcome addition to viable FinFET technology. For longer underlap lengths, SCEs are insensitive to L es /L ed (hence, L eff ), as for such cases, the coupling of two gates defined by the fin thickness determines the control of SCEs. Hence we note in Figure 2.9(a) that for longer underlap lengths S is almost independent of L es. The variations of Φ M in Figure 2.9(b) also illustrate that another advantage of introducing underlap in FinFET is that it widens the acceptable range of Φ M. The prominent gate materials in consideration for FinFET technology are nitrides of Ti and Ta. The choice of nitrogen concentrations in both the gate [Wak01] and the underlying SiON determines the work function of the gate. The use of

45 S (mv/decade) t Si = 10nm t Si = 15nm L g = 18nm t oxf = t oxb = 1nm L es = L ed (nm) 4.70 (a) Φ G (ev) I OFF = 100nA/µm L g = 18nm, t Si = 10nm t oxf = t oxb = 1nm L es = L ed (nm) (b) Figure 2.9 Effects of underlaps on the subthreshold characteristics of a FinFET illustrated by the MEDICI-predicted variation of (a) subthreshold swing, and (b) gate work function required to maintain a constant off-state current with varying underlap lengths.

46 30 underlaps thus can add flexibility in the choice of needed nitrogen concentration in the gate or in the SiON. In Figure 2.10, the variation of I ON and I OFF with L es /L ed is shown. Increasing the underlap lengths increases L eff, which reduces the SCEs and hence I OFF decreases exponentially. On the other hand, increasing the underlap lengths increases R S/D and I ON decreases too. Note that for L es =L ed < 4nm, increase of I OFF is abrupt and such sensitivity will prevent reliable design with L es /L ed shorter than 4nm. On the other hand, longer underlap lengths increase the resistance, and have a diminishing effect on SCEs. Hence, from Figure 2.9(a) and Figure 2.10, we conclude that the range of useful underlap lengths for the FinFETs considered here is ~ 4-6nm. Indeed, a pragmatic FinFET design, with a Gaussian source/drain doping profile, proposed in [Tri05a], shows that an optimum 18nm FinFET should have 4.5nm of underlap on each side of the gates. Further discussion on such pragmatic design will be presented in Chapter 5. Note that we refrain from taking any quantitative interpretation of I ON (L es /L ed ) in Figure The transport models in MEDICI that are appropriate for bulk-si are not calibrated for thin-body FinFETs and hence, while the effects of parasitic resistances will be reflected properly in MEDICI predictions, uncertainty in the MEDICI channel mobility/velocity saturation model will introduce uncertainties in the predicted I ON, thus I ON (L es /L ed ) in Figure 2.10 should only be interpreted in qualitative terms. Figure 2.11 shows the effects of asymmetric underlaps on device performance. In Figure 2.11(a) the variations of DIBL and S are shown for increasing

47 I ON I OFF I OFF (A/µm) I ON (ma/µm) L es =L ed (nm) Figure 2.10 MEDICI-predicted variation of I ON and I OFF of the FinFET defined in Figure 2.8 with underlap lengths L es/d ; V DD = 1.2V.

48 DIBL (mv/v) V t (V) V DS =0.1V L es (nm) S (mv/decade) (a) DIBL S L es (nm) V DD =1.2V I OFF (na/µm) I ON (ma/µm) Figure L es (nm) (b) MEDICI-predicted variation of FinFET performance, (a) SCEs, and (b) I ON /I OFF, with the position of the gate in the extension. Simulation is done by keeping the total extension length, L es +L ed constant. Inset in (a) shows the variation of threshold voltage when the gate is moved away from the center (i.e, when L es = L ed = 13nm). 0.0

49 33 L es for a constant L es +L ed = 26nm. For L es =L ed = 13nm, i.e., when the gate is in the middle with symmetric underlaps on both sides, DIBL and S are minimum. Subthreshold slope, which is defined by L eff, and does not depend on the gate position, except when the gate is very near the source/drain, and spilled-over electrons from source/drain reduce gate control by creating an G-S/D overlap region like that in the bulk-si devices (the difference between the overlap region in the bulk- Si device and the FinFET in Figure 2.11(a) is that in the bulk-si MOSFET the overlap region is due to the encroachment of S/D dopants, where as for the FinFET is due to the spilled-over mobile carriers from S/D). Similarly, the off state current in Figure 2.11(b) also remains relatively constant with the gate position. The on-state current, however, is maximum when the gate is near the source, understandably so, as the smaller L es, the less the reduction of effective gate bias by R es, the resistance due to L es. The optimum FinFETs, thus, should have L es > L ed. 2.7 Summary We have presented insights from calibrations of UFDG to FinFET data that explain the good short-channel effects observed in data with L g ~ t Si. The calibration results show that the G-S/D underlap in the nanoscale FinFETs elongates L eff and introduces a bias-dependent component in the parasitic R S/D. We also found that due to the underlaps, GIDL is absent in the FinFET. Design issues with the underlaps were explored through numerical simulations, which show that longer L es/d is needed to minimize I OFF sensitivity to L es/d variations (consistent with the finding that to get good SCEs L eff > 2t Si [Yan05]). Conversely, to keep the resistance low, L es /L ed should be minimum. The

50 34 advantage of underlaps in relaxing the fin thickness and the gate work function requirement was illustrated. Also, probable FinFET design with asymmetric underlaps was discussed, and it was concluded that having a longer underlap length in the drain side is optimum, as shorter underlap length in the source side reduces the reduction of effective gate bias due to the resistive drop across the underlap. The calibration results also pointed out some required upgrades in UFDG, namely modeling of bias-dependent L eff and R S/D due to underlaps. In the next chapter, we will deal with such modeling issues, as well as further applications of UFDG, with the effects of underlaps incorporated.

51 CHAPTER 3 UFDG UPGRADES FOR NANOSCALE FINFETS WITH UNDERLAPS 3.1 Introduction As observed in the previous chapter, the presence of gate-source/drain underlap, with an undoped UTB, introduces variation of the gate-controlled area with bias that gives rise to a bias-dependent effective channel length, and adds a nonohmic component to the parasitic resistance of the FinFET. In this chapter, our focus will be on the analysis and UFDG modeling of such novel features and their effects on FinFET characteristics in both weak and strong inversion. The weak-inversion discussion will be concerned with a modification of the weak-inversion current formalism that is compatible with compact models, while the strong-inversion discussion will center around the properties of the parasitic resistances. In a compact model for a MOSFET, the weak-inversion current is calculated neglecting drift current, and the potential profile in the channel is obtained by solving the 2D Poisson equation (PE) using the depletion approximation. For the FinFET, the gate-controlled region extends beyond the channel and presents different boundary conditions for the PE, which requires extension of the compact model developed for conventional DG MOSFETs. Hence, we first check the applicability of UFDG for predicting weak-inversion characteristics of nanoscale FinFETs, and then the required model upgrades will be presented. Before delving into the FinFET weak-inversion characteristics, we first briefly review the weakinversion current model in UFDG. 35

52 Calculation of Weak-Inversion Current in UFDG Review of Weak-Inversion Current Model in UFDG UFDG solves the PE in weak inversion assuming negligible carriers in the channel [Yeh96]. The effective channel length L eff in the model is the length over which the solution of PE is sought. In DG MOSFETs, L eff is defined by (2.1), where the channel within L eff is completely covered by the gate. The 2D PE, 2 2 qn φ ( x, y) φ A x 2 + ( x, y) y ε s (3.1) with the potential φ referenced to a hypothetical neutral body, is subjected to the boundary conditions shown in the schematic cross-section of a DG MOSFET in Figure 3.1(a). The channel is surrounded by the gate in the transverse direction, and by the highly doped source and drain in the lateral direction. With the gate over the entire effective channel length, the boundary conditions in the transverse direction are clearly defined by the gate-induced electric fields, ε φ ox φ sf ( y) ( V GfS V FBf ) = E x x = 0 sf ( y) = ε s t oxf ε ( V φ ox GbS V FBb ) φ ( y) sb = E x x = tsi sb ( y) = ε s t oxb (3.2) where V Gf/bS is the front/back gate bias, ε ox/s is the oxide/silicon dielectric constant, V FBf/b is the flat-band voltage of the front/back gate, E sf/b is the front/back surface the electric field, and φ sf/b is the front/back surface potential. In the lateral direction, the boundary conditions are defined by the source/drain-channel built-in potential. The inherent assumption here is that source/drain doping is infinite (i.e., the potential

53 37 L/2 (0,0) L g Front Gate Ε sf (y) L/2 (0,L eff ) y Source φ b Channel φ b +V DS Drain L eff (t Si, 0) x Ε sb (y) Back Gate (t Si,L eff ) L es L g L ed (0,L es ) (0, 0) Front Gate (0,L eff -L ed ) (0, L eff ) Ε sf (y) y Source φ b Channel Ε sb (y) (t Si, 0) Back Gate x φ b +V DS (i) (ii) (iii) Drain (t Si,L eff ) Figure 3.1 Boundaries for the solution of Poisson s equation in the DG MOSFET. (a) In a conventional DG MOSFET the boundary conditions are well defined on all four sides by (3.2) and (3.3). (b) In an undoped-utb FinFET, with undoped extensions as part of the channel (of length L es, and L ed ), the boundary conditions are not well defined. From y = L es to L es +L g, the electric fields are easily obtained from (3.2), but from y = 0 to L es,ory= (L eff -L ed )tol eff, the electric fields come from the fringing effect of the gates that complicate the solutions of PE inside the box [(0,0);(t Si,L eff )].

54 38 drop across the quasi-neutral S/D region is neglected), which gives a biasindependent potential at the boundary and defines the boundary values for the PE in the y direction as Ψ( x, 0) = φ b Ψ( x, L) = φ b + V DS. (3.3) A solution of (3.1) subject to the boundary conditions in (3.2) and (3.3) is [Yeh96], φ( x, y) = [( K + φ sinh( γ L eff ) b + V DS )sinh( γy) + ( K + φ b )sinh( γ ( L eff y) )] K. (3.4) Here, γ is the constant (in y) inverse length scale, which indicates the severeness of the SCEs in the channel at any x, and is given as γ ( x) = C of C of γ o C ob C b ; γ C o = of 1 + x x 2 2 2C γ of ε o t b s C b. (3.5) Also in (3.4), K is the 1D potential, found from the solution of the 1D PE in the vertical direction and is related to the gate biases as K γ 2 qn A = CV ( FBb V GbS ) BV ( GfS V FBbf ) ε s, (3.6) where the structure-dependent constants are defined as

55 39 B B o + γ 2 C of ( x) B ε o x 2 = ; B s o = C of C of C ob C b , (3.7) 2 2C of t b C b and C C o 1 + ( γx) 2 2 2C of 1 = ( ); C o = t b (3.8) C b The minimum potential along y at any x, φ m (x), is obtained by solving for y = y m such that the lateral electric field is zero. From (3.4) we find E y and y m as φ y = E y = γ [( K + φ sinh( γ L eff ) b + V DS ) cosh( γy) ( K + φ b ) cosh( γ ( L eff y) )] (3.9) 1 y m = -- atanh γ 1 K + φ b + V DS tanh( γ L cosh( γ L eff ) K + φ eff ). b (3.10) We note that, when V DS =0,y m =L eff /2. Once the minimum potential, φ m is found, the diffusion length, L e in the channel is calculated by, L e L eff L S L D, (3.11) with 2[ φ b φ m ] L S , (3.12) ψ y y = 0 and

56 40 2[ φ b φ m + V DS ] L D (3.13) φ y y = Leff In (3.12) and (3.13), the lengths L S and L D refer to the depletion lengths inside the channel near the source and drain, respectively, as illustrated in Figure 3.2. The channel current is assumed to be due to diffusion only, and is approximated as QL ( S ) V DS I wk qd n 1 exp (3.14) L e V T Here, Q(L s ) is the integrated carrier density at the virtual source and is exponentially dependent on φ m [Yeh96]; q, V T, D n, are electron charge, thermal voltage and diffusion length, respectively. So, the current is mainly dependent on two variables, exponentially on φ m and linearly on L -1 e. In UFDG, the channel is separated into multiple strips along x, and (3.14) is used to calculate the current in each strip [Tri05b]. The total current is then obtained by summing up the contributions of all the strips Source/Drain-Body Junction Potential There are few assumptions in the above model for the weak-inversion current in DG MOSFET. One is the boundary condition (3.3), which says the potential at y = 0 is fixed at φ b, assumed to be the built-in potential V bi and approximated as (for a p-type body), φ b E g kt N A ln , (3.15) q n i

57 41 φ(t Si /2,y) φ m L S /2 L D /2 L e 0 L eff Figure 3.2 Lateral potential profile in weak inversion in the channel of a typical DG MOSFET. The diffusion length L e is obtained by subtracting L S and L D, which are calculated by extrapolating the electric fields at the source/ channel (y = 0) and drain/channel (y = L eff ) boundaries, from L eff.

58 42 i.e., the model assumes the Fermi level in the source is aligned with the source conduction band. In (3.15), E g is the silicon band gap, n i is the intrinsic carrier concentration, and k is the Boltzman constant. For a typical doping density of 1x10 20 cm -3, φ b can be ~ 2kT/q higher than that predicted by (3.15) if Fermi-Dirac (F-D) statistics are used. Besides the inherent approximation of Maxwell-Boltzman (M-B) statistics, (3.15) also assumes that there is no spatial variation of carrier density inside the source/drain. In reality, however, there will always be some carriers spilling over into the undoped channel from the source, and the potential profile in the source will be a function of gate length, film thickness, and biases. A typical profile of φ(y) across the source-channel boundary is plotted in Figure 3.3 showing the deviation of φ b from V bi, the potential inside the source where the carrier density equals the doping density. The inaccuracy, if any, introduced by the assumption in (3.15) that φ b =V bi needs examination before we incorporate the effects of G-S/D underlap. To estimate the potential at the source-body junction accurately, one needs to solve the 1D PE inside the source, 2 d φ q dy ( n ε s N D ) s, (3.16) where N D is the source doping density and n s is electron concentration in the source. In near-equilibrium, for an undoped body, n s can be expressed assuming M-B statistics as [Tau98], φ n s = n i exp (3.17) V T

59 43 N D V bi φ b φ(y) Source Channel N A -y s 0 y m y Figure 3.3 Schematic of variation of lateral potential (solid line) across the sourcechannel boundary in a FinFET with abrupt doping profile (dashed line). Due to finite depletion layer inside the source, φ b < V bi.

60 44 Using (3.17) in (3.16) we find, 2 d φ dy 2 = qn D φ V bi exp , (3.18) ε s V T where V bi is the φ where n=n D. Integrating (3.18) once, and using = 0 at y = -y s, we get dφ dy dφ dy 2 qv T N D φ V bi φ V bi = exp ε s V T V T. (3.19) At the boundary (y = 0), the electric field and potential are continuous, so solutions of (3.1) and (3.16) are nearly the same there. Thus equating (3.9) and (3.19) aty=0wecangetarefined expression for φ b, but the solution requires numerical evaluation. A simpler way is to employ the depletion approximation inside the source and neglect n s in (3.16). Then the potential at the boundary, in terms of the electric field, is 2 ε s E φ b b = V bi ; (3.20) 2qN D E b is the electric field at y = 0 and can be approximated from (3.9) for low V DS as γl E b γ K φ eff ( + b ) tanh (3.21) 2 Replacing E b in (3.20) by (3.21), and solving the resultant quadratic equation we get φ b as

61 45 1 φ b [ ( 2αK + 1) + ( 4αK + 4αV, (3.22) 2α bi + 1) ] where α = εγ h 2 γl eff tan qN D 2 is a constant in y, and relates the dependence of φ b on the device parameters, i.e., N D,L eff, and t Si. Note that in (3.22), φ b depends on the gate bias through K, but the variation is negligible in the weak-inversion region. Figure 3.4 shows the variation of φ b from (3.22) with t Si and L g.asis evident, φ b is independent of L g until the length becomes too small, and punchthrough increases the density of carriers in the channel (and at the boundary, increasing φ b ). With decreasing t Si, φ b decreases as thinner t Si enhances gate control reducing SCEs. In other words, in the 2D PE, de dy qn de = ε dx, the gradient of the electric field along x increases with decreasing t Si, and thus decreases n (so too does φ through (3.17)), for a constant gate length and drain bias. The prediction of (3.22) is in good agreement with that of MEDICI, as shown in the figure, except for thin films, where in the middle of the film the assumed depletion approximation is inaccurate. Also in the figure, the variation of φ b with α is shown in the inset. As α goes to zero (which can happen when N D ), φ b approaches V bi as assumed in (3.3). Note that for a pragmatic FinFET having t Si > 8nm, undoped body, and L eff (= L g here) > 2t Si, φ b is around 0.55 V in Figure 3.5, as will be predicted by (3.15), φ b E g /2 = 0.55V. The prediction by (3.15) is close because the deviation of φ b from V bi is compensated by the use of M-B statistics (instead of F-D statistics), which underestimates the actual potential for source doping ~ 1x10 20 cm -3. So, use of (3.15)

62 L g (nm) φ b (V) 0.40 V bi 0.35 φ b φ b vs. T Si φ b vs. L g Eq. (3.22) MEDICI (0,0) α t Si (nm) Figure 3.4 Comparison of the variation of boundary potential as a function of film thickness (t Si ), and gate length (L g ) as modeled by (3.22) with that of MEDICI. For the first case L g is set to 18nm and for the latter t Si =10nm is used. V GfS =V GbS =0,WKF = WKB =0,V DS = 50mV, t oxf =t oxb = 1nm, N D = 1x10 20 cm -3, and N A =1.3x10 10 cm -3 are used. Inset shows the variation of φ b with α in (3.22); as α 0, φ b V bi.

63 47 works fine for typical FinFETs, although it does not capture the dependence of φ b on structural parameters. (In the next section, introduction of a new parameter SCEB will be discussed, which will help in removing the uncertainties introduced by (3.15), particularly for undoped UTBs.) Weak-Inversion Model Verification for DG MOSFET Figure 3.5(a) shows the calibration of the UFDG weak-inversion model to MEDICI-simulated DG-MOSFET characteristics. The excellent match corroborates the model validity for DG MOSFETs. Figure 3.5(b) shows the comparison of UFDGpredicted φ(y) with that of MEDICI for the same device. Note that both the curves have identical φ m and will yield identical L e. Because the weak-inversion current is mainly dependent on these two parameters, y m, and L e, as long as the calculation of these two are correct in (3.14), UFDG-predicted channel currents, and hence SCEs, will be valid. For conventional DG MOSFETs such accuracy in determining φ m and L e is obtainable by using the exact physical parameters directly in the model. But for the undoped-utb FinFET the model is not directly applicable since the boundary condition in solving the PE is different. Figure 3.1(b) shows the boundaries within which the solution of the PE is sought. While the boundaries in the y direction are still well defined, the boundaries along the x direction in the extensions are defined by the fringing fields from the gates, which invalidate the use of (3.2) there. An exact solution for such a system will involve solving PE in regions (i), (ii) and (iii) in Figure 3.1(b) and equating the solutions at the boundaries of region (i) and (ii), and (ii) and (iii). Such an exact approach is complex and not favorable for compact models. As an alternative, we employ our insight from UFDG

64 I D (A) V DS =1.0V 50mV MEDICI UFDG V GS (V) (a) L g V DS = 50mV 0.5 φ(v) MEDICI UFDG Figure y (nm) (b) Comparison of UFDG predictions with that of MEDICI in weak inversion, (a) I D -V GS characteristics, and (b) potential (φ) along the channel at x = t Si /2. The device is an undoped, mid-gap DG MOSFET with L g = 18nm, t Si = 7nm, and t oxf =t oxb = 1nm. The relevant UFDG model parameters are WKF = WKB = , NSD = 1x10 20 cm -3, DL = -0.4nm, and NBODY = 1.3x10 10 cm -3. For (b) the gate bias is fixed at 0V. Note that in (a) the DL needed is nonzero, due to the uncertainty in the mesh size of MEDICI; the difference of 7mV in the work function can be attributed to the slight discrepancy in the values of intrinsic device parameters, like n i,e g and silicon affinity, χ, used in UFDG and MEDICI.

65 49 weak-inversion calibration that if we can get the correct φ m and L e for this structure (Figure 3.1(b)) by using an equivalent structure like that of in Figure 3.1(a), we can still reliably predict the performance of FinFETs. In the next section, the UFDG model s validity for FinFETs is examined and required upgrades are described based on the insights gained from the MEDICI-simulated FinFET characteristics and UFDG calibrations to those. 3.3 Upgrades in Weak-Inversion Model for FinFET with Underlaps Model Upgrades The nanoscale FinFET (Figure 3.1(b)) structure, from source to drain, is basically a gated n-i-n structure where the undoped portion (undoped/moderately doped extensions plus the channel) is flooded with electrons spilled over from the highly doped source and drain. The application of gate bias in the weak-inversion region modulates the carrier concentration over the entire channel in the process of establishing a drift-diffusion balance. Moreover, as the low carrier concentration in the weak inversion is not effective enough to screen the gate-induced electric field, the gate also modulates the carriers in the undoped extensions. Figure 3.6 shows the MEDICI-predicted variation of potential and electron concentrations between source and drain with gate bias in an undoped nanoscale FinFET for both low and high drain biases. As evident in the figure, in weak inversion gate modulates the carriers in the extensions as well as in the channel. The Debye screening length λ D is given as,

66 50 Potential (V) S L es VGS=1.2V 0.2V 0.0V -0.1V V GS =-0.5V y (µm) L g (a) V DS = 0.1V L ed D Doping Concentration (cm -3 ) Electron Density (cm -3 ) S L es y (µm) L g VGS=1.2V 0.2V 0.0V -0.1V V GS =-0.5V (c) V DS = 0.1V L ed D Doping Concentration (cm -3 ) Potential (V) S L es y (µm) L g V GS =1.2V 0.2V 0.0V -0.1V VGS=-0.5V (b) V DS = 1.2 V L ed D Doping Concentration (cm -3 ) Electron Density (cm -3 ) S L es y (µm) L g V GS =1.2V 0.2V 0.0V -0.1V VGS=-0.5V (d) V DS = 1.2 V L ed D Doping Concentration (cm -3 ) Figure 3.6 MEDICI-predicted surface potential variation between the S and D contact regions of an L g = 105nm DG nfinfet (V t ~ 0) for V GS varying between weak and strong inversion, and for (a) low and (b) high V DS ;t Si = 26nm. Electron density (at x = 0, t Si ) variation corresponding to the potential variation in (a) and (b) is shown in (c) and (d), respectively. The entire S/D fin-extension regions (L es =L ed = 25nm) were left undoped, as was the body/channel. The S/D doping profile is abrupt as shown by the dotted curve.

67 51 λ D = εv T (3.23) qn In weak inversion, usually the carrier concentration n < 1x10 16 cm -3, which makes λ D > 40nm. Such a long screening length allows the gate bias to alter the carrier concentration beyond the channel, inside the undoped part of the extensions. As the carrier concentration goes up near the source (or drain), the gate-induced carrier modulation ceases. If the effective channel length L eff is defined as the length over which the gate modulates the carriers, for nanoscale FinFETs it becomes L eff = L es + L g + L ed, (3.24) where L es and L ed are the undoped parts of the extensions near the gate edges as shown in Figure 3.6 and Figure 3.1(b). Comparing (3.24) with (2.1) we find that L = ( L es + L ed ) (3.25) if the UFDG model is applicable for such FinFETs. To check this conjecture, we calibrate UFDG to MEDICI-simulated FinFETs. The gate length of the device chosen for simulation is 18nm, t oxf =t oxb = 1nm, and t Si = 10nm; it has a mid-gap gate and its body is left undoped. In Figure 3.7 the calibration results are shown. The parameter DL (corresponds to L in (3.25)) in UFDG is tuned to match the shortchannel effects. For (L es +L ed ) = 8nm structure, to get an excellent match in SCEs (DIBL and S), DL is tuned to -6.2nm (Figure 3.7(a)) and for (L es +L ed ) = 10nm, the required DL = -10.4nm (Figure 3.7(b)).

68 52 I D (A/µm) MEDICI UFDG V DS =1.0V 50mV V GS (V) (a) MEDICI UFDG V DS =1.0V 50mV I D (A/µm) V GS (V) (b) Figure 3.7 UFDG calibration to a MEDICI-simulated mid-gap FinFET with (a) L es =L ed = 4nm and (b) L es =L ed = 10nm. Other device/model parameters are L g = 18nm, t Si = 10nm, t oxf =t oxb = 1nm. UFDG model parameter DL is tuned to (a) -6.2nm, and (b) -10.2nm. Quantum-mechanical effects are turned off in both the simulators.

69 53 L es (L ed ), as defined in Figure 3.1(b) as well as in MEDICI simulations, is a rather technological definition, i.e., it is defined as the distance from the gate edge to the plane, where the source (drain) doping falls abruptly to zero. However, L es (L ed ) in (3.24) defines the source (drain) extension length over which the gate effectively controls the carriers. From Figure 3.6 it is evident that near the source (drain), gate does not modulate the carriers due to the shorter screening length there. Thus, (3.24) can be modified as L eff = L es + L g + L ed 2λ D ( n b ), (3.26) where λ D (n b ) is the Debye length corresponding to the carrier concentration at the boundary, n b. The typical value of λ D is ~1nm, corresponding to an average doping density of 1x10 19 cm -3 near the source/drain. Considering this, for shorter L es and L ed in Figure 3.7(a), (3.26) holds true. That is, when the undoped extensions are smaller (~4nm), UFDG is applicable to FinFET structures with its DL indicating the amount of gate underlap. But for longer L es and L ed, the DL required for predicting similar SCEs is almost half of L es +L ed and does not correlate directly to the underlap lengths. Before drawing any further conclusion, we look into the calibration results again in Figure 3.7. It is clear that while UFDG is predicting the SCEs well, it is overestimating the magnitude of the channel current I wk, which is more evident for the longer underlaps. To investigate further we look at the potential profile along y, predicted by both UFDG and MEDICI. Figure 3.8 shows the potential profile for the device in Figure 3.7(a) at low drain bias with V GfS =V GfS =V GS = 0V. While the

70 MEDICI UFDG φ(v) φ(v) y (nm) 0.2 V GS = 0V V DS = 0.05V 0.1 L es y (nm) L g (a) L ed 0.65 L es L g L ed φ(v) MEDICI UFDG V GS = 0V V DS = 0.05V y (nm) (b) Figure 3.8 MEDICI- and UFDG-predicted potential profile, φ(y) (a) along the channel of the FinFET simulated in Figure 3.7(a), and (b) potential profile for the same device as in (a) with the boundary value φ b taken from the MEDICI simulation rather than that predicted by (3.15). Inset in (a) shows the zoomed-in profile near the metallurgical boundary.

71 55 UFDG-predicted profile closely follows that of MEDICI, the minimum potential predicted by UFDG is a few millivolts higher than that of MEDICI, which results in the overestimation of UFDG-predicted I wk, as from (3.14) log(i wk ) φ m. This overestimation is independent of gate bias, which is evident from Figure 3.7, where a shift in the voltage axis towards the right for UFDG-predicted characteristics will yield an exact match of I wk between MEDICI and UFDG simulations, for all the bias points in weak inversion. The expression (3.4) for φ m using y m =L eff /2 for low V DS (from (3.10)), after some algebraic manipulation becomes γ L φ m K φ eff = ( + b ) sech K. (3.27) 2 In (3.27) the bias dependence comes from K. Then, the only parameter that gives a bias-independent variation of φ m is φ b, as dφ m γ L eff =. (3.28) dφ sech b As shown in the inset of Figure 3.8(a), the boundary value of φ b for the UFDG simulation is higher than (as predicted by (3.15)) that of MEDICI simulation. If we use the MEDICI-predicted φ b in the UFDG model, and compare the two profiles of Figure 3.8(a), as shown in Figure 3.8(b), we find that the minimum potential is identical for the two cases. So, the mismatch in I wk in Figure 3.7 is due to the use of inaccurate φ b. To check this conclusion further, the calibrations in Figure 3.7 are repeated in Figure 3.9, where φ b used in UFDG is extracted from the corresponding MEDICI simulation. Excellent matches in I wk, S, and DIBL are obtained, implying

72 MEDICI L es = L ed = 4 UFDG DL = -6.2 V DS =1.0V 50mV I D (A/µm) V GS (V) (a) MEDICI L es = L ed = 10 UFDG DL= V DS =1.0V 50mV I D (A/µm) Figure V GS (V) (b) Recalibration of the 18nm-FinFET in Figure 3.7. The value of the boundary potential φ b used in UFDG is extracted from MEDICI for both (a) the shorter-underlap, and (b) the longer-underlap FinFET.

73 57 that along with the tuned DL, φ b also has to be close to the physical value to predict the characteristics of FinFET reliably. In addition, to get a correct φ m, accuracy in φ b also aids in getting the correct electric field at the boundary. As seen from Eqs. (3.11)-(3.14), L e depends on the electric field at the boundary E b, as well as on φ m. From (3.21), i.e., overestimation of φ b will overestimate E b, which in turn overestimates L e in (3.13), and so underestimates the current. For short-channel devices such overestimation of L e in (3.14) is compensated by the overestimation of φ m. However, for long-channel devices, the minimum potential is mainly influenced by the vertical field and the variation of φ b has a negligible effect on φ m (as evident from (3.28), sech(γl/2) 0asL/t Si becomes large), so overestimation of φ b will mainly result in overestimating L e and thus underestimating I wk. Modeling φ b for FinFETs with underlap, along the lines of (3.22) for nonunderlap devices, requires a numerical solution of the PE in the extension. Nonetheless, we can get a simple model for φ b using our insights from (3.26). As defined earlier, L es (L ed ) is the length from the gate edge to the source (drain) contact where the gate-induced modulation ceases. So the effective channel boundary in the x-z plane is where the carrier density is high enough to give a negligible λ D and is able to screen the source (drain) carriers from the gate-induced field. Looking at Figure 3.6, the carrier density in the extensions where gate bias- de b = γ tanh γl dφ b 2 ; (3.29)

74 58 dependent modulation is negligible is ~ 1 x cm -3. So, the potential φ b at that point can be expressed as and SCEB removing the uncertainties in φ b in (3.31), the description of weak- N D φ b = V bi V T ln , (3.30) n b where n b = 1 x cm -3. The value of n b chosen here varies with the device structure; for example, for severe short-channel effects (i.e., when L eff /t Si is smaller), the electron concentration at the boundary increases due to increased punch-through, yielding an increase in φ b. Besides, the use of M-B statistics also introduces some uncertainty in (3.30). So, we introduce a new user-defined model parameter in UFDG, SCEB such that N D φ b = V bi ( SCEB)V T ln (3.31) n b Values of SCEB are positive and usually lie between 0 and 1. Along with this parameter, we also introduce two more parameters, LES and LED corresponding to the lengths L es and L ed in (3.24). These two length parameters replace the parameter DL in UFDG, but unlike DL, the contribution of LES and LED in L eff is bias-dependent, as we will show in the next section Verification and Utility With three new model parameters, LES and LED defining L eff in (3.24),

75 59 inversion current I wk in (3.14) is now complete for faithfully predicting the weakinversion characteristics of nanoscale FinFETs. In this section we present further calibration results to corroborate UFDG s validity in such predictions. To get the test data, we again use MEDICI. Along with the 10nm-thick-film device, we also simulate a device with thicker film, t Si = 15nm, to check the model s viability for devices with degraded SCEs. In our MEDICI simulations, we use a constant-mobility model to avoid non-physical variations of mobility in the weak-inversion region, which is present in some of the mobility models in MEDICI. Earlier UFDG models, used in this section (a QM-based mobility model [Tri05b], incorporated in the recent UFDG versions, is discussed in Chapter 4), take care of the dependence of mobility on film thickness [Chi01], which is absent in MEDICI s constant-mobility model. To have the similar mobility in both the simulations, UFDG low-field mobility UO is set to 820cm 2 /V.s and 670cm 2 /V.s for t Si = 10nm and 15nm, respectively, whereas in MEDICI, the low-field mobility is specified as 600cm 2 /V.s regardless of the film thickness. Also, quantum-mechanical effects are not included in either MEDICI or UFDG simulations. In Figure 3.10, UFDG calibration to MEDICI-simulated 15nm-thick-film FinFET is shown. UFDG s prediction of I OFF, S, and DIBL are precise for both devices with total underlap of (a) 8nm, and (b) 16nm. In Figure 3.10(a), values of LES and LED are close to those of L es and L ed in MEDICI, implying that for shorter L es and L ed, LES and LED tell us the amount of underlap in the device. For shorter underlaps, the carriers in the extensions are supported by both the longitudinal field and the vertical fringing field from the gate. As seen from Figure 3.11 near the gate

76 60 V DS =1.0V 10-6 I D (A) mV MEDICI L es = L ed = 4 UFDG LES = LED = 2.95, SCEB = V GS (V) (a) 10-5 V DS =1.0V mV I D (A) MEDICI L es = L ed = 10 UFDG LES = LED = 5.55, SCEB = 1.1 Figure V GS (V) (b) Calibration of UFDG to a MEDICI-simulated 15nm-thick fin FinFET with (a) smaller underlaps, and (b) longer underlaps. All other device parameters are the same as in Figure 3.7.

77 61 FG S L g D BG (a) FG S L g D BG Figure 3.11 (b) MEDICI-simulated electric field vector in the x-y plane of the FinFETs of Figure 3.7 with V GfS =V GfS =V GS = 0.1V and V DS = 50mV. The gate is spanned from 50nm to 68nm. In (a) L es =L ed = 4nm and in (b) L es =L ed = 10nm.

78 62 edges, in the extensions, the electric field is 2D in nature, thus (3.1), with its boundary conditions (3.2) and (3.3), holds true, as long as L es and L ed are ~ 4nm or less. The physical nature of the UFDG model for such shorter lengths thus allows us, through LES and LED, to extract the amount of underlaps in the devices directly. Figure 3.11(b) shows the electric field vector for longer L es and L ed. The field is clearly 1D in nature in most parts of the extensions. So, the UFDG model in such cases basically presents an equivalent structure of the device with underlap, where L eff (as in (3.24)) represents an effective length, which allows UFDG to predict the correct diffusion length L e and minimum potential φ m. So, there is no direct correlation between LES and LED with actual underlap in the device where L es and L ed are longer. However, the LES and LED in UFDG can still be effectively used in gathering information regarding the amount of underlap in the device. In Figure 3.12, UFDG-predicted (LES + LED) vs. actual underlap length in the MEDICI (L es +L ed ) simulation is plotted for two different film thicknesses. For both devices, UFDG predicts shorter underlaps quite correctly; for longer underlap cases, its prediction is around 50% of the actual underlaps. From this empirical observation, we thus conclude that for devices with long underlap lengths (> 4nm), UFDG parameters LES and LED roughly indicate half of the underlap lengths. Note that from Figure 3.12, for a particular underlap length, the UFDGpredicted L eff (defined by LES and LED) is almost independent of t Si. It is expected, because if t Si is thin enough to have sufficient gate-control all over the film, then L eff, i.e., the gate control of carriers in the lateral direction, will be independent of t Si. However, if t Si is so thick that the drain has more control of the carriers in the middle

79 (square) t Si = 15nm (circle) t Si = 10nm L g = 18nm t oxf = t oxb = 1nm 1.0 LES + LED (nm) SCEB Total Underlap Length (nm) Figure 3.12 Comparison of UFDG-predicted LES + LED (closed symbols), obtained by calibrating to MEDICI-predicted WI characteristics, with the total underlaps of test FinFETs for two different film thicknesses: 10nm (circles) and 15nm (squares). The tuned SCEB (open symbols) in UFDG for the respective underlaps are also shown.

80 64 of the fin than the gate, we can expect for a particular underlap length, L eff to be smaller compared to that of a thinner film FinFET. In fact in the figure, the thickerfilm device has slightly smaller LES+LED (when L es +L ed < 3nm) compared to the thinner film one, consistent with our understanding of L eff (t Si ). Also, in Figure 3.12 the SCEB required for corresponding underlap is plotted. With the increase of underlap lengths, the required values of SCEB increase. This is because for the longer-underlap devices, the short-channel effects are reduced, thereby reducing the potential at the boundary, and thus necessitating an increase in SCEB in (3.31). Usually the value of SCEB will lie between 0 and 1, as in the figure. But, for long channel devices, or with longer underlaps, it may go beyond Upgrades in Strong-Inversion Model for FinFET with Underlaps Effective Channel Length We observed with gate bias the carrier concentration in the channel (n s ), as well as that in the G-S/D extension (n es/d ) increases. However, as n s reaches ~ cm -3 in strong inversion, it screens the gate-induced electric field, as λ D decreases and prevents gate-induced modulation of carriers in the extension. The phenomena is depicted in Figure 3.6, where we find that gate-induced modulation of n es/d ceases after the gate bias drives the device into the strong-inversion region. That is, in SI there is no contribution of L es /L ed to L eff in (3.26), which in SI shrinks to L eff = L g + 2λ D ( n s ) L g. (3.32)

81 65 With n s ~10 19 cm -3, the contribution of λ D (n s ) in (3.32) is small compared to L g, hence, L eff L g in SI is a reasonable approximation. Indeed in the calibrations in Chapter 2, we have found that L eff L g in SI for longer devices. (The discrepancy in SI-L eff and L g in Figure 2.3 for the 17.5nm FinFET could be due to the high R S/D, which reduces the effective gate bias, i.e., inversion charge, and hence, increases λ D. Also, the longer L eff obtained might also be accounting for the decrease of I D due to the poly-depletion effects.) The validity of (3.32) for shorter channel lengths will be shown later in this section, after discussing the parasitic resistances. Note the difference in the manner L and L es /L ed contribute to the L eff. The overlap always reduces the effective channel length, regardless of the gate biases as evident in (2.1), whereas the underlaps lengthen L eff in weak inversion but do not affect L eff in strong inversion. Such bias dependence is incorporated in UFDG by modeling strong-inversion L eff by (3.32) but ignoring the contribution of λ D (n s ). The shrinking of L eff from (3.24) to (3.32) in UFDG is implicit in the moderate-inversion spline, which is defined by the weak-inversion and strong-inversion currents that are governed by the respective L eff Parasitic Resistance Even though in strong inversion, the extensions do not contribute to L eff, they add an additional component to the parasitic resistance. The concentration of carriers in the extensions that define the resistance is determined by the amount of injection from the source (drain), and the diffusion of electrons from the channel. To develop a first-order model for the resistor we can approximate this carrier concentration in the extensions with an average carrier concentration, n es/d,inthe

82 66 linear region of operation. Then the resistance of the extension, R es/d, assuming drift-dominated conduction, is L es/d R es/d = , (3.33) qµn es/d Wt Si where µ is the carrier mobility in the extension. The average carrier concentration, n es/d, is determined by the carrier concentration on both sides of the G-S/D underlap, i.e., n b and n s (Figure 3.6). The complexity in (3.33) comes from n s, which is a function of the effective gate bias, which in turn depends on the resultant R es/d that reduces the gate bias, V GS by V es/d =I D R es/d. Hence, incorporation of R es/d by (3.33) will require introducing an iterative solution scheme for I D (V GSeff =V GS - V es,v DSeff =V DS -2V ed ), where the initial solution of I D has to be obtained with R es/d = 0, which will also give the initial value of n s, and hence R es/d. Then the updated R es/d has to be used to get I D ; the loop has to continue until a convergence criterion is met. Thus the incorporation of the linear resistance will increase simulation time significantly. In addition to the dependence on V GS,R es/d also depends on the drain bias V DS. With the increase of V DS,I D increases, which in turn increases V es/d, thus the electric field in the underlap increases. As the carrier concentration in the extension n es/d <n s, to support the same I D, the velocity v es/d of the carriers in the extension has to be greater than the velocity v s of the carriers in the channel. With an increased electric field in the extension, v es/d thus increases, and becomes saturated (to a value v sat ) before v s. As such, at high V DS,R es/d saturates and becomes independent of the gate bias, as we have found from UFDG calibration to data in Chapter 2. The

83 67 phenomenon is further illustrated in Figure 3.13(a) where MEDICI-predicted SI-v(y) of a FinFET with long, 27nm of underlap on each side of the gate (the device studied in Figure 2.3), is shown for increasing V DS. At high V DS, both v es and v ed are saturated and are higher than v s.asv es/d v sat, µ 0in (3.33), and thus R es/d saturates to a value higher than that in the linear region. With v es/d =v sat, (3.33) is not applicable for saturated R es/d. Rather, using a quasi-2d analysis, like that done for accounting the channel-length modulation in bulk-si [Man77], we find the expression for the saturated R es/d as L 2 es/d R es/d = (3.34) 2ε Si Wt Si v sat Using the dimension parameters (t Si = 32nm, L es/d = DL/2 = 9nm) of the FinFET in Figure 2.4, and assuming v sat = 5x10 6 cm/s, the voltage drop across the S/D underlap is 0.28V, with I D = 1x10-4 A. From the calibration results in Figure 2.4, R S = 425Ω- µm, assuming 150Ω-µm of it is due to the contacts/sheet resistance, R es/d ~ ( ) or 275Ω-µm, or 3KΩ, which gives a voltage drop across L es,v es =I D R es ~ 0.3V, close to the value that is implied by (3.34). A complete modeling of R es/d (V GS,V DS ) includes smoothing of the linear resistance defined by (3.33) to the saturation resistance defined by (3.34), and then including the model in an iterative scheme to solve for I D (R S/D ), and R S/D (I D ). For pragmatic FinFETs, however, L es /L ed should be short, ~ 4nm, as discussed in Chapter 2, and as demonstrated in [Tri05a]. For such FinFETs, the velocity does not saturate in the extensions as illustrated in Figure 3.13(b). In the figure MEDICI-

84 Electron Velocity (10 7 cm/s) S L es V GS =1.2V L g 1.2V V DS =0.4V L ed y (µm) D (a) Electron Velocity (10 7 cm/s) S V DS 0.4V 0.6V 0.8V 1.0V 1.2V V GS =1.2V L es L g L ed D Figure y (µm) (b) MEDICI-predicted electron velocity along the channel of a FinFET with (a) long extension length, L es/d = 27nm, and t Si =17nm, like that in Figure 2.4, and (b) L es/d = 4.5nm, t Si = 14nm, like the optimum FinFET [Tri05a] discussed in Chapter 5. (In (b) the reduction in velocity in the channel near the drain-end with increasing V DS could be due to the spurious solution of MEDICI energy-balance model.)

85 69 predicted SI-v(y) of FinFET with L es/d = 4.5nm is shown for different drain biases. As the underlap length is not much longer than λ D (n s ), the gate bias can effectively control the carriers in the extensions. Consequently, at high V GS, when n s and I D increase, n es/d increases as well, and can support the increased I D. Also, shorter underlap length reduces V es/d, hence the electric field is also low in the extension. Thus v es/d (and hence n es/d ) does not saturate at high V DS ; instead the carriers in the channel near the drain experience velocity saturation, like that in the typical MOSFETs. Therefore for pragmatic FinFETs, accounting for the saturation of underlap resistance is not needed. The total parasitic resistance (R S/D ) in FinFET is the sum of the contribution of the contact resistance (R co ), sheet resistance (R sh ), and spreading resistance (R sp ) [Tau98], and an additional component R es/d when underlap is present, i.e., R S/D = R co + R sh + R sp + R es/d. (3.35) While in the bulk-si MOSFET, R sp is ~ 20-30% of R S/D, in the FinFET due to bulk inversion [Kim06], R sp is small compared to R co or R sh (as evident from MEDICI simulations). For shorter underlap length, R es/d will be low as well. Dependence of R es/d on L es/d is illustrated in Figure 3.14, where extracted linear resistance from MEDICI-predicted linear I D -V G, is plotted for varying L es. The extraction is done following the channel resistance method described in [Tau98]. As expected from (3.33), the resistance increases sharply with the increase of L es. Also note the increase of R es/d for the thinner fin. We argued that for pragmatic FinFET L es/d ~

86 V DS = 50mV, V GS -V t = 0.85V 200 t Si =8nm R es (Ω µm) ITRS R S/D 14nm L es (nm) Figure 3.14 Extracted linear resistance of an 18nm-FinFET with varying underlap lengths, for two different fin thicknesses. The resistances are extracted from MEDICI-predicted linear I D -V G. Also shown in the figure is the ITRS targeted R S/D for an 18nm-MOSFET [ITR05].

87 71 4nm, and for such cases R es/d is not that high, and the total R S/D will be dominated by R co and R sh. Hence bias dependence of R es/d expected from (3.33), will not be reflected in R S/D. That is, for shorter L es /L ed neither the V GS nor the V DS dependence has a significant effect on the total resistance, and thus, allows us to avoid incorporating the iterative R es/d model described by (3.33) and (3.34). In UFDG thus, the bias-independent model parameter RS/RD is retained to model the resistive-effects of L es/d. This will make UFDG predictions optimistic for FinFETs with longer underlaps, but for pragmatic, shorter L es/d -FinFETs, model predictions will remain acceptable. The validity of retaining the bias-independent RS/RD to account for the parasitic resistance, as well as that of (3.32) to account for SI-L eff, for shorter underlap length is illustrated in Figure With RS = RD =60Ω µm, and biasdependent L eff captured by LES = LED = 3.2nm, UFDG predictions are well in agreement with that of MEDICI for an 18nm-SDG FinFET with 4nm of underlaps on each side of the gate. Excellent match in both the weak and strong inversion exemplifies UFDG s applicability for performance projection of pragmatic nanoscale-utb FinFETs. 3.5 Design Implications With the incorporation of effects of underlaps in UFDG, we now can extend the design study done in Chapter 2. In Chapter 2, we focused on the effects of underlaps on device performance, here we look into their effects on speedperformance of CMOS-FinFETs using a 9-stage FinFET ring-oscillator. The FinFET structure considered is like that shown in Figure 2.8, except for the fin thickness. We

88 V DS =1.0V 50mV 10-5 I D (A/µm) MEDICI L es = L ed = 4nm UFDG LES = LED = 3.2nm RS = RD = 60Ω µm SCEB = V GS (V) Figure 3.15 Comparison of MEDICI- and UFDG-predicted I-V characteristics of a mid-gap gate 18nm-SDG FinFET with underlaps; t Si = 8nm, t ox = 1nm. In both the simulators, carrier-temperature-dependent transport models and QM models are turned off.

89 73 use a pragmatic, thicker (14nm) film [Tri05a]. Also, L es/d is kept relatively short, 0-8nm, as UFDG predictions are more reliable for shorter underlap lengths, and we already concluded that longer underlap lengths are not useful due to high, biasdependent R S/D. Figure 3.16 shows UFDG-predicted variation of RO delay with underlap lengths. The FinFET has L g = 18nm, t Si = 14nm, and a mid-gap gate. In the simulation, R es/d is taken from Figure 3.14, and 100Ω µm is assumed due to contact and sheet resistance. As we do not consider the bias-dependence of R es/d, the delay predicted for the longer underlap lengths, like for L es/d = 8nm is optimistic, but will not affect our conclusion here. Values of the inner fringing parameter FIF shown in the figure are taken from [Kim06]. The effect of underlap lengths on t d is two-fold. With increasing L es/d, I ON decreases (Figure 2.10) due to high R S/D, as well as increased V t, which tends to increase the delay time. On the hand, increasing L es/d decreases the fringing capacitances [Kim06], and thus tends to decrease t d. The former dominates for longer L es/d, and thus we see t d showing a positive slope for L es/d > 6nm in Figure 3.16 (the increase in t d is not that pronounced in the figure due to assumed constant, low R es/d ). The reduction of fringing capacitances dominates for shorter L es/d, and gives an optimum range for L es/d, 4-5nm. In Chapter 2, we reached a similar conclusion considering the device-level performances. Thus a pragmatic, and optimum ITRS 45nm node FinFET with L g = 18nm, should have 4 to 5nm of G-S/D underlap. In Chapter 2, we also found that, if asymmetric L es and L ed are feasible, it is advantageous to have L es <L ed, as such a case offers lower R es and hence less

90 t d (ps) L es/d (nm) RS/D (Ω-µm) FIF L es/d (nm) Figure 3.16 UFDG-predicted variation of ring-oscillator delay (t d ) with underlap lengths (L es/d ). Inset shows key UFDG model parameters used for different L es/d. 100Ω µm ofrs/rd is assumed to be due to the contact and sheet resistance, and the contribution of R es/d (L es/d ) is obtained from Figure Values of the inner fringing parameter, FIF is due to [Kim06]. The devices are undoped {110}-FinFET with L g = 18nm, t Si = 14nm, t ox = 1nm, and Φ M = 4.6eV; V DD = 1V. QM and ballistic-limit model in UFDG is turned on.

91 75 reduction of effective gate bias. In Table 2.1, we show the improvement in RO delay when L es <L ed is adopted over a reference FinFET having L es =L ed = 4nm. For example, when L es = 0 and L ed = 8nm, the improvement in UFDG-predicted t d is 20%. The substantive increase is due to two reasons, one is the noted reduction of R es, and the other is the reduction of gate-to-drain capacitance, C gd with increasing L ed. Increasing L es/d increases the separation between the source/drain plane and the gate, which reduces both the inner and outer fringing capacitances [Kim06]. So, when L ed (L es ) is increased (decreased), C gd (gate-to-source capacitance, C gs ) decreases (increases). Due to the Miller effect, RO delay is more dependent on C gd than C gs [Rab03], and hence, even though having L es < L ed increases C gs, t d decreases due to the decreased C gd, and enhances the speed-performance compared to the L es =L ed design. However, caution should be exerted in designing a device with asymmetric L es /L ed, as when the gate is too close to the source/drain the SCEs degrade (Figure 2.11) and I OFF increases. Moreover, having the source/drain close to the gate edge increases the sensitivity of device performance to the variation of source/drain dopants in the extension, an issue discussed in Chapter Conclusion Due to the presence of underlaps, the effective channel length in nanoscale undoped-utb FinFET is bias-dependent and is greater than the metallurgical gate length in weak inversion. In this chapter, we have discussed complexities presented by underlaps in compact modeling of FinFETs, and upgraded UFDG to account for

92 76 L es (nm) L ed (nm) RS (Ω µm) Table 3.1 UFDG-predicted ring-oscillator delay for an 18nm-FinFET with asymmetric underlaps. Values of R S/D (L es/d ) and FIF S/D (L es/d ) are from Figure 3.16, also other device parameters are the same as in Figure RD (Ω µm) FIF S 1 FIF D 1 t d (ps) At present UFDG does not allow asymmetric FIF; the above values are hard-wired in the code before each simulation.

93 77 the bias dependence of L eff. Also, the modeling of the source-channel boundary potential was discussed for both underlap and conventional non-underlap devices. In strong inversion, the noted underlap does not affect the L eff significantly, but introduces a component to the parasitic resistance. The resistance due to the underlap shows bias dependence as well; it decreases with gate bias in the linear region, but saturates in the saturation region. However, for pragmatic FinFETs having shorter underlap lengths, the bias-dependence of parasitic resistance is negligible and does not warrant a change in the present UFDG formalism that accounts for the parasitic resistance with bias-independent model parameters. Hence, even though modeling of the bias dependence of the underlap resistance was discussed, they were not incorporated in UFDG. However, proper accounting of the bias dependence of L eff was incorporated by replacing the overlap parameter DL, with parameters LES and LED that account for the effective underlap lengths, and modulate L eff appropriately. Model upgrades were verified by comparing UFDG predictions with those of MEDICI s. For both weak and strong inversion, upgraded UFDG predictions were found to be in excellent agreement with MEDICI for pragmatic UTB FinFETs. The proper accounting for the effects of underlaps thus enhanced the reliability of UFDG performance-projection capability for pragmatic FinFET circuits. The upgraded model was then used to extend the design study of Chapter 2 by performing circuit-level simulation. Study of the speed-performance of FinFET- CMOS revealed that the optimum underlap length for a pragmatic, 45nm ITRS node

94 78 FinFET is 4-5nm. Also, UFDG-predicted RO simulation showed that speed enhancement as high as 20% can be achieved if asymmetric underlaps are used.

95 CHAPTER 4 CARRIER TRANSPORT IN NANOSCALE FINFETS 4.1 Introduction In Chapter 2, in the preliminary calibration of UFDG to contemporary FinFETs, we mainly focused on the electrostatics of UTB FinFETs. We found that due to the undoped UTB, the extensions are not doped directly, which in turn results in G-S/D underlaps, resulting in bias-dependent L eff. A more direct effect of leaving the body undoped is that it reduces the transverse electric field, which promises higher channel mobility. In this chapter, with the upgrades done in Chapter 3 (i.e., accounting for the effects of gate-source/drain underlap), and the recently incorporated QM-based mobility model [Tri05a], we present further calibration of UFDG to FinFETs, and insights thereby derived, especially regarding the carrier mobility and transport properties in the channel. Both electron mobility and hole mobility in n- and p-channel FinFETs are studied. The transport parameters obtained from the calibrations are then used to project channel currents of sub-20nm FinFETs, by using UFDG simulations, which involve both dissipative and ballistic transport. With high-mobility/ballistic-limited transport, the FinFET channel resistance is expected to be low, which indicates that the FinFET will be more vulnerable to parasitic resistance. Effects of the parasitic resistance on drive current and ring-oscillator delay are thus discussed by comparing a hypothetical bulk-si device with an SDG FinFET. 79

96 Carrier Mobility in the Channel Electron Mobility in nfinfet For our nfinfet calibration work described here, we chose roomtemperature I D -V GS characteristics of a 370nm-gate-length FinFET with n + -poly gate fabricated at AMD with {110} surface [Yu02]. Calibration of UFDG to the subthreshold characteristics, like subthreshold swing and DIBL, allows us to uniquely obtain two of the three dimension-related parameters, effective channel length L eff (defined by model parameter L, LES and LED, ordl), fin thickness t Si (defined by model parameter TSI) and oxide thickness t ox (defined by model parameter TOXF/TOXB). Hence if the third parameter is known through some other method e.g., oxide thickness from the C-V characteristics, or fin thickness from TEM pictures, etc., a valid calibration can be done. However, for the long-channel device here, with apparently no short-channel effects (SCEs), it is not possible to get unique values for these parameters from UFDG calibration. We mainly thus rely on the manufacturer-supplied information for the values of the device dimensions. The gate oxide thickness used is 17Å, known from the process information [Yu02] and also verified with reasonable accuracy from calibration of shorter-channel devices, as well as C-V characteristics for the same technology [Yu02]. The physical gate length is 370 nm, and with extensions not doped directly, there is no source/gate or drain/ gate overlap and hence DL is set to zero. Underlap length, LES/LED, is assumed to be zero also; however as discussed in Chapter 2, in this device they are actually nonzero and may be ~ 3% of the gate length but their effect is negligible in weak inversion. For the same reason, t Si is assumed to be 26 nm, though TEM pictures of the fabricated device suggest it can vary from 17 nm to 26 nm.

97 Calibration Results The weak-inversion calibration results, with the model parameters listed in Table 4.1, are shown in Figure 4.1, where UFDG predictions are in good agreement with data except for gate bias, V GS < V. In that region, the drain current, I D at high drain bias increases due to gate-to-drain tunneling leakage. Throughout this work the UFDG gate leakage model will be turned off but the QM model will remain turned on. The mobility, on which the subthreshold current is linearly dependent, used in the calibration is extracted from the linear-region, strong-inversion characteristics described later. The gate work function (WKFG/WKBG) obtained from the calibration is 4.073, which indicates a poly doping of 4.5 x cm -3 (using Fermi-Dirac statistics) in the gate. The high poly-doping concentration is consistent with the degradation of capacitances observed in the C-V characteristics in [Yu02], where the degradation of gate capacitance is observed only at very high gate bias, V GS > 1.2 V. Once the dimensional parameters are known through weak-inversion calibration, the next step is to extract transport parameters from strong-inversion calibration. As we have found in Chapter 2, UO and THETA can be obtained uniquely from calibration of g m /I 2 D -V GS, which is independent of R S/D [Ghi88]. In Figure 4.2, we showed the calibration result of UFDG to g m /I 2 D characteristics of the AMD 370 nm FinFET. With UO = 565 cm 2 /V.s and THETA = 0.2, the UFDG prediction is in excellent agreement with data throughout the strong-inversion region, which spans from V GS (N inv ) = 0.3V (5x10 12 cm -2 ) to 1.2V (2.1x10 13 cm -2 ).

98 82 Table 4.1 Key UFDG model parameters extracted from the calibration to 370 nm AMD nfinfet. Model Parameter Description Value L Physical Gate Length 370 nm LES Source-gate underlap length 0 nm LED Drain-gate underlap length 0 nm DL Source/drain-gate Overlap length 0 nm TSI Film Thickness 26 nm TOXF Front gate oxide thickness 1.7 nm TOXB Back gate oxide thickness 1.7 nm WKFG Front gate work function ev WKBG Back gate work function ev UO Low-field mobility 565 cm 2 /V.s THETA Mobility tuning parameter 0.2 RS Parasitic source resistance 390 Ω-µm RD Parasitic drain resistance 390 Ω-µm W Width 50 nm

99 I D (A) V D = 0.1V, measured data V D = 1.2V, measured data UFDG V GS (V) Figure 4.1 Calibration of UFDG to weak-inversion characteristics, I D -V GS of a 370 nm gate length FinFET. Model parameters are listed in Table 4.1

100 Measured Data UFDG g m /I D 2 (10 6 /V-A) µ 0 = 565cm 2 /V-s θ = V DS = 0.1V V GS (V) Figure 4.2 Calibration of UFDG to measured g m /I D 2 vs. V GS at low drain bias. The range of V GS shown is all strong-inversion, as V t -0.1V.

101 85 With the transport parameters obtained from g m /I 2 d calibration, the I D - V GS calibration is now straightforward needing only RS/RD to be tuned. In Figure 4.3 (a), the linear region I D -V GS calibration result is shown. An excellent match with data is obtained with a constant RS = RD = 390 Ω µm. Compared to the extension resistance in the shorter-channel devices, the RS/RD here does not show the expected bias dependence due to carrier modulation in the underlaps by gate bias [Fos03c]. The reason is, in this longer-channel device the channel resistance is much higher and any variation, unless severe, in RS/RD is not reflected in R ON in (2.2). The voltage drop due to RS at V GS = 1.2 V with V DS = 0.1 V is V, which justifies our assumption used in (2.2) for g m /I 2 D calibration that (V GS -I D RS / W) V GS. In Figure 4.3 (b) we show the calibration results at high drain bias. The conspicuous mismatch is due to the fact that UFDG does not consider the variation of transverse field (E x (y)) along the channel and its effect on the mobility. However, compared to the match obtained for a 10µm pfinfet (shown later, Figure 4.8), UFDG predictions are here much better, and get better with increasing V GS. Both of these observations justify our reasoning that the mismatch is due to not accounting for E x (y) degradation along the channel, which ceases with decreasing L g and increasing V GS. Before drawing inference from the values of the parameters, like UO and THETA on the FinFET technology, we will look into the uncertainties that may result in inaccuracies in the g m /I 2 D calibration. The first, is the uncertainty in the film thickness. As mentioned in the weak inversion calibration, for devices with no SCEs

102 I D (ma) I D (ma) 10-6 V D =0.1V, measured data UFDG V GS (V) (a) I D (A) I D (ma) V GS (V) (b) V D =1.2V, measured data UFDG 0.00 Figure 4.3 UFDG-predicted strong-inversion I D -V GS characteristics of AMD 370 nm FinFET: in (a) linear region, (b) saturation region. UFDG model parameters are listed in Table 4.1

103 87 it is difficult to accurately find out what is the actual thickness of the fin, and there is a possibility of t Si varying from 17nm - 26nm [Yu02]. The effect of t Si comes in to play in determining the threshold voltage that affects g m /I 2 D, which is negligible for this long-channel device for the noted range of fin thickness, and the other possible variation may come from the dependence of µ eff on t Si in (2.2), through the dependence of phonon-limited scattering on t Si, but for the noted range of t Si, phonon-limited mobility does not vary much with t Si, especially for high N inv [Tri05b]. So, we can assume that uncertainty in t Si does not affect the calibration results here. The second uncertainty is in the effects of polysilicon doping. Poly depletion can reduce the effective gate bias, and in turn the inversion-charge density. If there is a severe poly-depletion effect, the inversion charge predicted by not taking care of it will be an overestimate, which will give lower effective mobility (to maintain the same amount of drain current). That is, if there is some poly-depletion effect, the UFDG prediction for effective mobility will be lower than the actual mobility values in the device. As the mobility value we get from this {110}-FinFET is higher than that is expected theoretically (discussed later), we do not expect a significant effect of poly depletion on our calibration results as that would mean the mobility values are unrealistically high. To confirm this inference, we use MEDICI to check the effects of polysilicon depletion on g m /I 2 D characteristics for similar device, and the results are shown in Figure 4.4. The simulation clearly shows that for polysilicon doping of 5x10 19 cm -3 (which is approximately the poly-doping obtained

104 g m /I D 2 (µm/va) N poly (1x10 19, 5x10 19, 1x10 20 ) V DS = 0.1V V GS (V) 1.2 Figure 4.4 MEDICI-predicted variation of g m /I D 2 with polysilicon doping. Energy balance and the quantum-mechanical model were turned off. The device dimensions are defined by the parameters in Table 4.1.

105 89 from the weak-inversion calibration), poly depletion has no significant effect on g m / I 2 D, especially at high gate bias Inference on the Electron Mobility The low-field mobility µ 0 obtained from the calibration in Figure 4.2 is low (compared to that of the bulk CMOS) for this nfinfet, that is the mobility in weak inversion is lower, which is beneficial, as it will reduce the off-state current. To identify the mechanism that renders µ 0 low, we briefly describe the mobility model in UFDG. Detailed description (with verification) of the mobility model is published in [Tri04]. The mobility model in UFDG consists of a physical model of dominant scattering mechanisms that are added using Matthiessen s rule to give the effective mobility (µ eff ), which is given as, µ 0 µ = eff, (4.1) µ 0 µ ph( bulk) µ θ µ ph( bulk) µ ph µ sr where, µ µ co µ + others µ = ph( bulk), (4.2) and µ ph, µ sr, µ co, µ others, µ ph(bulk) are the phonon-limited mobility, surfaceroughness-limited mobility, Coulomb-scattering (CS) -limited mobility, mobility due to other scattering mechanisms (for example, remote Coulomb scattering (RCS)), and phonon-limited-mobility in the undoped bulk Si, respectively. The

106 90 model parameters, UO and THETA mentioned earlier, correspond to µ 0 and θ in (4.1) and (4.2). The Coulomb-limited mobility, µ co in (4.2) can be due to the carrier interaction with interface charge or with ionized impurities in the channel. For ultra-thin body (UTB), undoped FinFETs (no impurity atom), the dominant mobility components are µ ph and µ sr, and they are modeled physically in UFDG. The rest, µ co and µ others, are included in the tunable model parameter UO. The third term in (4.2), µ ph(bulk) is added to have a finite upper limit for UO. IfCS or other scattering mechanisms are negligible, µ 0 should be the bulk phonon mobility, which is 1350 cm 2 /V.s for electron. However, from our calibration results here, µ 0 = 565 cm 2 /V.s. Such low value indicates presence of other scattering mechanism in addition to the surface roughness and phonon scattering, and the usual suspect for poly gate is RCS. However, for the 17Å oxide and the N inv range in Figure 4.2, RCS is negligible [Ess03]. CS due to interface states should not be important as there is no evidence of significant interface states in the I D -V GS characteristics. But CS due to donor atoms in the channel resulting from the tail of the source/drain doping profile N SD (y) might be non negligible. The process technology to fabricate this FinFET uses low-temperature annealing of implanted source/drain dopants to get them into the source/drain extensions. The process is not well understood (and hence not well controlled) in ultra-thin body, and the tail of the source/drain doping profile can extend inside the channel. So, even though the channel is undoped, it might contain donor dopants (for n-channel). From our calibration of shorter-channel devices (described in Chapter 2) of the same technology, we know that these FinFETs have ~15 nm of underlap (out

107 91 of an extension length of 80 nm) on both sides of the gate. The length of the underlap is estimated by modeling the effective channel length (L eff ), which is defined as the length over which the gate controls the modulation of electrons, and typically, gate control ceases once the source/drain doping concentration, N SD, reaches ~5x10 18 cm -3. For the longer-channel device, the calibration results for L eff is not unique, so underlap lengths cannot be obtained conclusively. However, as both the shortchannel device and the longer-channel one are fabricated using the same technology, and the extension length is the same for both the cases, we can assume the longerchannel one also has ~ 15 nm of underlap. That is, here, in this FinFET, N SD (y) can drop to ~ 5 x cm -3, 15 nm before the gate edge, and decrease gradually towards the channel, depending on the straggle. For straggle not sharp enough, the tail in the extension can lead to donor doping concentration near the source/drain end of the channel as high as cm -3. If we assume scattering due to other mechanisms are not present, then the low µ 0 can only be explained by the presence of impurity scattering due to the presence of the noted donors in the channel. Mobility due to impurity scattering by an impurity concentration N can be described as [Lun00], µ max µ min µ co = µ min N N α ref (4.3) where, µ min, µ max,n ref, and α are parameters that can be obtained by fitting low-field electron mobility data. From (4.1) and ignoring µ others, µ co = 972 for µ 0 = 565, plugging in this value in (4.3) and using the values of the fitting parameters given in

108 92 [Lun00] for electron in Si, we find the required impurity concentration to give µ 0 = 565 is merely 5.27 x cm -3. Due to the undoped body and polysilicon gate, the V t of the FinFET is low (~ V), and the inversion carrier density N inv is quite high even for low gate biases. For V GS = 0.3 V in Figure 4.2, N inv ~5x10 12 cm -2. If the donor concentration in the channel were uniform and equal to 5 x cm -3, such a high N inv would effectively screen the donors. However, as pointed out earlier, due to Gaussian profile, N SD near the source/drain end of the channel could be high enough to reduce the carrier mobility at high N inv. With the gate bias increasing, the increased inversion carrier density ultimately screens the impurity atoms, and µ co increases and its contribution becomes negligible in (4.2). As UO is a bias-independent model parameter, it does not reflect the screening effect on the ionized atoms, and model parameter THETA has to be adjusted to compensate for the low µ 0 in strong inversion (refer to the last term of the denominator in right hand side of (4.1)). Note, that THETA is intended to be used in UFDG to adjust µ sr and high value of THETA reflects severity of surface roughness scattering. Typical value for THETA is found to be 0.83 (along with UO = 1100) from UFDG calibration to {100}-DG MOSFET data as well as to Monte Carlo simulation of the same [Tri04], but in our calibration result here, it is found to be 0.2, which is partially due to the overestimating of the effects of impurity scattering in strong inversion by using bias independent UO to reflect the bias-dependent µ co. For example, in our case, if µ 0 were 1100 at V GS = 1.2 V, THETA would be However, this is still lower than the value of THETA calibrated from {100} DG MOSFET structures in [Tri04], and suggests that the surface-roughness scattering is

109 93 less severe in {110} FinFET. This is in contradiction to the effects seen in bulk-si MOSFET, where {110}-Si exhibits severe surface roughness scattering compared to {100}-Si [Tak94b]. To explain the decrease of surface roughness limited scattering in {110}- Si we will go through the possible reasons, starting with the possibility of effects of redistribution of carriers in {110}- compared to {100}-Si. Due to subband modulation, charge centroid moves away from the surface in {110}-Si compared to that in {100}-Si. Figure 4.5 shows SCHRED [Vas00] predicted average electron distribution, Ψ 2 avg in the channel for both the surface orientations for the FinFET defined by the parameters in Table 4.1. The average distribution is found by averaging the probability distribution function Ψ 2 of all the subbands (both in unprimed and primed valley) as, 2 Ψ avg = 2 Ψ ijnij ij ij N ij (4.4) where N ij is the inversion density of i-th valley, j-th subband. Only first two subbands are considered from each valley. Compared to {100}-Si, Ψ 2 avg with {110}-Si shows the peak of the distribution to be further away from the surface due to lower effective mass of the 4-fold (unprimed) valley in {110}, suggesting SR scattering might be less in {110}-Si. However, the increased DOS mass of the unprimed valley, which has higher population, increases the scattering rate (through Fermi Golden rule, scattering rate varies with DOS). Hence, the two facts, i.e., (i) lower confinement

110 {100} {110} Normalized Ψ avg Along x (nm) t Si /2 Figure 4.5 SCHRED-predicted average distribution of carriers along the fin thickness near front surface in SDG nfinfets with {100} and {110} surfaces at V GS = 1.2 V; t Si = 26nm, Φ M = 4.073eV.

111 95 mass in the unprimed valley in {110} moves carriers further away from the surface compared to that in {100}, (ii) higher DOS mass in {110}-Si increases the scattering rate compared to {100}-Si, have opposite effects on the mobility. In bulk Si, {110} electron mobility is lower than that in {100} [Tak94b], indicating the dominance of the latter phenomena. For FinFET with t Si ~ 5nm, the former portends pronounced volume inversion in {110} FinFET resulting much higher µ sr compared to that of {100} [Tsu05]. For our case, t Si is rather thick, ~26nm, thus QM effects are not that pronounced to begin with, and as shown in Figure 4.5, the movement of carriers away from surface are minimal for both the surfaces. Hence, the decrease in SR scattering has probably due to the change of surface properties themselves rather than due to the change of carrier distribution. Compared to the {100}-FinFETs [Ess01], the test FinFETs (both the n- and p-channel) here have some added process steps, i.e., uses sacrificial oxides technique to grow gate oxide, and uses SiON as gate dielectric instead of SiO 2. Both of these process changes help in reducing the surface roughness. Experimental observation of oxide/si surface roughness through x-ray reflectometry shows SiON/ Si surface is smoother compared to SiO 2 /Si surface [Gre94], and is found to increase µ sr in bulk-si with SION as well [Tak98]. We thereby conclude that the increased µ sr observed for both the electron (Figure 4.6) and the hole (Figure 4.9) in the calibration results of {110}-Si is due to low surface roughness scattering stemming from the added process steps that resulted in smoother surfaces in the test devices. In fact, such conclusion can be drawn from Figure 4.2 directly, where good match is obtained for all bias range for θ = 0.2. If the low value θ were due to some bias-dependent

112 96 effects (like the carrier redistribution mentioned above, neglect of SR-induced intervalley scattering and ignoring scattering of carriers in higher subbands in the UFDG µ sr model, etc.), we might have needed to vary θ with V GS, as done for the R S/D in Figure 2.4(b). The bias-independent effects in µ sr, to first order, comes from the Si/ SiO 2 properties, and hence constant, low θ (compared to the{100}-si devices) obtained from the calibrating indicates smoother surfaces in the test {110}-FinFETs. In Figure 4.6 UFDG predicted µ n(eff) with µ 0 and θ obtained from calibration, along with µ n(eff) of other contemporary MOS structure is shown. For the same inversion charge the effective mobility of FinFET is almost 2x higher than that of the bulk Si-MOSFET [Tak94] for N inv =7x10 12 cm -2 and will be much higher (~ 4x) at N inv at on state, which is ~ 1 x cm -2. Compared to {100} FinFET mobility data, {110}-FinFET mobility is 25% lower for N inv = 1.9 x cm -2. Also plotted in Figure 4.6, is UFDG predicted mobility for {110} SDG FinFET using µ 0 = 1100 and θ = These values of µ 0 and θ are obtained [Tri05b] by matching array of {100} SDG MOSFET data [Ess01] and found to be typical of undoped {100} DG MOSFET. Comparison of {100}- Si data and predicted {110}- Si mobility (open symbol in the figure) shows that changing the surface orientation to {100} might result in 40% reduction of mobility (at N inv = 1.9x10 13 cm -2 ) due higher conductivity mass in {110}- Si, however the {110} FinFET here shows that the reduction is only 25%, an encouraging improvement due to higher µ sr, discussed earlier. For the same reason degradation of mobility is less severe in {110} FinFET than that of {100} FinFET at high N inv. For decreasing N inv, the degradation of {110} FinFET mobility becomes severe due to low µ 0, i.e., donor impurity scattering. From our calibration

113 µ n(eff) (cm 2 /V.s) V GS = 0.3V V GS = 1.2V {110}-DG FinFET (t Si = 26nm) {110}-DG MOSFET (t Si = 21nm) {100}-DG MOSFET (t Si = 21nm) Bulk-Si MOSFET (N A = 4x10 18 cm -3 ) N inv (10 13 cm -2 ) Figure 4.6 Calibrated UFDG-predicted variation of effective electron mobility with inversion-carrier density (with range of gate voltage indicated) in the {110}- DG FinFET, compared with measured mobilities (points) in {100}-planar contemporary bulk-silicon [Tak94] and DG [Ess01] nmosfets. Also plotted is the UFDG-predicted {110}-DG nmosfet mobility (light curve) corresponding to µ 0 and θ obtained [Tri04] by matching mobility measurements of {100}-planar DG MOSFETs.

114 98 results, it is thus evident that undoped nfinfet with {110}-Si surface can have quite high mobility at on-state condition mainly due to absence of acceptor dopants in the channel and less severe surface roughness scattering and beneficial low mobility in off-state condition possibly due to presence of donor dopants (albeit a low average concentration) in the channel. We note that the reduction of µ n(eff) in the {110} DG FinFET relative to that in the {100} DG MOSFET (0.65x at N inv =10 13 cm -2 ) in Figure 4.6 is less than that measured in [Yan03] for bulk-si MOSFETs (0.33x). This DG versus bulk nmosfet difference, analogous to that noted for pmosfets in the previous section, stems in part from technology differences, i.e., the different dielectrics (SiON and SiO 2 ) of the DG devices compared and, possibly, fin rounding which yields ambiguous crystal orientation of the sidewalls [Lan06]. However, the DG versus bulk differences could also be aided by the different distribution of carriers among the unprimed (UP) and primed (P) valleys in {100}- and {110}-Si. In Table 4.2 we show SCHRED-predicted subband occupation factor, PF (i.e., N ij / N ij ) for both bulk-si and FinFET with {100} and {110} surfaces. From the table, the change in the weighted average m c (m c ) is more in bulk-si then in FinFET when surface is changed from {100} to {110}, leading to more change in µ n(eff) ( m -1 c ) in bulk-si than in FinFET. Also, note the change in the difference between the first two subbands of UP and P valleys for bulk-si and FinFET. For bulk-si, their separation decreases by 55meV from {100} to {110}, where as for FinFET, it is 38meV, which will increase the inter-valley scattering in {110}-FinFET more than that in {110}- bulk-si, for changing the surface from {100}.

115 99 Table 4.2 SCHRED-predicted subband occupation properties of a low doped bulk-si nmosfet and a 26nm thick fin nfinfet at N inv =10 13 cm -2. UP and P denotes unprimed and primed valley respectively, E 11_21 is the separation between the lowest subbands of UP and P valleys, and m c [Ste72] is the conductivity effective mass in free electron mass unit. m c is calculated by taking weighted average of the m c s of all the valleys (v). Device Surface m c Occupation(%) m c = ( PF v /m cv ) -1 E 11_21 UP P PF UP PF P Bulk-Si DG {100} {110} {100} {110}

116 Inference on the SDE Doping From the linear I D -V GS calibration in Figure 4.3 we have found R S/D = 390Ω µm. Assuming drift dominated conduction and 150Ω µm of the resistance are due to contact and sheet resistance, the average doping density in 15 nm underlap of the 80 nm extension required to get the above resistance is ~ 2 x cm -3. Such level of N SD is consistent with our realization that part of the extension is not doped well and along with the interpretation of the extracted low-field mobility values, we conclude that the straggle in the extension is large that leaves a significant N SD (y) tail in the channel. For long-channel devices, average doping density in the channel due to this tail may not be large (as found here from (4.3)), but for short-channel devices the average donor concentration can be high enough to eliminate the advantage of undoped body as far as mobility is concerned. As such, to get the full advantage of FinFET s perfect channel in smaller gate lengths, extension doping procedure needs careful attention not only to avoid punch-trough or high parasitic resistant effects but also to avoid low mobility in the channel Hole Mobility in pfinfet We use near-midgap metal-gate p-channel FinFETs, with {110} sidewall surfaces that were fabricated at Freescale Semiconductor [Mat06] to study the hole mobility in FinFET. The FinFETs were processed on 100nm-thick SOI, using 50nm nitride to pattern the thin Si fins with t Si 30nm and a height (h Si )of 100nm. After removal of a 10nm sacrificial oxide, a 2nm-thick (EOT = t ox ) contemporary gate oxide (i.e., nitrided oxide, or SiON) was thermally grown on the fins, and then 15nm of titanium nitride (TiN) was deposited over the gate dielectric using an optimized

117 101 PVD process. To improve the process conformality, amorphous Si was deposited over the TiN gate, yielding, ultimately, a polysilicon/tin gate stack. The ionimplanted (boron) source/drain (S/D) regions were activated using thermal annealing, which also doped the 50nm fin-extension via lateral diffusion. The fin- UTB was left undoped. The back-end contact/interconnect processing used cobalt silicide and copper Calibration Results Measured device gate capacitance-voltage characteristics, with corresponding UFDG calibration results, for an L g = 10mm pfinfet are shown in Figure 4.7(a). With our focus on hole mobility, we chose the long-channel device to avoid confusing effects of high and bias-dependent R S/D, in addition to enable reliable capacitance measurements. The good match of the UFDG predictions with the measured C G -V GS characteristics is obtained, with t ox = 2nm, by tuning the confinement mass (m x ), and thus m D, in the light/heavy-hole subbands, all of which we found to be 11% heavier than those at planar-{100} Si surfaces. While the increase of both the heavy- and the light-hole mass by the same amount could be fortuitous, the fact that they are heavier is consistent with Monte Carlo simulation results in [Fis03]. Commensurately, N inv vs. V GS is predicted very well as shown in Figure 4.7(b). Then, the linear region I D -V GS characteristics is matched, as shown in Figure 4.8, evaluating µ 0 = 250 cm 2 /V-s and θ = Note that θ, which is found to be ~1.0 for holes in planar-{100} devices [Tri05b], is much smaller here. The gate work function inferred from the calibration, which is consistent with the characteristics in Figure 4.7 and Figure 4.8, is 4.47eV, about 130mV smaller than the midgap work function. The conspicuous mismatch in the high-v DS characteristics in

118 V DS = 50mV 0.02 C G (pf) 0.01 Measured UFDG V GS (V) (a) N inv (10 13 cm -2 ) Figure V DS = 50mV Measured UFDG V GS (V) (b) Results of calibrating UFDG to an L g =10µm pfinfet: measured and predicted (a) gate capacitance-voltage and (b) integrated inversion-carrier density-voltage characteristics. The measured N inv (V GS ) in (b) is derived from integration of the measured C G (V GS ) in (a).

119 V V DS = 50mV I D (A) Measured UFDG V GS (V) Figure 4.8 UFDG calibration to the I D -V GS characteristics of the 10µm-pFinFET. Predicted linear region current-voltage characteristics, along with the results in Figure 4.7, imply the effective hole mobility.

120 104 Figure 4.8 is due to the fact that UFDG does not account for the increasing mobility from source to drain along the channel due to the decreasing ε eff (a long-channel peculiarity), which is also evident in the nfinfet calibration in Figure 4.3. It does not effect the results of this work Inference on the Hole Mobility Figure 4.9 shows the UFDG-predicted (low-v DS ) µ p(eff) vs. N inv for the pfinfet, defined by UO (µ 0 ) and THETA (θ) obtained from the calibration. Also shown in the figure is the directly measured (via the linear I D (V GS ) with N inv inferred from the C G (V GS ), i.e., the split-cv method) hole mobility for the same device, and hole mobility in a planar-{100} undoped DG pmosfet (t Si = 18nm) based on measured data from [Ess00]. For comparisons to classical devices, we include in the figure measured hole mobilities in a contemporary-like {100} bulk-si pmosfet [Tak94a] with channel doping density of 6.6x10 17 cm -3, and in an uncommon {110} bulk-si pmosfet [Yan03] with low channel doping density. The UFDG predictions are in good accord with the direct measurements for N inv > 4x10 12 cm -2, but they offer much more insight as we will show. For low N inv, the measured mobility is lower, which can be attributed to inaccuracy in the split-cv method for moderate inversion. The strong-inversion results are dramatic. For example, at N inv =10 13 cm -2 the FinFET hole mobility is more than 3x-higher than that of the contemporary bulk-si MOSFET, and about 1.5xhigher than that of the planar-{100} DG MOSFET. The superiority over the bulk-si device is due in part to the undoped fin-utb and the low ε eff, but note also that the degradation of mobility with increasing N inv is less severe in the {110}-surface

121 {110} DG pfinfet - UFDG {110} DG pfinfet - measured {100} DG pmosfet - measured {100} bulk pmosfet - measured {110} bulk pmosfet - measured µ p(eff) [cm 2 /V.s] µ 0 = 250cm 2 /V-s θ = N inv [10 13 cm -2 ] Figure 4.9 UFDG-predicted effective hole mobility (curve with µ 0 and θ given) versus integrated inversion-carrier density derived from the DG pfinfet calibration illustrated in Figure 4.7 and Figure 4.8. The directly measured mobility (squares) for the {110}-surface pfinfet is also shown, as well as those (symbols as noted) for a planar-{100} DG pmosfet (t Si = 18nm), based on [Ess00], a contemporary-like bulk-si pmosfet (N D = 6.6x10 17 cm -3 ) [Tak94], and an uncommon {110} bulk-si pmosfet with low channel doping density [Yan03].

122 106 FinFET than in both the {100} bulk device and the planar-{100} DG MOSFET. Further, the FinFET µ p(eff) fall-off is less severe than that in the {110} bulk-si MOSFET, although for low N inv the mobilities in these two devices are comparable. With the low value of THETA inferred, these results imply less surface-roughness scattering of holes, i.e., smoother {110} fin-surfaces, in the pfinfet we examined. Note that like the electron mobility, the change in the hole mobility from {100}- to {110}-pFinFET ( 1.5x) is also less than what is observed from that ( 3x) in the bulk devices [Yan03]. The reason, we believe, is the same as presented in the discussion of electron mobility, i.e., presence of different dielectrics in the FinFETs and affects of subband modulation. However, for the pmosfets, the SiO 2 -to-sion change tends to enhance the noted {100}-to-{110} µ p(eff) increase, suggesting therefore that the m c - and E j -defined benefits of {110} surfaces are less in DG devices than in bulk devices. This suggestion is consistent with our finding of heavier hole masses in the {110}-surface FinFETs. The good match of UFDG-predicted µ p(eff) with that of data in Figure 4.9 attests UFDG s utility as a characterization tool. In fact, use of UFDG to gain information on the carrier mobility is beneficial in two way, (i) UFDG calibration is not restricted to extremely long-channel devices, like the experimental methods: four-probe measurements or split C-V techniques, (ii) the extracted UFDG parameters themselves give insights about the scattering mechanism in the device as demonstrated here.

123 Ballistic-Limit Current While experimental data for the 17.5 nm device is published [Yu02], due to excessive resistive drop in the extensions such data is not very helpful to get insights on the channel properties. We find that the channel of the 17.5 nm gate length FinFET in [Yu02] gets less than 0.1 V of bias across it, when the drain bias is 1.2 V, due to very high R S/D and hence it is not possible to get any useful information on the transport properties of the channel from this device. So, we use UFDG to examine the shorter channel length device, using the transport parameters obtained from the long-channel calibration. If the high mobility observed in the longer channel device remains same in the shorter channel devices, which is possible if the N SD (y) in the channel remains low enough not to effect the mobility at high N inv, then the on-state current in the shorter channel device may be near ballistic. To check how close the on-state current is to the ballistic-limited current we used UFDG to predict the I D -V D characteristics for a 17.5 nm gate length n-channel FinFET and the prediction is shown in Figure The fin thickness is chosen to be 14 nm as device with such thin fin is already fabricated [Yu02] and also gives reasonable shortchannel effects for 17.5 nm of gate length. The underlap length is assumed to be 4.5 nm on both sides of the gate as this is the optimum value of L es /L ed that can be used in such nanoscale FinFETs [Tri05a]. The resistance, R S/D is set to 100 Ω µm, of which 27 Ω µm is due to the 4.5 nm long underlap (extracted from MEDICI simulation). The simulation is done for an effective gate bias, (V GS -V t ) of 0.8 V, as ITRS roadmap for 45 nm node (where the gate length is similar to that one we are

124 w/o I lim w/ I lim 1.50 V GS - V t = 0.8V I D (ma/µm) 1.00 pfinfet nfinfet V DS (V) Figure 4.10 UFDG-predicted current-voltage characteristics, with and without the ballistic-limit current activated, for undoped L g = 17.5nm n-channel and p-channel DG FinFETs. The key model parameters (i.e., UO, THETA, QMX, and QMD) were obtained from the calibrations of UFDG to long- L g {110}-surface FinFETs as reflected in Figure 4.7 and Figure 4.3.

125 109 studying) projects supply bias to be 1.0 V, and the device to have a threshold voltage ~ 0.2 V. The simulation shows that the on-state current, with the mobility extracted from the long-channel device is ~50% higher than the ballistic-limit current for nfinfet. That is, the short-channel FinFET on-state current will be limited by thermal injection only and hence, channel engineering like introducing strain in the channel is not needed to enhance the mobility. 4.4 Effects of Parasitics, and Design Implications For sub-20nm FinFET, we have found that the transport will be ballistic, so there is not much room for channel engineering to increase device performance. Rather, our focus should be on the effects of parasitics. In this section, we illustrate the effects of parasitics, the source/drain resistances and extrinsic capacitances, on FinFETs performance. In addition, we also present comparison of the effects of parasitics on {100}-Si SDG FinFET with that on a hypothetical {100}-Si bulk-si device. The bulk-si MOSFET is simulated using UFPDB [Fos02] and the key model parameters are listed in Table 4.3. The bulk-si device has L eff = 25nm, and is designed to give the corresponding ITRS 65nm node [ITR05] recommended I ON and I OFF, with V DD = 1.1V. The FinFET thickness (t Si = 13nm) and gate work function (Φ M = 4.58eV) are tuned to give the same I OFF as the bulk-si; the transport parameters that are obtained from the calibration of {100}-Si DG MOSFET [Tri04] are used. Note that for the SDG, a thinner fin can be used also to reduce the I OFF without hampering the I ON, as the t Si -dependence of I ON is not significant in the SDG FinFET. The off-state current for both the bulk-si and FinFET is the same, 0.2µA/µm, and the intrinsic I ON is 1.2mA/µm and 2.6mA/µm respectively. For the ring-oscillator simulations, we assume the width of the nmosfet

126 110 Table 4.3 Key UFPDB model parameters used in the study of effect of parasitic resistance and capacitance in Section 4.4. Model Parameter Description Value L Physical Gate Length 25 nm DL Source/drain-gate Overlap length 0 nm TF Film Thickness 20 nm TB Body Thickness 16 nm NBH Body Doping (High) 8x10 18 cm -3 NBL Body Doping (Low) 2x10 18 cm -3 TOXF Front gate oxide thickness 1.2 nm TPS Substrate Poly Type -1.0 TP Gate Poly Type 1.0 UO Low-field mobility 250 cm 2 /V.s THETA Mobility tuning parameter 0.9 QM Quantum-Mechanical effects tuner 0.5

127 111 (pmosfet) is 1µm (2µm), and the length of the source/drain is 0.39µm (6x the 1/2-pitch length). For the nfinfets (pfinfets), we assume there are seven (fourteen) fins per µm of 70nm-height Effects of Parasitic Resistance The saturation current in MOSFET, including the effect of parasitic source resistance R S, can be written as (assuming negligible gate leakage) I D C of ( V GS V T I D R S )v sat, (4.5) where v sat is the saturation velocity and C of is some effective capacitance (the effective capacitance of FinFET is twice that in bulk-si); I D R S represents the reduction of effective gate voltage due the drop across parasitic source resistance, R S. Assuming negligible dependence of v sat on V DS, differentiating (4.5) with respect to R S gives di D. (4.6) dr I D S R S + ( C of v sat ) 1 Eq. (4.6) implies that the effects of parasitics is more severe on the device with higher intrinsic I D, i.e., lower channel resistance. From (4.6), we can deduce that to get the same I ON as that in bulk, the R S needed in FinFET is 1 R s,fin = ----, (4.7) ξ 2 ( R s,bulk + ( ξ 1) ( C of v sat ) 1 )

128 112 where ξ is the ration of I ON of the intrinsic devices. Note that (C of v sat ) -1 is basically the channel resistance of the bulk device (R ch,bulk ), if effective gate drive is 1V. Thus for ξ=2 we can re-write (4.8) as 1 R s,fin = -- ( R. (4.8) 4 s,bulk + R ch,bulk ) For the case in Figure 4.11, R ch,bulk is 917 Ω µm, thus from (4.8), the additional R S FinFET can withstand maintaining the same I ON as that in bulk is 229Ω µm. In Figure 4.11 the degradation of I ON for both bulk-si and FinFET is shown. The intrinsic FinFET has more than 2x I ON than the bulk. With the addition of R S/D, its I ON superiority however decreases, but due its high intrinsic I ON, for a reasonable range of R S/D, FinFET always maintains its I ON superiority over the bulk- Si counterpart. The R S,fin needed to get the same I ON as that of the intrinsic bulk-si device is 225 Ω µm from Figure 4.11, in good agreement that predicted by (4.8). Even though FinFET I ON is higher than that in bulk-si in Figure 4.11, as FinFET has twice the gate capacitance compared to bulk-si, the immediate question that follows is can FinFET maintain shorter logic-delay compared to that in bulk-si. To seek the answer, we simulate a 9-stage ring oscillator with UFDG, and compared the per stage delay (t d ) in Figure Both the devices are assumed to have some bias-independent extrinsic capacitance C ext of 0.2fF/µm. Interestingly, FinFET in spite of twice the capacitance, maintains a shorter delay compared to the bulk-si device, for the range of R S/D considered. The explanation of such performance advantage of FinFET over bulk-si, even with the degradation of I ON with R S/D, lies in the fact that, due to the undoped body, intrinsic FinFET has lower capacitance in

129 Bulk-Si (UFPDB) DG (UFDG) 2.0 I ON (ma/µm) R S/D (Ω µm) Figure 4.11 Effects of parasitic resistance on the on-sate current of (dash-dot line) a bulk-si MOSFET, and (solid line) FinFET; L g = 25nm, t ox = 1.2nm, and V DD = 1.1V. The bulk-si MOSFET is defined in Table 4.3, and the FinFET is an undoped, near mid-gap gate SDG with t Si = 13nm.

130 Delay/stage (ps) Bulk-Si C ext = 0.2fF/µm (UFPDB) SDG FinFET C ext = 0.2fF/µm (UFDG, CFF = 0) SDG FinFET C ext = 0 (UFDG, CFF = 1) R S/D (Ω µm) Figure 4.12 Predicted propagation delays versus parasitic source/drain resistance from UFPDB/UFDG-aided simulations of unloaded nine-stage CMOS-inverter ring oscillator comprising bulk-si MOSFET (dash-dot line)/sdg FinFET (solid lines); L g = 25nm, and V DD = 1.1V. In addition, delay of an SDG FinFET-RO with UFDG fringing-capacitance model turned on (CFF = 1) is shown (line + symbols). For the bulk-si nmosfet (pmosfet) area of the source/drain is assumed to be 0.39pm 2 (0.78pm 2 ).

131 115 weak inversion compared to the bulk-si, which has a significant depletion capacitance in weak inversion. Thus the FinFET integrated CV is not twice of that in bulk, but much less [Kim05], which allows FinFET to maintain the shorter delay even with the degraded drive current. In Figure 4.12 we also show the FinFET-RO t d (R S/D ) with UFDG fringing-capacitance model turned on (line + symbols), instead of using C ext = 0.2fF/µm, which is the typical overlap-c f in present-day bulk-si technology, to replicate the fringing capacitances. With the physical model for C f UFDG-predicted t d is smaller than that using C ext, indicating less severe fringing capacitance in the FinFET (can be reduced further if G-S/D underlap is used, as discussed in Chapter 3) compared to Bulk-Si MOSFET where G-S/D overlap exacerbates fringing capacitances Effects of Parasitic Capacitance With the scaling of feature sizes, the parasitic capacitances in CMOS technology are increasing as the source/drain to gate distance are decreasing. To assess the effects of extrinsic capacitances (C ext ) on the performance of FinFET- CMOS, we plot the UFDG-predicted RO delay for increasing C ext in Figure The UFPDB-predicted RO delay for the bulk-si CMOS considered in Figure 4.11 is included in Figure The C ext includes layout-dependent extrinsic capacitances, as well as outer fringing and inner fringing capacitances (here we kept UFDG fringing-capacitance model turned off). However, fringing capacitances are biasdependent, and their effect decreases with bias [Kim06]. Hence, such lumped, biasindependent, accounting of fringing capacitances make our prediction in Figure 4.12

132 C ext D C ext C ext D 10.0 FG BG G Delay/stage (ps) C ext C ext S FinFET C ext S Bulk-Si 2.0 Bulk-Si (UFPDB) SDG FinFET (UFDG) C ext (ff/µm) Figure 4.13 Predicted propagation delays versus parasitic capacitance from UFPDB/ UFDG-aided simulations of unloaded nine-stage CMOS-inverter ring oscillator comprising bulk-si MOSFET (dash-dot line)/sdg FinFET (solid lines); L g = 25nm, V DD = 1.1V, and R S/D = 140 Ω µm. Inset defines the parasitic capacitance C ext.

133 117 pessimistic. But the insights regarding the comparison will remain valid. As with the R S/D, FinFET-CMOS maintains its performance advantage over bulk-si CMOS for a reasonable range of C ext, due to the noted low intrinsic weak-inversion capacitance. 4.5 Summary By calibrating UFDG, with its QM-based mobility model, to measured data of contemporary DG FinFETs with {110} Si fin-sidewall surfaces, we have shown that hole and electron effective mobilities in undoped fin-utb/channels can be dramatically higher than those in bulk-si counterparts at the same integrated inversion-carrier density. The calibrations further implied unusually smooth fin surfaces, relative to the planar-{110} and -{100} surfaces of test devices in [Ess00], [Ess01], [Yan03], and [Tak94]. Also, the pfinfet calibration revealed heavier (by 11%) hole effective masses than commonly presumed at {100} Si surfaces. UFDG simulations of nanoscale p- and n-channel DG FinFETs then showed that the high mobilities yield on-state currents at the ballistic limits for L g < 20nm. These interesting results suggest that strained-si channels for mobility enhancement are not needed for nanoscale FinFETs. The high mobility/ballistic-limited current indicates low channel resistance of the FinFET, which makes it more vulnerable to parasitic resistance. However, comparison of drive current of a FinFET with that of a hypothetical bulk- Si counterpart MOSFET showed that for reasonable range of R S/D, FinFET can maintain a drive-current superiority over bulk devices, due to its high intrinsic I ON. Ring-oscillator simulations furthered showed that DG FinFET-CMOS can maintain

134 118 a speed-performance advantage over bulk-si CMOS even with added parasitic resistance and capacitance.

135 CHAPTER 5 SENSITIVITY OF FINFET PERFORMANCE TO GATE-SOURCE/DRAIN UNDERLAP PROPERTIES 5.1 Introduction In previous chapters, we observed that nanoscale FinFETs having ultrathin bodies (UTB) can have underlaps that can be used beneficial in optimizing performance. The UTB is required for better charge-coupling between the two gates [Kim01b], as well as for controlling the short-channel effects (SCEs). However, the UTB, along with the technologically limited fin height (h Si )-to- thickness (t Si ) ratio (r f ), makes the channel volume too tiny to allow faithful placing of a sufficient number of dopants in the channel. To avoid this problem, an undoped body and use of tuned gate work function are prescribed [Fos04b]. The undoped/intrinsic UTB facilitates high carrier mobility, but it portends the possibility of S-D punch-through when the SDEs are heavily doped to minimize extrinsic S/D resistance (R S/D ). To prevent such punch-through, the SDEs are not doped directly; rather diffusion is facilitated through annealing of the ion-implanted source/drain, which when uncontrolled, leave a long underlap region on either side of the gate, as we observed in Chapter 2. However, by controlling the diffusion in the extension, the underlap length can be controlled and be used as a critical device design parameter, as discussed in Chapter 3. In [Tri05a] an optimized FinFET for the ITRS 45nm node [Fos04b] is presented, utilizing the beneficial underlaps through controlling the lateral doping 119

136 120 profile (N SD (y)) in the source/drain extension (SDE). As the extensions share the same width and height with the channel (unless it is flared out), the logical questions that follow (noting that in bulk-si, controlling the dopants in the channel is getting increasingly difficult) are how well can the doping in SDE be controlled and how will the variation in N SD (y) affect the device performance. While the answer of the first part is not known conclusively, the expectation is that near the gate edges, for the UTB devices, the doping will become random, and in this chapter we look into the effect of such randomness on the performance of FinFETs. In addition, we will also look at the sensitivity of performance of FinFETs to the variation of other device parameters that affect the underlap properties. For the purpose of this sensitivity study, we use the optimum FinFET in [Tri05a] as the reference device, which is of 18nm gate length, requires a pragmatic, Gaussian doping-density profile N SD (y) with 9.5nm straggle (σ L ), and has a 20nm long extension (L ext ). The film thickness (t Si ) of the device is 14nm. In FinFET technology, limitation in etching processes and mechanical stability requirements limit the fin aspect ratio, r f =h Si /t Si ; and a typical r f is 4. The small dimensions in both h Si and t Si mean that the number of dopants in an incremental volume of the SDE is also low. For example, for the design in [Tri05a], to have one atom in a one Silattice constant (a Si ) thick slice, the required doping density is 2.3 x cm -3.In Figure 5.1, we have plotted the number of dopants in the y-direction, from source to drain, corresponding to the doping profile proposed in [Tri05a] for the optimized FinFET. To get the number of dopants, we approximated the Gaussian N SD (y) with a series of step functions of width a Si. The doping density in each step, N step, is the average value of the doping concentration from the original profile for that step. The

137 Doping Concentration (cm -3 ) Source Gaussian Profile Step function appr. L eff L g Drain Number of Dopants Distance along y (nm) 0 Figure 5.1 The lateral S/D-extension doping concentration N SD (y) proposed in [Tri05a] for the optimum DG FinFET at the ITRS 45nm-node. The number of dopants are calculated within a slice of volume h Si t Si a Si, where a Si is the silicon lattice constant, and h Si is assumed to be 4t Si. The N SD (y) profile is approximated as the sum of step functions to obtain the average dopants within each slice.

138 122 number of dopants per segment then comes from N step xv slice, where V slice is the volume of a slice in the S/D extension of width a Si. Note in Figure 5.1 that near the gate the number of dopant is ~1 atom/slice or less than that. When the actual number of dopants is this low, the whole diffusion process becomes a random event. That is, even though the doping profile in the S/D extension is continuous Gaussian here, in reality, near the gate it will become a discontinuous random function. Hence, there may be a significant variation of S/D doping in the extension from device to device. Study of such randomness of dopants is usually done using atomistic simulation [Ase98] of a large sample of devices with the objective of obtaining statistical fluctuation parameters. However, our focus here is to assess the viability of introducing underlap as a design parameter, rather than obtaining an accurate quantitative picture. Hence, we look at the extreme cases of variation using a 2D numerical simulator, MEDICI [MED04], in conjunction with our physics/process - based compact model, UFDG [Fos04a]. MEDICI solves the 2D Poisson equation accurately, however its transport model, or the quantum-mechanical model, is not calibrated nor verified for the UTB devices. Fortunately, the reference FinFET has thick enough film (one of the advantages of having underlap, as used in [Tri05a], is that it relaxes the fin thickness requirement; see Chapter 2) so as not to have our conclusions be undermined due to the noted deficiencies of the numerical simulator. When looking at the sensitivity of I ON, I OFF or V t on various process/device parameters, we thus use MEDICI, but when we are looking into the effect of such variation of circuit performance, like ring-oscillator (RO) delay (t d ) or static noise margin (SNM) of SRAM, we use UFDG for both projection accuracy as well as time-

139 123 efficiency. UFDG transport and QM models are perfected for UTB devices, but being a compact model, it does not comprehensively solve Poisson s equation for arbitrary N SD (y). Hence, we first use UFDG to calibrate MEDICI-predicted weak-inversion characteristics of devices with different N SD (y) to obtain the equivalent device. Once the equivalent device is found, we turn on the QM mobility model and ballistic limit model [Tri05b] in UFDG to project the t d and SNM. The values for UFDG transportmodel parameters are obtained from UFDG calibration to experimental FinFETs fabricated at Freescale Semiconductor (see Chapter 2 and Chapter 4). The source/ drain resistance due to the G-S/D underlap, as well as the extension, is extracted from MEDICI following [Tau98]. In the next few sections, after defining the reference device, variations of its characteristics, and its speed and SRAM performance, due to the variations in the critical device dimensions like t Si,L g and process parameters like straggle, and the effects of randomness of the N SD (x,y), are presented. 5.2 Reference FinFET After choosing the pragmatic device presented in [Tri05a], which is designed for the ITRS 45 nm node (L g = 18 nm) [ITR03], as the reference device, the first problem is to know the L eff of the device. The effective channel length for FinFET with underlap is bias-dependent, as shown in Chapter 2, and is modeled by (3.24) and (3.32) in weak and strong inversion respectively. For completely undoped, shorter extensions, L es (L ed ) in (3.24) is approximately equal to the length of the undoped part of the extension. However, for devices with moderately doped extensions (possible with N SD (y) similar to that in Figure 5.1) the relation of L es (or L ed ) with extension length (L ext ) and σ L is non-trivial (a discussion on the relation

140 124 of L es /L ed with σ L and L ext is presented in [Tri05b]). For this work, we circumvent the problem of obtaining L eff in (3.24) for devices with non-abrupt N SD (y) by employing UFDG to calibrate the MEDICI-predicted characteristics of the device represented by N SD (y) in Figure 5.1. In Figure 5.2, the calibration result for the weak-inversion characteristics of the reference device is shown. UFDG predictions are in excellent agreement with MEDICI-simulated results for L eff = 27nm, and using (3.24) we get L es =L ed = 4.5 nm. Note that the underlap lengths are within the range of the optimum underlap length found in Chapter 3. Our reference device is now well defined, with L eff = 27nm, L g = 18 nm, t Si = 14 nm, t oxf =t oxb = 1 nm, h Si =4t Si, undoped body, mid-gap gate, and with the N SD (y) shown in Figure 5.1. For the reference design with V DD = 1.0 V, MEDICI predicted I OFF is 14 na/µm, I ON is 1.16 ma/µm, and the threshold voltage (V t ) is 215 mv. Once the equivalent device structure is obtained from the calibration, we turn on UFDG QM model, and use transport parameters obtained from earlier calibration results to predict circuit performance. In UFDG simulation, MEDICIextracted R S/D of 98 Ω-µm is used that includes the resistance due to the G-S/D underlap (R es/d ) and sheet resistance of the highly doped extension; however it does not consider the contact resistance. The UFDG-predicted FinFET performance parameters are V t = 235mV, I OFF = 6.3nA/µm, I ON = 1.21mA/µm. The difference between UFDG and MEDICI predicted V t (and I OFF ) is due to the use of lower lowfield mobility value used in UFDG and consideration of the QM effects in UFDG. The I OFF projected is well below the ITRS target [ITR03], which is 100 na/µm for

141 I D (A/µm) MEDICI UFDG V DS = 1.0V 50mV V GS (V) Figure 5.2 Partial calibration of UFDG to MEDICI-predicted characteristics of the reference device. Very good agreement of weak-inversion characteristics between UFDG and MEDICI are obtained for L eff = 27nm.

142 126 the 45nm node high performance (HP) devices, but the I ON does not meet the ITRS target of 1.9mA/µm. UFDG predicted RO delay for the noted design is an impressive 2.78 ps and the SRAM static noise margin (SNM) is 178mV. The design of the SRAM circuit cell follows that of [Zha06], which is focused on maximizing SRAM cell density, not necessarily optimizing the performance. The RO circuit delay might also differ depending on the chosen parasitic capacitance value. We used a pessimistic 0.16fF/ µm capacitance per gate-source (drain) to account for the effects of fringing (both inner and outer fringing) and parasitics. Layout-dependent, back-end process related capacitances were not considered. Note that in this sensitivity study, we allow all the FETs in the RO (Figure 5.3(a)) or the SRAM (Figure 5.3(b)) to vary in a similar fashion, which might not be the case in reality. However, devices in close proximity in the wafer tend to vary in a similar fashion. (For example, doping concentration in the middle of the wafer tends to be higher than that near the edges, hence the devices in the middle tend to have higher number of dopants than the mean.) Moreover, SRAM cell stability, to first order, depends on the threshold voltage of the driver FET (pull-down), V DD, and W/L ratio of access and driver transistor [See87]. As our focus is on the effects of variation of extension parameters that does not affect V DD and W/L (the L here is the strong-inversion L eff, from (3.32), which is independent of the underlaps) ratios, such an en mass variation of FinFETs in the cell is reasonable.

143 127 V DD M pu M pd (a) WL V DD M2 M4 M5 Access V L V R M6 Access Driver/ pull-down M1 M3 Driver/ pull-down BL BL Figure 5.3 FinFET-CMOS circuits used in the sensitivity study, (a) one stage of the 9- stage RO, and (b) the 6T SRAM cell [Zha06]. For the RO circuit, the W/L ratio, M pd /M pu is assumed to be 2, and for the SRAM, M1/M5 (or M3/M6) is assumed to be 1 (not necessarily optimized for stability). (b)

144 Effects of Variation of Film Thickness One of the pragmatic features of the optimum device discussed here, as mentioned, is that it employs a relatively thicker Si film, which is much easier to fabricate. However, the variation in t Si is unavoidable during fabrication due to systematic process variations, like mask defects, global variations, like process-tool bias, and local variations, like etching mismatch. In UTB devices, film thickness determines the severity of SCEs, quantum-mechanical (QM) effects, phonon-limited mobility, bulk inversion, and the source (and drain) series resistance, R S (and R D ). For the thickness we are concerned here, the thickness dependence of the bulk inversion is somewhat irrelevant [Ge02b], phonon-limited mobility is insensitive of the thickness [Tri05b] and QM effects are negligible for weak/moderate inversion [Ge02b]. Hence, in weak inversion we expect the V t and the I OFF to vary with the t Si due to the variation in SCEs, and in strong inversion, the I ON to vary mainly due to the variation of V t and R S/D. In Figure 5.4, MEDICI-predicted variation of (a) V t, (b) I OFF and I ON due to variation of t Si are shown. For 10% increase in t Si, increased SCEs decrease threshold voltage by ~20% and increase I OFF by a factor of four. Even though variation of I OFF is sharp, as the I OFF for the reference device is quite low (for HP devices), the effect of variation of t Si on I OFF is tolerable. A 10% increase (decrease) in t Si increases (decreases) I ON by 4%, which is due to the decreased (increased) V t mainly, as the change of R S/D due to the change of t Si is minimal.

145 Variation of V t (%) (a) 10.0 Ratio of I OFF to I OFF(ref) Variation of I ON (%) (b) Variation of t d (%) Variation of SNM (%) Variation of t Si (%) (c) Figure 5.4 Sensitivity of FinFET performance-parameters with the variation of t Si. (a) MEDICI-predicted variation of threshold voltage, (b) variation of I OFF and I ON and (c) UFDG-predicted variation of t d and SNM with t Si.

146 130 Figure 5.4(c) shows the UFDG-predicted variation of t d and SNM with t Si. The effect of t Si variation is, relatively, less severe on t d, for 10% variation in t Si ; the maximum variation observed is 8%. The SNM, which follows the threshold variation, shows a maximum of 12% variation due to 10% change in the t Si. The variations in the delay comes from the variation of current with t Si,ast Si variation has insignificant effect on the gate capacitance, C G (for the noted t Si range). Note that in the CV/I delay metric, the current I is not simply the I ON, rather it is some average of linear and saturation current [Na02]. As the linear current is more sensitive to R S/D (t Si ) variation (compared to I ON ), the variation in t d (t Si ) in Figure 5.4(c) is more than that of I ON (t Si ) in Figure 5.4(b). 5.4 Effects of Variation of Gate Length As the case with bulk-si MOSFET, gate is still the major determinant of the SCEs in UTB devices. Effects of variation of gate length can be studied in two ways, one by keeping the distance between the source to drain (2L ext +L g ), constant and varying the gate length; and in the second case, by keeping the extension lengths constant while letting L g vary. The first kind, which is absent in the present-day technologies, is studied with MEDICI in Figure 5.5, where we only take a look at the device level effects of variation of gate length while keeping distance between source and drain fixed. As expected, increased (decreased) SCEs with decreased (increased) L g decreases (increases) V t, and increases (decreases) I OFF. However, interestingly, the on-current increases with the increasing gate length (contrary to the typical L -1 eff dependence of I ON ). Increase of gate length decreases L es/d and hence the resistance R es/d decreases, which causes the increase in the I ON. A maximum of 12%

147 Variation of V t (%) (a) Ratio of I OFF to I OFF(ref) Variation of I ON (%) Variation of L g (%) Figure 5.5 Sensitivity of FinFET performance-parameters with the variation of L g. MEDICI-predicted variation of (a) threshold voltage, (b) I OFF and I ON (bottom) with gate length. The source to drain length was kept constant (L g + 2L ext ). (b)

148 132 variation in I ON is observed for a 10% variation in L g, where as the I OFF can increase by 3x for the same amount of change in L g. The second type of gate length variation, where the extension lengths are insensitive of the gate length variation, is more realistic. Because in state-of-the-art technologies, the extension lengths are defined by the spacers, length of which is independent of L g -variation. For this type of variation, the doping profile in the extension remains unchanged, i.e., L es /L ed and R S/D remain unchanged. So, we can still expect variation in I ON and I OFF, however in lesser magnitude. In Figure 5.6 MEDICI-predicted variation of V t (Figure 5.6(a)), I OFF and I ON (Figure 5.6(b)), and t d and SNM (Figure 5.6(c)) with the variation of L g is shown for this case. For a 10% variation in the gate length, a maximum of 20% variation in V t is observed, which in turn changes the I OFF by 4x. The maximum change in I ON is merely 0.5%. However, the maximum change in t d is 5%, reflecting mainly the variation in C G due to the variation in L g. For 10% change in L g, the maximum change observed in SNM is 12%, (follows the change in V t ). 5.5 Effects of Variation of Lateral Straggle Like the device dimensions, the lateral straggle can also vary from device to device, die to die, and chip to chip. Lateral straggle defines the L eff [Tri05a], and affects the R S/D. Hence, both the strong- and weak-inversion performance parameters are expected to vary with σ L. Figure 5.7(a) shows the variation of UFDGpredicted L eff and MEDICI-predicted V t with the variation of σ L. A 10% increase in σ L decreases V t by 23% and increases the I OFF by ~ 6x (Figure 5.7(b)), whereas a 10% decrease in σ L increases V t by 15% and decreases I OFF by 3x. Here the

149 Variation of V t (%) (a) Ratio of I OFF to I OFF(ref) Variation of I ON (%) (b) Variation of t d (%) Variation of SNM (%) Figure Variation of L g (%) (c) Effects of varying L g, but keeping L ext constant, on the sensitivity of FinFET performance. MEDICI-predicted variation of (a) threshold voltage, (b) I OFF and I ON, and (c) UFDG-predicted t d and SNM variations with the variation of gate length are shown in.

150 Variation of L eff (%) Variation of V t (%) -20 Ratio of I OFF to I OFF(ref) R S/D (%) σ L (%) (a) (a) (b) Variation of I ON (%) Variation of t d (%) Variation of SNM (%) Figure Variation of σ L (%) (c) Effects of variation of lateral straggle on the sensitivity of FinFET performance. Figure shows variation of (a) the effective channel length (L eff ) and the threshold voltage (V t ), (b) I OFF and I ON, (c) t d and SNM variations with lateral straggle (σ L ). The variation of R S/D is shown in the inset of (b). The reference σ L is 9.5nm. The L eff in (a), t d and SNM in (c) are from UFDG simulations, while rest of the parameters are from MEDICI simulations.

151 135 asymmetric variation of V t (and I OFF ) is mainly due to the nonlinear variation of L eff with σ L. The variation of UFDG-predicted L eff with σ L shows (Figure 5.7(a)) that the increase of σ L changes L eff more severely than the decrease of σ L does. The reason for such asymmetry can be explained by (3.23). The extent of L es (L ed )inthe source (drain) extension are defined by a certain carrier concentration, say n es (cm -3 ), which is high enough to give a smaller Debye length and usually lies in the vicinity of 5x10 18 cm -3. When σ L is large, i.e., N SD (y) is flatter, n es is defined by the N SD (y) and increase of σ L decreases L es (L ed ), and hence L eff decreases sharply with the increase of σ L. However, when σ L is decreasing, N SD (y) becomes more abrupt, and n es is defined by the spilled over electrons in the extension from the source/ drain, and becomes less dependent on the N SD (y). Hence, L eff becomes less sensitive of σ L, as the latter decreases after certain value. In Figure 5.7(b) the variation of I ON with σ L is shown. With 10% variation in σ L,I ON could vary as high as 18%. Such variation is due to the variation of both V t and R S/D (shown in the inset). The variation of extension resistance could be quite significant, as shown in the figure. For 10% variation of σ L, the maximum variation in R S/D is ~ 20%. However, if contact resistance is considered, percentage variation of total R S/D will be less, but with the variation of σ L, the modulation of sheet resistance and R es/d will remain significant. The UFDG-predicted variation of t d and SNM are shown in Figure 5.7(c). The variation of t d follows that of 1/I ON indicating no significant change of gate capacitance due to the variation of σ L. The variation of SNM follows that of 1/I OFF, as the leakier pull-down transistors reduce the stability of the SRAM cell. For a 10%

152 136 change in σ L a maximum of 7% variation in t d and 13% variation in SNM is obtained for our design. 5.6 Effects of Random Doping N SD (y) Randomness To study the effects of N SD (y) randomness, here we only vary the dopants within that part of the extension which contributes to the effective channel length, i.e., within L es /L ed. Two extreme cases of N SD (y) variations are considered; the first case (profile y_a in Figure 5.8) is when the number of dopants/slice within L es (L ed ) is constant and equal to the number at the beginning of the L eff, which is ~3 atoms/ slice (Figure 5.1) for a FinFET with h Si = 56nm. In the second case (profile y_b in Figure 5.8), we assume the number of dopants/slice is zero within L es /L ed. In both the cases, the number of atoms in the channel under the gate is assumed to be zero, as assuming the same for the reference case does not change the device characteristics noticeably. MEDICI-predicted performance parameters of the devices having N SD (y) as in Figure 5.8 are listed in Table 5.1. For the profile y_a, where the number of n- type dopants within L eff is higher than that of in the reference profile, V t decreases by 8%. To understand the variation of V t, we used UFDG to calibrate the device characteristics with different profiles and found that the L eff is different for all three cases. The L eff changes by 5% from the reference device for the two extreme cases and as no other parameters in the UFDG model card are changed, we conclude that the change in the L eff is solely responsible for the variation of the subthreshold

153 Reference Profile Profile y_a Profile y_b N SD (y) (cm -3 ) Source L g Drain Distance along y (nm) Figure 5.8 Various lateral doping profiles for studying the effects of source/drain doping variation in the extension. Table 5.1 shows the corresponding variations in the performance parameters.

154 138 Profile L eff (nm) R S/D (Ω- µm) S (mv/ decade) Table 5.1 MEDICI- and UFDG-predicted characteristics of FinFETs with N SD (y) shown in Figure 5.8 DIBL (mv/ V) V t (V) I OFF (na/ µm) I ON (ma/ µm) t d (ps) SNM (V) Ref y_a y_b

155 139 parameters in Table 5.1. When there are more dopants within L es/d (profile y_a), the donor dopant concentration there becomes quite high (~ 7x10 18 cm -3 for profile y_a), which translates into smaller Debye length (~ 1.5 nm in this case), and can effectively screen the gate induced electric field, and thus reduces the L eff. Similarly, absence of dopant atoms in the extension extends the gate-controlled region, and L eff increases for the second case. Note that, as the change in the donor concentration occurs outside the physical gate length, they do not effect the workfunction difference between the gate and the channel, and only varies the L eff slightly. In contrast, the variation of body doping in the bulk-si, where the gate-body work function difference, as well as the contribution of depletion charge changes with the variation of channel dopants, varies V t significantly. Thus, the control of V t by introducing underlap is much more viable than by controlling the dopants in the channel. (Not to mention, for the reference device, it is impossible to get a reasonable threshold voltage with polysilicon gate and highly doped body. One needs to use a combination of highly doped body, thin t Si, and some near mid-gap gate to get a threshold voltage ~0.2V). Also in Table 5.1, the MEDICI-predicted I ON is listed corresponding to different profiles in Figure 5.8. Maximum variation in I ON observed is ~20% from the reference device, and happens when there are no dopants within L es /L ed. The variation is due to the change in the threshold voltage and source/drain resistance. A maximum of 8% variation in t d and a 10% variation in SNM is predicted by UFDG for these extreme cases of randomness of the dopants within L es and L ed.

156 N SD (x) Randomness Like in the previous case, the doping in the extension can be distributed randomly in the x-direction also. Here as well we consider two possible extreme cases only, one of which is where all the atoms in each slice (Figure 5.9(a)) are placed near to one of the surfaces (henceforth referred as profile x_a) and the other is where all the atoms are in the middle of the channel (Figure 5.9(b), henceforth referred as profile x_b). In both the cases, the number of dopant atoms/slice is the same as for the reference cases, however the carrier concentration is changed to reflect the localization of the atoms in the specified part of the channel. We expect the placement of the donor dopants (for n-channel) to influence the threshold voltage depending on their position relative to the leakage path. In an undoped FinFET, the leakage path (i.e., where the carrier concentration is the largest) is at the center of the channel, so when the source/drain dopants gather around the middle of the fin (profile x_b), they increase the conduction (provide a punch-through path) and decrease threshold voltage. In Figure 10, MEDICI predicted I D -V G characteristics follow our expectation, and profile x_b does give the worst short channel effects. For the case of profile x_a, when all the donor dopants are placed near one of the surfaces, their effects come from the reduction of the donors from the middle of the channel, compared to that of the reference device, and V t increases slightly. As the donor doping level is negligible in the channel, in quantitative terms (inset of Figure 5.10) the change in I OFF and I ON, due to the different placement of the donor dopants, is not alarming. A maximum of 3.5% change in the I ON is predicted by MEDICI for

157 141 N SD (cm -3 ) N SD (cm -3 ) Distance along x (nm) Distance along y (nm) (a) Distance along x (nm) Distance along y (nm) (b) Figure 5.9 Localization of lateral dopants, N SD (y) at different x, all the dopants within L eff are assumed to be crammed near (a) the front surface (profile x_a), and (b) in the middle of the film (profile x_b).