UT Austin, ECE Department VLSI Design 4. CMOS Transistor Theory
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1 UT Autin, EE Department S Dein 4. MOS Tranitor Theory 4. MOS Tranitor Theory at moule: mplementin loic function with MOS tranitor Thi moule: Baic ehavior of MOS tranitor at the electrical level D. Z. Pan 4. MOS Tranitor Theory 1 Electrical Propertie Neceary to unertan the aic electrical propertie of the MOS tranitor (eometry => electrical), e.., elay/power Enure that the circuit are rout reate workin layout Preict elay an power conumption A technoloy avance an circuit imenion cale own, electrical effect ecome more important Seconary/nonieal effect D. Z. Pan 4. MOS Tranitor Theory The nmos Tranitor Moerately ope p type utrate (or well) in which two heavily ope n reion, the Source an Drain are iffue Gate i inulate from utrate y thin oxie Reitance of oxie i > 10 1 Ω, o current 0 Two type of nmos tranitor Enhancement: non conuctin when ate voltae = (ource voltae) (normally ue) Depletion: conuctin when = D. Z. Pan 4. MOS Tranitor Theory 3 Terminal oltae Moe of operation epen on,, = = = = Source an rain are ymmetric iffuion terminal By convention, ource i terminal at lower voltae Hence 0 nmos oy i roune; for imple ein, aume ource i 0 too Three reion of operation utoff inear Saturation D. Z. Pan 4. MOS Tranitor Theory 4 Moe in MOS Structure nmos utoff AUMUATON polyilicon ate ilicon ioxie inulator putrate << t DEPETON epletion reion = t No channel = 0 = 0 NERSON inverion reion (n type) epletion reion > t n n D. Z. Pan 4. MOS Tranitor Theory 5 D. Z. Pan 4. MOS Tranitor Theory 6 1
2 UT Autin, EE Department S Dein 4. MOS Tranitor Theory hannel form urrent flow from to e from to increae with Similar to linear reitor nmos inear Threhol oltae, t > t > t n n n n = = 0 > > t 0 < < t nmos Saturation hannel pinche off inepenent of e ay current aturate Similar to current ource > t n n < t > t D. Z. Pan 4. MOS Tranitor Theory 7 D. Z. Pan 4. MOS Tranitor Theory 8 The pmos Tranitor Moerately ope n type utrate (or well) in which two heavily ope p reion, the Source an Drain are iffue Application of a neative ate voltae (w.r.t. ource) raw hole into the reion elow the ate; channel chane from n to ptype (ourcerain conuction path) onuction ue to hole; neative weep hole from ource (throuh channel) to rain D. Z. Pan 4. MOS Tranitor Theory 9 haracteritic n inear reion, epen on How much chare i in the channel? How fat i the chare movin? D. Z. Pan 4. MOS Tranitor Theory 10 hannel hare MOS tructure look like parallel plate capacitor while operatin in inverion Gate oxie channel Q channel = = = ε ox /t ox = ox = c t = ( /) t t ox polyilicon ate n n SiO ate oxie (oo inulator, ε ox = 3.9) where ox = ε ox / t ox ate ource rain channel n n D. Z. Pan 4. MOS Tranitor Theory 11 arrier elocity hare i carrie y e arrier velocity v proportional to lateral E fiel etween ource an rain v = μe (μ calle moility) E = / Time for carrier to cro channel: t = / v D. Z. Pan 4. MOS Tranitor Theory 1
3 UT Autin, EE Department S Dein 4. MOS Tranitor Theory nmos inear Now we know How much chare Q channel i in the channel How much time t each carrier take to cro Qchannel = t = μ = β t ox t where β = μox nmos Saturation f < t, channel pinche off near rain hen > at = t Now rain voltae no loner increae current at = β t at β = ( ) t D. Z. Pan 4. MOS Tranitor Theory 13 D. Z. Pan 4. MOS Tranitor Theory 14 nmos Summary Shockley 1 t orer tranitor moel 0 < t = β < β ( ) > t at t at cutoff linear aturation Example Example: a 0.6 μm proce from AM emiconuctor.5 t ox = 100 Å μ = 350 cm /* 1.5 t = Plot v. 0.5 = 0, 1,, 3, 4, 5 = 0 = 1 Ue / = 4/ λ β = μox = ( 350) 10 μa/ = (ma) = 5 = 4 = 3 D. Z. Pan 4. MOS Tranitor Theory 15 D. Z. Pan 4. MOS Tranitor Theory 16 pmos All opin an voltae are inverte for pmos Moility μ p i etermine y hole Typically 3x lower than that of electron μ n Thu pmos mut e wier to provie the ame current Simple aumption, μ n / μ p = apacitance Any two conuctor eparate y an inulator have capacitance Gate to channel capacitor i very important reate channel chare neceary for operation Source an rain have capacitance to oy Acro revereiae ioe alle iffuion capacitance ecaue it i aociate with ource/rain iffuion D. Z. Pan 4. MOS Tranitor Theory 17 D. Z. Pan 4. MOS Tranitor Theory 18 3
4 UT Autin, EE Department S Dein 4. MOS Tranitor Theory Gate apacitance Approximate channel a connecte to ource = ε ox /t ox = ox = permicron permicron i typically aout ff/μm t ox polyilicon ate n n SiO ate oxie (oo inulator, ε ox = 3.9ε 0 ) D. Z. Pan 4. MOS Tranitor Theory 19 apacitance Etimation The ynamic repone (witchin pee) of a MOS circuit i very epenent on paraitic capacitance aociate with the SOURE circuit HANNE t ox DEPETON GATE PSUBSTRATE AYER DRAN Paraitic apacitance:, = atetochannel capacitance lumpe at ource an rain reion, = ource an rain iffuion capacitance to ulk (utrate) A routin capacitance to et total capacitance. D. Z. Pan 4. MOS Tranitor Theory 0 Gate apacitance of MOS Tranitor = 49. μ, = 0.75μ Diffuion apacitance, from Source/Drain Uneirale, calle paraitic capacitance apacitance epen on area an perimeter Ue mall iffuion noe omparale to for contacte iff ½ for uncontacte arie with proce D. Z. Pan 4. MOS Tranitor Theory 1 D. Z. Pan 4. MOS Tranitor Theory Area an Periphery apacitance Pa Tranitor DFFUSON X Periphery capacitance (pf/μ) e have aume ource i roune hat if ource > 0? e.. pa tranitor pain DFFUSON a ja GND OR Area capacitance (pf/μ ) D. Z. Pan 4. MOS Tranitor Theory 3 D. Z. Pan 4. MOS Tranitor Theory 4 4
5 UT Autin, EE Department S Dein 4. MOS Tranitor Theory Pa Tranitor Pa Tranitor ircuit e have aume ource i roune hat if ource > 0? e.. pa tranitor pain = f > t, < t Hence tranitor woul turn itelf off = tn DD tn DDtn tn nmos pa tranitor pull no hiher than tn alle a erae 1 Approach erae value lowly (low ) pmos pa tranitor pull no lower than tp SS = tp tn tn D. Z. Pan 4. MOS Tranitor Theory 5 D. Z. Pan 4. MOS Tranitor Theory 6 Effective Reitance Shockley moel have limite value Not accurate enouh for moern tranitor Too complicate for much han analyi Simplification: treat tranitor a reitor Replace (, ) with effective reitance R = /R R averae acro witchin of iital ate Too inaccurate to preict current at any iven time But oo enouh to preict R elay D. Z. Pan 4. MOS Tranitor Theory 7 O A The MOS Reitor Reitance of a ar of uniform material O B The channel reitance of a MOS tranitor in the linear reion D. Z. Pan 4. MOS Tranitor Theory 8 Reitor onnecte in Serie R1 R R1 R Reitor onnecte in Parallel R1 Sheet Reitance, R : Any material on the chip can e ivie into quare on a ie with (R Ω/ )R = R (/)Ω R = R 1 R = Typical heet reitance (Ω/ ) for 0.5μ TSM proce: 4.7 for N, 3.5 for P, 4. for Poly, 0.06 for Metal1, 0.08 for Metal Metal4, 0.03 for Metal5, an 1191 for the Nwell ncreae of aout 0.3%/ (metal, poly), 1%/ (iffuion) D. Z. Pan 4. MOS Tranitor Theory 9 For two quare in parallel, the equivalent reitance i ½ Exprein heet reitance in implifie the calculation ontact reitance ecome more important a procee cale own (new tren: reunant via) Aout 6 Ω for N, P, Poly, Metal 4 Ω for Metal 4 Ω for Metal3 8 Ω for Metal5 in 0.5μ TSM proce R Ue multiple contact for low reitance connection D. Z. Pan 4. MOS Tranitor Theory 30 5
6 UT Autin, EE Department S Dein 4. MOS Tranitor Theory Reitance of TurneOn Tranitor / ratio efine ize of N an P channel tranitor hannel reitance of turneon tranitor i: k i in the rane of ,000 Ω/ Reitance increae y aout 0.5%/ aove 5 R = (/) 1 R = 3 R = 1/3 D. Z. Pan 4. MOS Tranitor Theory 31 R Delay Moel Ue equivalent circuit for MOS tranitor eal witch capacitance an ON reitance Unit nmos ha reitance R, capacitance Unit pmos ha reitance R, capacitance apacitance proportional to with Reitance inverely proportional to with k R/k k D. Z. Pan 4. MOS Tranitor Theory 3 R/k nverter Delay Etimate Etimate the elay of a fanoutof1 inverter Y A 1 1 = 6R R Y R R D. Z. Pan 4. MOS Tranitor Theory 33 Example of SPE Deck *file aic3.p tet of 10 tae lumpe mo moel * comment.option cale=1e6 pot= nomo vin in 0 pl 0v 0n 5v 100p.param rpoly=40 wt=100 lt=1. m1 inle in 0 0 n w=wt l=lt xm1 lumpe in 0 0 lrtp xw=wt xl=lt vinle inle 0 5v vlumpe lumpe 0 5v.tran 5p 4n.raph tran moel=time1 inle=par('i(vinle) ) lumpe=par('i(vlumpe)').moel time1 plot xmin=0p xmax=800p * uckt an moel on next pae *.uckt lrtp rain ate ource ulk D. Z. Pan 4. MOS Tranitor Theory 34 Example of SPE Deck, ont.uckt lrtp rain ate ource ulk m1 rain ate ource ulk n w='xw/18' l=xl m rain 1 ource ulk n w='xw/9' l=xl m3 rain ource ulk n w='xw/9' l=xl m4 rain 3 ource ulk n w='xw/9' l=xl m5 rain 4 ource ulk n w='xw/9' l=xl m6 rain 5 ource ulk n w='xw/9' l=xl m7 rain 6 ource ulk n w='xw/9' l=xl m8 rain 7 ource ulk n w='xw/9' l=xl m9 rain 8 ource ulk n w='xw/9' l=xl m10 rain 9 ource ulk n w='xw/18' l=xl D. Z. Pan 4. MOS Tranitor Theory 35 Example of SPE Deck, ont r1 ate 1 'xw/xl*rpoly/9' r 1 'xw/xl*rpoly/9' r3 3 'xw/xl*rpoly/9' r4 3 4 'xw/xl*rpoly/9' r5 4 5 'xw/xl*rpoly/9' r6 5 6 'xw/xl*rpoly/9' r7 6 7 'xw/xl*rpoly/9' r8 7 8 'xw/xl*rpoly/9' r9 8 9 'xw/xl*rpoly/9'.en lrtp * * moel ection *.moel n nmo level=3 vto=0.7 uo=500 kappa=.5 kp=30u eta=.03 theta=.04 vmax=e5 nu=9e16 tox=50e10 amma=1.5 p=0.6 j=.1m xj=0.5u l=0.0 nf=1e11 n=e10 co=00p co=00p co=300p.en D. Z. Pan 4. MOS Tranitor Theory 36 6
7 UT Autin, EE Department S Dein 4. MOS Tranitor Theory Spice Simulation: NAND Gate SPE "eck" ha "meaure", print tatement; parameter, netlit Moel: 0.18 micron D. Z. Pan 4. MOS Tranitor Theory 37 7
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