VLSI Design I; A. Milenkovic 1

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1 Review Voltage wing of PT Driving an Inverter PE/EE 47, PE 57 VLI Design I L9: MO & Wire apacitances Department of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www. ece.uah.edu/~milenka ) www. ece.uah.edu/~milenka/cpe57-3f [dapted from Rabaey s Digital Integrated ircuits,, J. Rabaey et al. and Mary Jane Irwin ( www. cse. psu.edu/~mji ) ] In = V DD.5/.5 D x.5/.5.5/.5 V DD ody effect large V at x - when pulling high ( is tied to GND and charged up close to V DD ) o the voltage drop is even worse V x = V DD - (V Tn + γ( ( φ f + V x ) - φ f )) Voltage, V 3 In x =.8V.5.5 Time, ns 9/4/3 VLI Design I;. Milenkovic 4 ourse dministration ascaded NMO Only PTs Review Instructor: leksandar Milenkovic milenka@ece.uah.edu Office Hrs: MW 7:3-8:3, E7-L T: Fathima Tareen Office Hrs: Friday : : M, E46 URL: Text: Digital Integrated ircuits, nd Edition Rabaey et. al., (October) Lab: eptember 5 (posted), Due: October Hw: eptember 5 (posted), Due eptember 9 Project: Default project # posted! 9/4/3 VLI Design I;. Milenkovic = V DD = V DD G = V DD x = V DD - V Tn G y M wing on y = V DD - V Tn - V Tn = V DD = V DD = V DD 9/4/3 VLI Design I;. Milenkovic 5 x M y wing on y = V DD - V Tn Pass transistor gates should never be cascaded as on the left Logic on the right suffers from static power dissipation and reduced noise margins NMO Only PT Driving an Inverter Review olution : Level Restorer Review In = V DD V V x = G = V DD V DD -V Tn D M Level Restorer on M r off = M x = = = M n = V x does not pull up to V DD, but V DD V Tn Threshold voltage drop causes static power consumption (M may be weakly conducting forming a path from V DD to GND) Notice V Tn increases of pass transistor due to body effect (V ) 9/4/3 VLI Design I;. Milenkovic 3 Full swing on x (due to Level Restorer) so no static power consumption by inverter No static backward current path through Level Restorer and PT since Restorer is only active when is high For correct operation M r must be sized correctly (ratioed) 9/4/3 VLI Design I;. Milenkovic 6 VLI Design I;. Milenkovic

2 Voltage, V Transient Level Restorer ircuit Response 3 W/L =.5/.5 W/L n =.5/.5 W/L =.5/.5 W/L r =.75/.5 W/L r =.5/.5 W/L r =.5/.5 W/L r =./ Time, ps node x never goes below V M of inverter so output never switches Restorer has speed and power impacts: increases the capacitance at x, slowing down the gate; increases t r (but decreases t f ) 9/4/3 VLI Design I;. Milenkovic 7 olution 3: Transmission Gates (TGs ) Most widely used solution = V DD = GND = V DD Full swing bidirectional switch controlled by the gate signal, = if = 9/4/3 VLI Design I;. Milenkovic = GND = GND = V DD olution : Multiple V T Transistors Technology solution: Use (near) zero V T devices for the NMO PTs to eliminate most of the threshold drop (body effect still in force preventing full swing to V DD ) In = V In =.5V =.5V on sneak path off but leaking = V low V T transistors Impacts static power consumption due to subthreshold currents flowing through the PTs (even if V G is below V T ) 9/4/3 VLI Design I;. Milenkovic 8 Resistance, kω Resistance of TG W/L p =.5/.5 3 V 5 R n R p.5v Rp 5 R n.5v R eq 5 W/L n =.5/.5, V 9/4/3 VLI Design I;. Milenkovic olution 3: Transmission Gates (TGs ) TG Multiplexer Most widely used solution In F V DD F = GND = GND In = V DD = GND = V DD = V DD Full swing bidirectional switch controlled by the gate signal, = if = F =!(In + In ) GND In In 9/4/3 VLI Design I;. Milenkovic 9 9/4/3 VLI Design I;. Milenkovic VLI Design I;. Milenkovic

3 Transmission Gate XOR MO & Wire apacitances 9/4/3 VLI Design I;. Milenkovic 3 Transmission Gate XOR MO Inverter: Dynamic Transient, or dynamic, response determines the maximum speed at which a device can be operated. off on off on weak if!!! V DD = Today s focus weak if an inverter R n L t phl = f(r n, L ) = V DD Next lecture s focus 9/4/3 VLI Design I;. Milenkovic 4 9/4/3 VLI Design I;. Milenkovic 7 Review: Delay Definitions ources of apacitance L input waveform output waveform 5% t phl t f 5% % Propagation delay t p = (t phl + t plh )/ 9/4/3 VLI Design I;. Milenkovic 5 t plh t r 9% t t signal slopes G4 M D M 4 Vin GD w D G3 M 3 intrinsic MO transistor capacitances extrinsic MO transistor (fanout) capacitances wiring (interconnect) capacitance 9/4/3 VLI Design I;. Milenkovic 8 VLI Design I;. Milenkovic 3

4 MO Intrinsic apacitances tructure capacitances hannel capacitances Depletion regions of the reversebiased pn-junctions of the drain and source Review: ummary of MO Operating Regions utoff (really subthreshold) V G V T Exponential in V G with linear V D dependence I D = I e (qv G /nkt) ( - e - (qv D /kt) ) ( - λ V D ) where n trong Inversion V G > V T Linear (Resistive) V D <V DT = V G - V T I D = k W/L [(V G V T )V D V D /] (+λv D ) κ(v D ) aturated (onstant urrent) V D V DT = V G - V T I Dat = k W/L [(V G V T )V DT V DT /] (+λv D ) κ(v DT ) NMO V T (V).43 γ(v.5 ).4 V DT (V).63 k (/V ) 5 x -6 λ(v - ).6 PMO x /4/3 VLI Design I;. Milenkovic 9 9/4/3 VLI Design I;. Milenkovic Top view MO tructure apacitances lateral diffusion ource x d Poly Gate L drawn L eff Overlap capacitance (linear) x d W t ox Drain GO = GDO = ox x d W = o W verage Distribution of hannel apacitance Operation Region utoff Resistive aturation G ox WL G ox WL/ (/3) ox WL GD ox WL/ G ox WL ox WL (/3) ox WL ox WL + o W ox WL + o W (/3) ox WL + o W hannel capacitance components are nonlinear and vary with operating voltage Most important regions are cutoff and saturation since that is where the device spends most of its time G 9/4/3 VLI Design I;. Milenkovic 9/4/3 VLI Design I;. Milenkovic 3 MO hannel apacitances The gate-to-channel capacitance depends upon the operating region and the terminal voltages G = G + GO G V G + - GD = GD + GDO D MO Diffusion apacitances The junction (or diffusion) capacitance is from the reverse-biased source-body and drain-body pnjunctions. V G + - G D n channel G = G p substrate depletion region = diff n channel p substrate depletion region D = Ddiff 9/4/3 VLI Design I;. Milenkovic 9/4/3 VLI Design I;. Milenkovic 4 VLI Design I;. Milenkovic 4

5 ource Junction View channel-stop implant (N +) Reverse-ias Diode Junction apacitance junction depth x j W source bottom plate (N D ) L side walls substrate (N ) channel j (ff).5.5 linear (m=/3) abrupt (m=/) j diff = bp + sw = j RE + jsw PERIMETER = j L W + jsw (L + W) 9/4/3 VLI Design I;. Milenkovic V D (V) 9/4/3 VLI Design I;. Milenkovic 8 Review: Reverse ias Diode ll diodes in MO digital circuits are reverse biased; the dynamic response of the diode is determined by depletion-region charge or junction capacitance j = j /(( V D )/φ ) m where j is the capacitance under zero-bias conditions (a function of physical parameters), φ is the built-in potential (a function of physical parameters and temperature) and m is the grading coefficient m = ½ for an abrupt junction (transition from n to p-material is instantaneous) m = /3 for a linear (or graded) junction (transition is gradual) Nonlinear dependence (that decreases with increasing reverse bias) 9/4/3 VLI Design I;. Milenkovic 6 + V D - MO apacitance Model G = G + GO G GD = GD + GDO G G GD D = diff D = Ddiff G = G 9/4/3 VLI Design I;. Milenkovic 9 D Junction apacitance Transistor apacitance Values for.5m Example: For an NMO with L =.4 µm, W =.36 µm, L D = L =.65 µm GO = GDO = ox x d W = o W = G = ox WL = so gate_cap = ox WL + o W = bp = j L W = sw = jsw (L + W) = so diffusion _cap = ox o j m j φ b jsw m jsw φ bsw (ff/µ m ) (ff/µ m) (ff/µ m ) (V) (ff/µ m) (V) NMO PMO /4/3 VLI Design I;. Milenkovic 7 9/4/3 VLI Design I;. Milenkovic 3 VLI Design I;. Milenkovic 5

6 Transistor apacitance Values for.5m Example: For an NMO with L =.4 µm, W =.36 µm, L D = L =.65 µm GO = GDO = ox x d W = o W =. ff G = ox WL =.5 ff so gate_cap = ox WL + o W =.74 ff bp = j L W =.45 ff sw = jsw (L + W) =.45 ff so diffusion _cap =.9 ff ox o j m j φ b jsw m jsw φ bsw (ff/µ m ) (ff/µ m) (ff/µ m ) (V) (ff/µ m) (V) NMO PMO /4/3 VLI Design I;. Milenkovic 3 Drain-ulk apacitance: K eq s (for.5 mm) We can simplify the diffusion capacitance calculations even further by using a K eq to relate the linearized capacitor to the value of the junction capacitance under zero-bias eq = K eq j NMO PMO high-to-low K eqbp K eqsw.6.86 low-to-high K eqbp K eqsw.8.7 9/4/3 VLI Design I;. Milenkovic 34 Vin Review: ources of apacitance L G4 M D M 4 GD w D G3 M 3 Extrinsic (Fan-) apacitance The extrinsic, or fan-out, capacitance is the total gate capacitance of the loading gates M3 and M4. fan-out = gate (NMO) + gate (PMO) = ( GOn + GDOn + W n L n ox ) + ( GOp + GDOp + W p L p ox ) implification of the actual situation ssumes all the components of gate are between and GND (or V DD ) ssumes the channel capacitances of the loading gates are constant intrinsic MO transistor capacitances extrinsic MO transistor (fanout) capacitances wiring (interconnect) capacitance 9/4/3 VLI Design I;. Milenkovic 3 9/4/3 VLI Design I;. Milenkovic 35 V Gate-Drain apacitance: The Miller Effect M and M are either in cut-off or in saturation. The floating gate-drain capacitor is replaced by a capacitance-to-ground (gate-bulk capacitor). GD V capacitor experiencing identical but opposite voltage swings at both its terminals can be replaced by a capacitor to ground whose value is two times the original value 9/4/3 VLI Design I;. Milenkovic 33 V V G PMO.5/.5 Layout of Two hained Inverters Polysilicon NMO.375/.5 In 9/4/3 VLI Design I;. Milenkovic 36 V DD GND. µm =l Metal.5.5 NMO PMO W/L.375/.5.5/.5 D (mm ).3.7 PD (mm) (mm ).3.7 P (mm) VLI Design I;. Milenkovic 6

7 omponents of L (.5 mm) Permittivity Values of ome Dielectrics Expression Value (ff) Value (ff) Term HfiL LfiH GD on W n.3.3 GD op W p.6.6 D K eqbpn D n j + K eqswn PD n jsw.66.9 D K eqbpp D p j + K eqswp PD p jsw.5.5 G3 ( on )W n + ox W n L n G4 ( op )W p + ox W p L p.8.8 w from extraction.. L Material Free space Teflon F romatic thermosets (ilk) Polyimides (organic) Fluorosilicate glass (FG) ilicon dioxide Glass epoxy (Ps) ilicon nitride lumina (package) ilicon ε di /4/3 VLI Design I;. Milenkovic 37 9/4/3 VLI Design I;. Milenkovic 4 Wiring apacitance ources of Interwire apacitance The wiring capacitance depends upon the length and width of the connecting wires and is a function of the fan-out from the driving gate and the number of fan-out gates. Wiring capacitance is growing in importance with the scaling of technology. fringe wire = pp + fringe + interwire = (ε di /t di )WL + (πε di )/log(t di /H) + (ε di /t di )HL interwire pp 9/4/3 VLI Design I;. Milenkovic 38 9/4/3 VLI Design I;. Milenkovic 4 Parallel Plate Wiring apacitance Impact of Fringe apacitance current flow L electrical field lines W H t di dielectric (io ) H/t di = H/t di =.5 pp substrate permittivity constant (io = 3.9) pp = (ε di /t di ) WL W/t di (from [akoglu89]) 9/4/3 VLI Design I;. Milenkovic 39 9/4/3 VLI Design I;. Milenkovic 4 VLI Design I;. Milenkovic 7

8 Impact of Interwire apacitance Dealing with apacitance Low capacitance (low-k) dielectrics (insulators) such as polymide or even air instead of io family of materials that are low-k dielectrics must also be suitable thermally and mechanically and compatible with (copper) interconnect opper interconnect allows wires to be thinner without increasing their resistance, thereby decreasing interwire capacitance OI (silicon on insulator) to reduce junction capacitance (from [akoglu89]) 9/4/3 VLI Design I;. Milenkovic 43 9/4/3 VLI Design I;. Milenkovic 46 Insights For W/H <.5, the fringe component dominates the parallel-plate component. Fringing capacitance can increase the overall capacitance by a factor of or more. When W <.75H interwire capacitance starts to dominate Interwire capacitance is more pronounced for wires in the higher interconnect layers (further from the substrate) Rules of thumb Never run wires in diffusion Use poly only for short runs horter wires lower R and Thinner wires lower but higher R Wire delay nearly proportional to L 9/4/3 VLI Design I;. Milenkovic 44 Wiring apacitances Field ctive Poly l l l3 l4 Poly l pp in af/µm fringe in af/µm l l3 l l Poly l l l3 l4 l5 Interwire ap per unit wire length in af/µm for minimally-spaced wires 9/4/3 VLI Design I;. Milenkovic 45 VLI Design I;. Milenkovic 8

CPE/EE 427, CPE 527 VLSI Design I Pass Transistor Logic. Review: CMOS Circuit Styles

CPE/EE 427, CPE 527 VLSI Design I Pass Transistor Logic. Review: CMOS Circuit Styles PE/EE 427, PE 527 VLI Design I Pass Transistor Logic Department of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) Review: MO ircuit