CMOS Digital Integrated Circuits Analysis and Design

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1 MOS igital ntegrated ircuits Analysis and esign hapter 4 Modeling of MOS ransistors Using SPE 1

2 ntroduction he SPE software that was distributed by U Berkeley beginning in the late 1970s had three built-in MOSE models LEVEL1(MOS1 is a described y a square-law current-voltage characteristics LEVEL (MOS is a detailed analytical MOSE model LEVEL 3 (MOS3 is a semi-empirical model Both MOS and MOS3 include second-order ects he short channel threshold voltage, subthreshold conduction, scattering-limited velocity saturation, and charge-controlled capacitances he BSM3 version More accurate characterization sub-micron MOSE characteristics

3 Basic concept he equivalent circuit structure of the NMOS LEVEL 1 model 3

4 he LEVEL 1 model equation Linear region V L k γ V L L μ ' k ' k 0 ε W L + γ Si k q Saturation region W L [ ( V V V V ] ( 1+ λv ( V V ( 1+ λ V ( φ + VSB φ q N A n ln N i A he threshold voltage ' φ where ε t for V and V V V for V and V -V V < V -V K 7.6μA/V KP7.6U V 0 1.0V VO1 γ0.53v 1/ GAMMA0.53 φ-0.58 PH0.58 λ0 LAMBA0 μ n 800cm /Vs UO800 t 100nm OX100E-9 N A cm -3 NSUB1E15 L 0.8μm L0.8E-6 4

5 Variation of the drain current with model parameter 5

6 he LEVEL model equation V 0 n the current equation above, the surface carrier mobility has been assumed constant, and its variation with applied terminal voltages has been neglected n reality, the surface mobility decreases with the increasing gate voltage ue to the scattering of carriers in the channel ( 1 λ V sat G k ' ( 1-λ V q N W L ss he saturation voltage V V VA V VB φ + γ 1 he saturation mode current 1 he zero bias threshold voltage Φ k U U U ' ( new c t e B + φ + γ φ V φ 1+ γ ( V V V ' ε Si toc U c k ( V V Ut V ε is the gate - to - channel critical field is the exponential fitting parameter B 3 γ [( V VBS + φ ( VBS φ ] 3/ + 3/ is the contribution of the drain voltage to the gate - to - channel field Ue 6

7 variation of channel length in saturation mode L ' ε Si V VA V V A L Δ + 1+ q N A 4 4 he empirical channel length shortening coicient λ L he slope of the fitted to experimental data by changing the substrate doping parameter n this case, however, other as φ L ΔL V ΔL -V vurve is saturation can be adjusted and N A - dependent electrical parameters such and γ must be specified separately in the.moel statement N A 7

8 Saturation of carrier velocity he calculation of the saturation voltage V A is based on the assumption he channel charge near the drain becomes equal to zero when the device enters saturation his hypothesis is actually incorrect Since a minimum charge concentration greater than zero must exist in the channel, due to the carriers that sustain the saturation current he minimum concentration depends on the speed of the carriers he inversion layer charge at the channel-end is found as Q inv W v sat max ΔL X X v μ max + V V A X v μ max X ε Si q N N A he parameter N is used as a fitting parameter 8

9 Subthreshold conduction or V <V, there is a channel current even when the surface is not in strong inversion his subthreshold current ue mainly to diffusion between and the channel Becoming an increasing concern for deepsub-micron designs he model implemented in SPE introduces an exponential, semi-empirical dependence of the drain current on V in the weak inversion region the voltagev V on on he parameter N and is used as a fitting parameter that determines the slope of current - voltage characteristics d his (weak inversion is the current in strong inversion for V V on nk + q is found as : is the depletion capacitance model introduces a ( V q N where n 1+ S on e V on S q nk + is defined as the number of fast superficial states discontinuity for V the subthreshold, therefore, the simulation of the transition region between weak and strong inversion is not very precise d V on V on 9

10 he LEVEL 3 model equations he LEVEL 3 model has been developed for simulation of short channel MOS transistor Quite precisely for channel lengths down to μm he current-voltage equation in the linear region has been simplified with a aylor series expansion he majority of the LEVEL 3 model equations are empirical o improve the accuracy of the model o limit the complexity of the calculation W 1+ B μs V V V V L where μ μ s he n B s μ 1+ θ 1+ μ 4 ( V -V s μ v s γ s V L max φ s + V he empirical parameter SB B + hev., and μ are influenced by the short is influenced by the narrow - channel ects n he decrease in the ective mobility with the average lateral electrical field express the dependence of - channel ects the bulk depletion charge 10

11 State-of-art MOSE models BSM-Berkeley short-channel GE model he model is analytically simple and is based on a small number of parameters, which are normally extracted from experimental data Accuracy and d\iciency Widely used by many companies and silicon foundries EKV (Enz-Krummenacher-Vittoz transistor model Previous models considering he strong-inversion region of operation separately from the weakinversion region ausing serous problems in the modeling of transistors at very low voltages as in many cases involving deep sub-micron MOS technology Attempting to solve this problem by Using a unified view of the transistor operating regions Avoiding the use of disjoint equations in strong and weak inversion 11

12 Gate ide capacitance SPE uses a simple gate ide capacitance model that represents the charge storage ect by three nonlinear two-terminal capacitor: GB, and G he geometry information required for the calculation of gate ide capacitance are: Gate ide thickness OX hannel width W hannel length L Lateral diffusion L he capacitances GBO, O, and GO, which are specified in the.moel statement, are the overlap capacitances between the gate and the other terminals outside the channel region f the parameter XQ is specified in the.moel statement SPE uses a simplified version of the charge-controlled capacitance model proposed by Ward 1

13 Junction capacitance j AS and A are the source and the drain areas PS and P are the source and the drain perimeters M SB j AS jsw PS + M j M jsw V 1 BS V 1 BS φ0 φ0 j A jsw P + M j M jsw V 1 B V 1 B φ0 φ0 : the zero - bias depletion capacitance per unit area at the bottom of B jsw jsw j : the zero - bias depletion capzcitance per unit length at the sidewall and M 10 jsw x denote the efault values are M j j j junction grading coicients for the bottom and the sidewalls 0.5 and M jsw 0.33 the junction junctions junctions 13

14 omparison of the SPE MOSE models he LEVEL 1 model Not very precise Quick and rough estimate of the circuit performance without much accuracy HE LEVEL model Require a larger time May occasionally cause convergence problems in the Newton-Raphson algorithm used in SPE HE LEVEL 3 model he PU time needed for model evaluation is less and the number of iterations are significantly fewer for the LEVEL three model isadvantage he complexity of calculating some of its parameters 14

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