Thermionic Emission Theory

Transcription

1 hapter 4. PN and Metal-Semiconductor Junction Thermionic Emiion Theory Energy band diagram of a Schottky contact with a forward bia V applied between the metal and the emiconductor. Electron concentration at the interface i (auming E Fn i flat all the way to the peak of the barrier) 3/ m kt n Ne e h q( BV )/ kt n q( BV )/ kt It can be hown that the average velocity of the left traveling electron i v kt / m 1 4 J SM qnvthx T e e KT e e J e h Only half of the electron travel toward the left. 4 qmnk K 3 h thx mk n q B/ kt qv / kt q B/ kt qv / kt qv / kt 3 1 A/( cm / K ) called Richardon contant J J n e SM q / kt B e q( V )/ kt Determine how many electron poe ufficient energy to urpa the peak of the energy barrier and enter the metal. B

2 Schottky Diode hapter 4. PN and Metal-Semiconductor Junction At zero bia (V = ), the net current i zero. I I () I () I SM M S I () SM I MS () I where I AJ AKT e Adiode area q B / kt, At forward bia, I ( V ) I () I M S M S B becaue the barrier height remain unchanged at the value at equilibrium. B ISM( V ) AkT e e I e q / kt qv / kt qv / kt becaue the barrier height i now maller by qv. I( V ) I ( V ) I ( V ) I e I I ( e 1) SM M S qv / kt qv / kt

3 Application of Schottky Diode I I e ( qv / kt 1) hapter 4. PN and Metal-Semiconductor Junction Schottky Diode: Majority carrier only: high peed/frequency (negligible minority carrier injection ) Larger I maller forward bia low power conumption Schematic IV characteritic of PN and Schottky diode having the ame area. Schottky diode i preferred in low voltage and high current rectifier application. Power conumption = ~ 15 W ( 5 A.3 V) ~ 4 W ( 5 A.8 V), if PN junction rectifier i ued. Block diagram of a witching power upply for electronic equipment uch a P. lamp diode

4 Ohmic ontact hapter 4. PN and Metal-Semiconductor Junction Ideal ohmic contact: The voltage acro an ideal ohmic contact i zero. The Fermi level cannot deviate from it equilibrium poition and therefore n p at ideal ohmic contact. Or, equivalently, urface recombination velocity become infinity, S. Semiconductor device are connected to each other in an integrated circuit through metal. The emiconductor to metal contact hould have ufficiently low reitance. For good ohmic contact, the emiconductor mut be very heavily doped to have only few nm-thin depletion layer. Tunneling Tunneling probability, 8 m P exp T ( V ) H E h V E H T W dep / Bn

5 V E H, Bn T W dep / qn 8 m Bn 8 m P exp T ( V ) exp H E Bn h qnd h 4 H Bn / Nd e where, H ( mn) / q h Bn d hapter 4. PN and Metal-Semiconductor Junction At V =, 1 J J SM J M S qndvthxp If a mall voltage i applied acro the contact, the barrier for i reduced from Bn to ( V ) J JS M 1 qn v e S M d thx H ( V )/ N Bn d Bn The IV characteritic of a.3 µm (diameter) TiSi contact on N + -Si and P + -Si. (From [11] IEEE.) At mall V, the net current denity i, dj SM 1 J V V V qvthxh Nd e dv Specific contact reitance [Ω cm ], (The reitance of a 1 cm contact) R H Bn d V e e J qv H N thx / N d H Bn / N d H Bn / N d Theoretical pecific contact reitance. (After [1].)

6 hapter 5. MOS apacitor hapter 5 MOS apacitor OBJETIVES 1. Undertand the modern MOS tructure.. Undertand the concept of urface depletion, threhold, and inverion. 3. Undertand the MOS capacitor -V 4. Build the foundation for undertanding the MOSFET.

7 MOS (metal-ide-emiconductor) apacitor hapter 5. MOS apacitor Al (before 197), Heavily doped polycrytalline ilicon (after 197) Variou metal (after 8) Thickne: a thin a ~ 1.5 nm Silicon diide (almot perfect inulator) Advanced dielectric (after 8) The MOS capacitor The MOS capacitor: the implet of MOS device and the tructural heart of all MOS device including MOSFET. An MOS tranitor i an MOS capacitor with PN junction at two end.

8 Flat-Band ondition and Flat-Band Voltage hapter 5. MOS apacitor For V g = E Flat-Band ondition (for V g = V fb ) E q g gate Band i not flat. Applying a negative voltage equal to flatband voltage (V fb ) to the gate. Flat-Band Voltage V fb g Flat-band E E In SiO, the exact poition of E F ha no ignificance. n N exp[( E E ) / kt 1 cm F 6 3,auming E F i around in the middle of the SiO band gap. E : vacuum level : work function of gate material [ V ] g : work function of emiconductor[ V ] : electron affinnity of ilicon[ ev ] Si SiO : electron affinnity of ide[ ev ]

9 Surface Accumulation hapter 5. MOS apacitor For V g < V fb : urface potential[ V ] q : band bending[ ev ] qv V : ide voltage negative, if E bend upward. poitive, if E bend downward. hole accumulation (p > p = N a ) V E E V V g Fm F fb At flat-band, V V, V g fb Potential reference ( x) E E Accumulation layer p N e N p, q / kt a a i Qacc f 1 mv [ / cm ]

10 hapter 5. MOS apacitor In the cae of urface accumulation, V V V g fb Uing Gau Law at the urface, D ( x) D 1 D3 D4 i mall in a firt-order model. ide urface Q acc D D AD A D A D AD AD where A A, 1 ide ide ide D AD1 () x D1 E E E ( x) E Q A acc Qacc Qacc E V E T (deep into emiconductor) where F cm, [ / ] T emiconductor x In general, V Q ub All the charge that may be preent in the ubtrate, including Q acc. Q ( V V ) acc g fb The MOS capacitor in accumulation behave like a capacitor but with a hift in V by V fb.

11 Surface Depletion hapter 5. MOS apacitor For V g > V fb ( x) V Q ub qn W dep a dep a Q qn The MOS capacitor i biaed into urface depletion. (a) Type of charge preent; (b) energy band diagram. E E qn W a dep W dep qn a Depletion layer charge N a qnawdep qnaw q dep / kt Vg Vfb V V fb a a p N e N p

12 hapter 5. MOS apacitor Threhold ondition and Threhold Voltage For more poitive (V g = V t > V fb ) Fermi potential energy q ( E E ) B i F bulk Threhold condition t B ( E E ) ( E E ) ( E E ) ( E E ) F urface F V bulk i F bulk F i urface ( x) E x E x de ( x) ( x) dx n N a Qub Qdep Qinv Qdep V( x) E ( x) dv ( x) E ( x) dx Surface electron n Depletion layer charge N a E () E ()

13 hapter 5. MOS apacitor Fermi potential energy q ( E E ) B i F bulk N kt ln n i a n N exp[ ( E E ) / kt ] i i p N exp[ ( E E ) / kt ] V F V n N N exp[ E / kt ] i V g Theoretical threhold voltage v. body doping concentration. At threhold, kt Na t B ln q n i Threhold Voltage, V t (V g at the threhold condition) V V V V t g fb a dep a dep V V B qn W qn W Vfb t fb B qn a B For P-Type Body For N-Type Body V V t fb t qn d t kt t B, B ln q N n d i

14 Strong Inverion beyond Threhold hapter 5. MOS apacitor For V g > V t WithV g > V t, doe not increae much further beyond B ince even mall increae in would induce a much larger urface electron denity and therefore a larger V that would oak up the V g. Surface potential i eentially pinned at B B. An MOS capacitor i biaed into inverion. ( x) E E n q exp( ) kt Inverion layer charge denity Inverion layer (thickne: ~5 nm) Depletion layer charge N a Q [ / ] inv cm a Q Q Q ub dep inv n N Surface become N-type.

15 hapter 5. MOS apacitor If, B W dep W d max Q Vg V fb V Vfb B B qn Qdep Q qna inv B Q Vfb B Vfb B V t Q inv ub Q ( V V ) a inv g t There are few electron in the P-type body, and it can take minute for thermal generation to generate the neceary electron to form the inverion layer. How to olve thi problem? inv V Q ub Q Q Q ub dep inv The MOS capacitor in trong inverion behave like a capacitor except for a voltage offet of V t. (a) The urface inverion behavior i bet tudied with a PN junction butting the MOS capacitor to upply the inverion charge. (b) The inverion layer may be thought of a a thin N-type layer.

16 Review: Baic MOS apacitor Theory hapter 5. MOS apacitor Surface potential aturate at ϕ B in inverion when V g i larger than V t and aturate at Vf b in accumulation. Depletion-region width in the body of an MOS capacitor.

17 hapter 5. MOS apacitor omponent of charge (/cm ) in the MOS capacitor ubtrate: (a) depletion-layer charge; (b) inverion-layer charge; and (c) accumulationlayer charge. The total ubtrate charge, Q ub (/cm ), i the um of Q acc, Q dep, and Q inv.

18 hapter 5. MOS apacitor Q ub V. Surface Potential Qub ( / cm ) B B ( V )