Adder Circuits Ivor Page 1

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1 Adder Circuit Adder Circuit Ivor Page 4. The Ripple Carr Adder The ripple carr adder i probabl the implet parallel binar adder. It i made up of k full-adder tage, where each full-adder can be convenientl made from two half-adder and an OR gate. The truth table of the half-adder i a follow: Input Output i i c i+ z i Figure how the blockdiagram of the adder. i i i- i- HA HA c i+ c c i c c i- HA HA c c z i z i- Figure : Ripple Carr Adder Each half-adder can be contructed from four 2-input nand gate. Univerit of Tea at Dalla

2 Adder Circuit 2 i c i Figure 2: Half-Adder in Nand Gate Figure 2 how the logic diagram. The complement of the carr ignal i produced, which i eactl what i needed if the inter-tage OR gate i replaced b a nand gate: c. c 2 = c + c 2. Figure 3 i from the tet and how one of man poible CMOS implementation of a half-adder. The dela from,, or,to comprie 2-inverter dela plu the dela due to pa-tranitor in the multipleer Figure 3: Half-Adder in Nand Gate Figure 4 i from Wete & Ehraghian 2. It how one of man poible CMOS implementation of a full-adder. Thi circuit i generall referred to a 28T ince it ha 28 tranitor, including two for each inverter. The dela through thi circuit from, to come from the two erie tranitor pull-up and pull-down in the firt tage and an inverter dela. For 2 Principle of CMOS VLSI Deign, Wete & Ehraghian, Addion Wele

3 Adder Circuit 3 the um output, there are two cacaded tage, each with 2 erie tranitor pull-up and pull-down, followed b an inverter. um Figure 4: CMOS Full-Adder Figure 5 how one poible laout uing imple tranitor equencing. It doe not include the two inverter. In thi laout, darkblue i ued for metal- line and light blue for metal- 2. P-Diffuion i ellow and N-diffuion i green. Polilicon line are pink. Each time a pol line croe P-Diff, a PMOS tranitor i formed, and each time it croe N-Diff, an NMOS tranitor i formed. It i common to modif the 28T circuit to implif the laout. To do o, diconnect the ource of the top tranitor from V in the output chain for um and connect it intead to the drain of the top three parallel tranitor in the penultimate tage. Make a correponding change at the bottom end of the final chain. Thi change enable a more compact laout which ha horter connection.

4 Adder Circuit 4 V Vdd um Figure 5: CMOS Laout of Full-Adder Figure 6 how the circuit of the adder arranged according to the laout of Figure 5. A an eercie, make the circuit change dicued above and devie a new laout. You hould be able to reduce the length of the metal- trackfor the um ignal. um Figure 6: CMOS Scematic of Laout of Full-Adder

5 Adder Circuit 5 Wang and Jiang 3 introduced new laout for the CMOS full-adder. The objective of optimizing the laout i to reduce capacitance throughout the circuit, epeciall at internal ignal point. In HSPICE imulation, their laout had 6% maller dela time and % lower power conumption than thoe of Wete. Wang and Jiang alo eperimented with 4 new circuit for the full-adder, compriing mainl pa-tranitor. Some of their circuit had onl - tranitor and were hown to have 9% maller dela time and % lower power conumption than previou T circuit. Figure 7 how one of their circuit. Note that buffer gate would be needed between uch tage ince there are two pa tranitor in erie in between the and ignal in each tage. V DD V DD MID um MID Figure 7: Jiang & Wang Full Adder Circuit 3 Yingtao Jiang, Ph.D Diertation, Department of Electrical Engineering, UT Dalla 2

6 Adder Circuit Dela Through Ripple Carr Adder The dela through a k tage ripple-carr adder, from input, to output c k, uing nand-baed circuit i (2k +)D, whered i the normalized gate dela. We conider the average dela ince the probabilit of the wort cae i ver mall and, auming that it i poible to detect that carr propagation ha terminated, the computer tem need not wait for the wort cae dela time on ever addition. Unfortunatel, taking advantage of a variable time adder would erioul complicate the deign of a clocked tem. It i more practical to bae the deign on wort cae dela aumption. Firt we conider the mean carr-chain length, auming that the two value being added have random bit-pattern. Thi aumption i clearl not true of mot computer program. Mot integer calculation involve the addition or ubtraction of mall contant. Conider a imple eample, where the tranpoe of a matri i being calculated: // Matri Tranpoe Eample int in_matri[4][4], out_matri[4][4];... for(int i=;i<4;i++) for(int j=;j<4;j++) out_matri[j][i] = in_matri[i][j]; Although contrived, the eample doe reflect what take place in real program: much of the arithmetic activit i devoted to loop-counting and computing addree. Thee operation require the addition and ubtraction of mall integer contant. The Burrough B7 computer wa baed on thi premie. It enabled torage of, and arithmetic on, variable-length integer, reflecting the propenit of operation with mall integer contant. Let continue with the aumption that the two operand have random bit pattern. For each operand, ever poible value within the range of the number tem i equall likel. The following tatement are then true for an arbitrar tage: Probabilit of carr generation = /4

7 Adder Circuit 7 Probabilit of carr annihilation = /4 Probabilit of carr propagation = /2 The firt cae correpond to i. i =. The econd require i + i =,and the third require i i =. For a carr chain to begin at tage i and end at tage j, j>i,itmutbe generated b tage i, propagated b tage i+,i+2, j, and topped at tage j. To top the carr chain, tage j mut either annihilate the incoming carr, or generate a carr, thereb beginning new chain. The probabilit that a carr generated at poition i end at poition j, for j>ii: P carr chain (j, i) =2 (j i ) /2 =2 (j i) j>i The equation doe not include the probabilit that tage i generate a carr. The term /2 come from the combined probabilitie that tage j generate a carr or annihilate the incoming carr. To obtain the mean length of a carr chain beginning at tage i we um the length of all poible chain time their probabilitie. = = k j=i+ k j l= [ (j i)2 (j i) ] +(k i)2 (k i ) [ l2 l ] +(k i)2 (k i ) = 2 (k i )2 (k i ) +(k i)2 (k i ) = 2 2 (k i ) The ummation include all chain that top before or at tage k. The term (k i)2 (k i ) i for a carr chain of length k i, that mut end ince there i no tage k. The change of variable, l = j i, in the econd line facilitate the ue of the theorem: p l= l (p +2) =2 2l 2 p For k>>i, the mean carr-chain length i 2, quite hort. Now we conider the mean of the longet carr-chain length when adding pair of arbitrar

8 Adder Circuit 8 integer. That i, if we add one million pair of randoml generated integer and tabulate the length of the longet carr-chain in each of thee um, what will be the mean of thoe tabulated value? Let η k (h) be the probabilit that the longet carr-chain in a k bit addition i of length h or more. The probabilit that the longet carr chain i eactl of length h i η k (h) η k (h + ). We can form a recurrence relation b uing the following condition that enable a carr chain of length h or more: c: The leat ignificant k bit have a carr length of h or more. c2: The leat ignificant k bit do not have uch a carr chain, but the mot ignificant h bit have a carr chain of length eactl h. Condition c and c2 are mutuall ecluive. In general: η k (h) =η k (h)+2 (h+) P (condition 2) The term 2 (h+) repreent the probabilit of a carr being generated at tage k h, time the probabilit of that carr being propagated over (the mot ignificant) h 2 tage. Since we cannot know the probabilit that the econd condition will occur, we et it probabilit to, change the equal ign to le-than-or-equal, and unwind the recurrence: η k (h) η k (h)+2 (h+)... η k 2 (h)+2 2 (h+) η k 3 (h)+3 2 (h+) η k 4 (h)+4 2 (h+) Then, ince η i (h) =fori<h, η k (h) (k h +)2 (h+) k2 (h+) Note that η k (h) i a probabilit, η k (h), but the RHS of the above inequalit i forh log 2 k.

9 Adder Circuit 9 To compute the mean of the longet carr-chain, λ, we um the length time their probabilitie: λ = k h [η k (h) η k (h +)] h= = [η k () η k (2)] + 2[η k (2) η k (3)] + + k[η k (k) ] = k η k (h) h= Net we partition the um into two part. The firt γ = log 2 k term and the remaining k γ term. We et the value of the firt γ term to, the larget the can be ince the are probabilitie. Each of the remaining term i bounded above b k2 (h+). k γ k λ = η k (h) + k2 (h+) <γ+ k2 (γ+) h= h= h=γ+ Now let ɛ = log 2 k log 2 k or γ = log 2 k ɛ, where ɛ<, then, noting 2 log 2 k = k and 2 ɛ < +ɛ, λ<log 2 k ɛ +2 ɛ <log 2 k Thi conclude the proof that the mean dela through a ripple-carr adder i O(log k). To make ue of thi information, it would be necear to add logic to the adder to detect when the output wa table, i.e. when all the carr propagation had been completed. Carr-Completion Logic provide thi facilit. Stud it deign from the tet. 4.3 Mancheter Carr Chain A we aw in the above proof, each tage can generate, propagate, or annihilate a carr: g i = i i p i = i i a i = i + i t i = a i = i + i

10 Adder Circuit We have added a tranfer ignal t i that can be ued in preference to p i ince it i eaier and quicker to generate. From thee equation a imple recurrence reult: c i+ = g i + c i p i = g i + c i t i In the carr-lookahead adder, the recurrence i unwound m time to form a blockcarr tem. In the Mancheter carr chain, the equation i implemented b three witche per tage: c i+ t i c i a i g i logic logic Figure 8: Mancheter Carr Chain If thi circuit i implemented with pa tranitor and a buffer gate i ued after ever m tage, the dela would be proportional to (k/m)m 2.