SERIES COMPENSATION: VOLTAGE COMPENSATION USING DVR (Lectures 41-48)

Transcription

1 Chapter 5 SERIES COMPENSATION: VOLTAGE COMPENSATION USING DVR (Lecture 41-48) 5.1 Introduction Power ytem hould enure good quality of electric power upply, which mean voltage and current waveform hould be balanced and inuoidal. Furthermore, the voltage level on the ytem hould be within reaonable limit, generally within 100 ± 5% of their rated value. If the voltage i more or le than thi pre-pecified value, performance of equipment i acrificed. In cae of low voltage, picture on televiion tart rolling, the torque of induction motor reduce to the quare of voltage and therefore there i need for voltage compenation. 5. Conventional Method to Regulate Voltage In order to keep load bu voltage contant, many conventional compenating device uch a lited below can be ued. In general, thee can be referred a VAR compenator. 1. Shunt Capacitor. Serie Capacitor 3. Synchronou Capacitor 4. Tap Changing Tranformer 5. Booter Tranformer 6. Static Synchronou Serie Capacitor 7. Dynamic Voltage Retorer 169

2 The firt ix method are employed at tranmiion level while the lat method i by employing Dynamic Voltage Retorer (DVR), i motly employed in power ditribution network to protect any voltage variation at the load bu connected to the enitive and critical electrical unit. The DVR i a erie connected cutom power device ued to mitigate the voltage unbalance, ag, well, harmonic and any abrupt change due to abnormal condition in the ytem. In the following ection, dynamic voltage retorer will be decribed in detail. 5.3 Dynamic Voltage Retorer (DVR) A dynamic voltage retorer (DVR) i a olid tate inverter baed on injection of voltage in erie with a power ditribution ytem [1], []. The DC ide of DVR i connected to an energy ource or an energy torage device, while it ac ide i connected to the ditribution feeder by a three-phae interfacing tranformer. A ingle line diagram of a DVR connected power ditribution ytem i hown in the figure below. In thi figure, v (t) repreent upply voltage, v t (t) repreent terminal voltage and v l (t) repreent the load voltage. Since DVR i a erie connected device, the ource current, i (t) i ame a load current, i l (t). Alo note in the figure, v f (t) i DVR injected voltage in erie with line uch that the load voltage i maintained at inuoidal nominal value. v () t R jx () vt () t vl t i i l vf () t L O A D Fig. 5.1 A ingle-line diagram of DVR compenated ytem The three-phae DVR compenated ytem i hown in Fig. 5. below. It i aumed that the tranmiion line ha ame impedance in all three phae. A DVR unit which i repreented in Fig. 5.1, have following component [3]- [5]. 1. Voltage Source Inverter. Filter capacitor and inductor 3. Injection tranformer 4. DC torage ytem Thee component are hown in Fig Some other important iue i.e., how much voltage hould be injected in erie uing appropriate algorithm, choice of uitable power converter topology to yntheize voltage and deign of filter capacitor and inductor component have to be addreed while deigning the DVR unit. 170

3 N v a v b vc R R R jx jx jx i a i b i c v fa v fb v fc v la vlb v lc A B C n Fig. 5. A ingle-line diagram of DVR compenated ytem R L PCC v t Injecion tranformer - v f Cf + v l Load L f v VSI C dc Energy torage Fig. 5.3 Schematic diagram of a DVR baed compenation in a ditribution ytem 5.4 Operating Principle of DVR Conider a DVR compenated ingle phae ytem a hown in Fig Let u aume that ource voltage i 1.0 pu and we want to regulate the load voltage to 1.0 pu. Let u denote the phae angle between V and V l a δ. In thi analyi, harmonic are not conidered. Further we aume that during DVR operation, real power i not required except ome loe in the inverter and the non ideal filter component. Thee loe for the time being are conidered to be zero. Thi condition implie that the phae difference between V f and I hould be 90 o. Let u firt conider a general cae to undertand the concept. The DVR equivalent circuit with fundamental voltage and current i hown in Fig Applying Kirchoff voltage law in the circuit, V + V f = I (R + jx ) + V l = I Z + V l. (5.1) 171

4 R jx V V t Vl I V f L O A D Fig. 5.4 Schematic diagram of a DVR baed compenation in a ditribution ytem Note that in above curcuit I = I l = I. The load voltage V l can be written in term of load current and load impedance a given below. V + V f = I (Z + Z l ) (5.) Uing (5.1), the ource voltage can be expreed a in the following. V = V l + I R (V f ji X ) (5.3) With the help of above equation, the relationhip between load voltage and the ource and DVR voltage can be expreed a below. ( ) V + V f V l = Z l (5.4) Z + Z l Example 5.1 Let u apply condition to maintain load voltage ame a ource voltage i.e., V l = V. Dicu the feaibility of injected voltage in erie with the line a hown in Fig. 5.4, to obtain load voltage ame a ource voltage. Conider the following cae. (a) Line reitance i negligible with Z = j0.5 pu and Z l = j0.5 pu. (b) When the load i purely reitive with Z = j0.5 pu and Z l = 0.5 pu. Solution: (a) When line reitance i negligible The above condition implie that, X = 0. Without DVR, the load terminal voltage V l can be given a following. I l = V Z l + jz = 1.0 0o j0.5 = 1.0 j1.0 = o pu 17

5 Therefore the load voltage i given a following. V l = Z l I l = o o = o pu. Thi i illutrated in Fig. 5.5(a). Thu the load voltage ha reduced by 1%. Now it i deired to maintain load voltage ame a upply voltage in magnitude and phae angle. Thu, ubtituting V = V l in equation (5.1), we get, V + V f = I (R + jx ) + V l V f = I (R + jx ) V f = jx Z l V l, ince R = 0 and I = V l /Z l Neglecting reitance part of the feeder impedance, Z = j0.5, the DVR voltage can be computed a above. V f = j j o for V l = o = o pu. From the above the, line current i computed a following. I = V l Z l = o o = o pu. It i to be noted that, although V = V l = o pu, it doe not imply that no power flow from ource to load. In fact the total effective ource voltage i V = V + V f = pu. Therefore it implie that the effective ource voltage i leading the load voltage by an angle of o. Thi enure the power flow from the ource to load. Thi i illutrated by drawing phaor diagram in the Fig. 5.5(b). below. I 45 o 18.8 o V =1.0 0 o V l jxi I V 6.56 o Vl jx I =1.0 0 o f V jx I (a) (b) Fig. 5.5 Terminal voltage (a) Without DVR (b) With DVR (b) When load i purely reitive 173

6 For thi cae X l = 0, therefore Z l = R l = 0.5 pu. Subtituting V = V l in (5.1), we get the following. Subtituting I = V l /R l, we get, V f = R + jx R l V l = R V f = (R + jx )I ( ) V l R l ( ) V l + jx = R I + jx I. R l From thi above equation, it i indicated that DVR voltage ha two component, the one i in phae with I and the other i in phae quadrature with I. Thi implie that for purely reitive load, it i not poible to maintain V l = V without active power upplied from the DVR to the load. Thi i due to the preence of in phae component of the DVR voltage in the above equation. Thi i illutrated in the phaor diagram given in Fig. 5.6 below. V jxi I V l IR Fig. 5.6 When load i purely reitive General Cae In general, it i deired to maintain the magnitude of the load voltage equal to the ource voltage i.e., 1.0 pu. The voltage equation in general relating the ource, load and DVR ha been expreed in (5.3) and i given below. V = V l + I R (V f ji X ) The above equation i illutrated uing phaor diagram decription in Fig. 5.7 given below. Three cae of voltage compenation are dicued below. Cae 1: When R I < CD For thi cae, it i alway poible to maintain load voltage ame a ource voltage i.e., V l = V. The DVR i expected to upply enough range reactive power to meet thi condition. When R I i quite maller than CD, the above condition can be met by uppling le reactive power from the DVR. For thi condition there are two olution. Graphically, thee olution are repreented by point A an B in the Fig Cae : When R I > CD For thi condition, it i not poible to meet V l = V. Thi i hown by line paing through 174

7 O V l A 1 IR I l V A jxi C D D 1 V Locu of f jx I V D B 1 B Fig. 5.7 Compenation uing DVR: General cae point between D 1 and D. Thi may take place due to the higher feeder reitance or high current, thu making product of I R relatively large. Cae 3: When R I = CD Thi i limiting cae of compenation to obtain V = V l. Thi condition i now atified at only one point when CD=R I. Thi i indicated by point D in the Fig Now let u et the following objective for the load compenation. V l = V = V = 1.0 pu (5.5) From Fig. 5.7, OC = V co φ l = co φ l. Therefore, CD = OD OC = V (1 co φ l ) = (1 co φ l ) pu. In order to meet the condition given by (5.5), the following mut be atified. The above implie that R I V (1 co φ l ) (5.6) R V (1 co φ l) I (5.7) or I V (1 co φ l) R. (5.8) Thu it i oberved that for a given power factor, the DVR characteritic can be obtained by varying R and keeping I contant or vice vera. Thi i decribed below. Let u conider three 175

8 condition R = 0.04 pu, R = 0.1 pu and R = 0.4 pu. For thee value of feeder reitance, the line current are expreed a following uing (5.8). I = 5 (1 co φ l ) pu for R = 0.04 pu I = 10 (1 co φ l ) pu for R = 0.1 pu I =.5 (1 co φ l ) pu for R = 0.4 pu. The above current are plotted a function of load power factor and are hown in Fig Since R I = V l (1 coφ l ), when R increae, I ha to decreae to make V l (1 coφ l ) to be a contant for a given power factor. Thu if the load require more current than the permiible value, the DVR will not be able to regulate the load voltage at the nominal value, i.e., 1.0 pu. However we can regulate bu voltage le than 1.0 pu. For regulating the load voltage le than 1.0 pu the current drawing capacity of the load increae Fig. 5.8 DVR characteritic for different load power factor and feeder reitance 5.5 Mathematical Decription to Compute DVR Voltage The previou ection explain DVR characteritic and decribe the feaibility of realizing DVR voltage graphically under different operating condition. In thi ection, a feaible olution for the DVR voltage i preented with a mathematical decription. Thi play ignificant role while implementing DVR on real time bai. Reproducing equation (??) for ake of completene, V + V f = V l + (R + jx ) I. (5.9) 176

9 Denoting, (R + jx ) I = a + jb and V f = V f V f = V f (a 1 + jb 1 ), the above equation can be written a following. V = V l + (a + jb ) V f = V l + (a + jb ) V f (a 1 + jb 1 ) = o + (a + jb ) V f (a 1 + jb 1 ) (5.10) Since, ource voltage and load voltage have to be maintained at nominal value i.e., 1.0 pu, therefore V = V δ = 1.0 δ. Subtituting thi value of V in above equation, we get, V = 1.0 δ = co δ + j in δ = {(1 + a ) V f a 1 } + j(b V f b 1 ) (5.11) Squaring and adding the real and imaginary part from both the ide of the above equation, we get, (1 + a ) + V f a 1 (1 + a ) a 1 V f + b + V f b 1 b 1 b V f 1.0 = 0 (5.1) Since a 1 + b 1 = 1, therefore ummation of underline term, Vf (a 1 + b 1). = Vf. Uing thi and rearranging above equation in the power of V f, we get the following. V f {(1 + a ) a 1 + b 1 b } V f + (1 + a ) + b 1.0 = 0 (5.13) The above equation give two olution for V f. Thee are equivalent to two point A and B hown in the Fig However, the feaible value of the voltage i choen on the bai of the rating of the DVR. Example 5. Conider a ytem with upply voltage 30 V = 1.0 pu, 50 Hz a hown in the Fig Conider feeder impedance a Z = j0.3 pu and load impedance Z l = j0.3 pu. 1. Compute the load voltage without DVR.. Compute the current and DVR voltage uch that V l = V. 3. Compute the effective ource voltage including DVR. Explain the power flow in the circuit. 4. Compute the terminal voltage with DVR compenation. Solution: 1. When DVR i not connected. The ytem parameter are given a following. The upply voltage V = o pu, Z = R + j X = j0.3 and Z l = R l + j X l = j0.3 pu. The current in the circuit i given by, I = I = I l = V = Z + Z l j0.6 = 0.83 j0.91 = o pu 177

10 v () t R jx () vt () t vl t i i l vf () t Rl jxl The load voltage i therefore given by, Fig. 5.9 A DVR compenated ytem V l = Z l I = j0.3 = o pu Thu we oberve that the load voltage i 71% of the rated value. Due to reduction in the load voltage, the load may not perform to the expected level.. When DVR i connected It i deired to maintain V l = V by connecting the DVR. Taking V l a reference phaor i.e., V l = o, The line current i computed a below I = j0.3 = 1.47 j0.88 = o pu Writing KVL for the circuit hown in (5.9), V + V f = V l + (R + jx ) I. The DVR voltage V f can be expreed a following. V f = V f ( I + 90 o ) The angle of V f i taken a ( I + 90 o ) o that DVR do not exchange any active power with the ytem. V f = V f ( I + 90 o ) = V f ( o + 90 o ) = V f o = V f ( j0.86) = V f (a 1 + jb 1 ) pu The above equation implie that a 1 = 0.51, b 1 = Let u now compute (R + jx ) I. (R + jx ) I = ( j0.3) (1.46 j0.86) = o o = o = j pu 178

11 The above implie that a = and b = A dicued in previou ection, the equation V + V f = V l + (R + jx ) I can be written in following form. V f {(1 + a ) a 1 + b 1 b } V f + (1 + a ) + b 1.0 = 0. Subtituting a 1, b 1, a, b in the above equation, we get the following quadratic equation for the DVR. V f.0463 V f = 0 Solving the above equation, we get V f = 0.708, pu a two value of the DVR voltage. Thee two value correpond to the point A and B repectively in Fig However, the feaible olution i V f = pu, a it enure le rating of the DVR. Therefore, V f = o = j0.608 pu. The ource voltage can be computed uing the following equation. 3. Effective ource voltage V = V l + (R + jx ) I V f. = o + ( j0.3) o o = j0.056 = o pu It i een that the magnitude of V i 1.0 pu which i atifying the condition V = V l. However the angle of V i o which implie that power i flowing from load to the ource. Thi i not true becaue the effective ource voltage i now V = V +V f. Thi i computed below. V + V f = V = j j0.608 = j0.397 = o pu From above it i evident that the effective ource voltage ha magnitude of pu and an angle of 16.5 which enure that power flow from ource to the load. For thi the equivalent circuit i hown in the Fig below. 4. Terminal voltage with DVR compenation The terminal voltage can alo be computed a following. V t = V Z I = V l V f = o o = o pu Thi indicate that for rated current flowing in the load, the terminal voltage i le than the 1.0 pu and need compenation. After compenation the load voltage i 1.0 pu a hown in the Fig The detail of voltage are depicted in the following figure. 179

12 ' V V Vf o R jx Vl o I I l Rl jxl 5.6 Tranient Operation of the DVR Fig A DVR compenated ytem In the previou ection the operation of the DVR in the teady tate wa dicued with aumption that full ytem information i available. While implementing the DVR compenation cheme, the above dicued method hould be implemented on the real time bai. For the ingle phae DVR operation, following tep are required. 1. Define a reference quantity uch a the terminal voltage V l (t) and other quantitie are ynchronized to it.. To compute phae angle of the DVR voltage, a fundamental of line current i extracted with repect to reference quantity. 3. Then DVR voltage i computed uing Equation (5.13), which i reproduced below. V f {(1 + a ) a 1 + b 1 b } V f + (1 + a ) + b 1.0 = 0 4. DVR voltage V f i then yntheized uing magnitude V f from the above equation and phae angle that lead the fundamental of the line current by 90 o. The above method can be refereed a Type 1 control [1]. The method aume that all circuit parameter are known along with the information of the ource impedance. Thi however may not be feaible in all circumtance. To olve thi problem Type control i uggeted. In Type control only local quantitie are required to compute the DVR voltage. The method i decribed below. The terminal voltage, which i local quantity to the DVR a hown in Fig. 5.1 can be expreed a following. V t = V l V f = V l 0 o V f (a 1 + jb 1 ) = (V l a 1 V f ) jb 1 V f (5.14) Since, V t = V t δ t = V t co δ t + jv t in δ t, the above equation i written a following. V t co δ t + jv t in δ t = (V l a 1 V f ) jb 1 V f (5.15) 180

13 Squaring adding both ide we get, Vt = (V l a 1 V f ) + b 1 Vf = Vl + a 1 Vf + b 1 Vf a 1 V l V f = V l + V f a 1 V l V f (ince a 1 + b 1 = 1). (5.16) The above equation can be arranged in the power of the DVR voltage a given below. V f a 1 V l V f + V l V t = 0 (5.17) To implement DVR for unbalanced three-phae ytem without harmonic, the poitive equence current (I + a, I + b and I + c ) of line current are extracted uing Fourier tranform. Baed on thee value of current the angle of DVR voltage are found by hifting current angle by 90 o i.e., V fa = I + a + 90 o V fb = I + b + 90 o (5.18) V fc = I + c + 90 o The magnitude of DVR voltage can be found uing equation (5.13) and (5.17) for Type 1 and Type control repectively. Baed on above the DVR voltage v fa, v fb, v fc can be expreed in time domain a given below. v fa = V fa in(ω t + V fa ) v fb = V fb in(ω t 10 o + V fb ) (5.19) v fc = V fc in(ω t + 10 o + V fc ) Operation of the DVR With Unbalance and Harmonic In the previou analyi, it wa aumed that the upply voltage are unbalanced without harmonic. In thi ection the operation of the DVR with harmonic will be dicued. The terminal voltage (v ta, v tb and v tc ) are reolved into their fundamental poitive equence voltage and the ret part, a given below. v ta = v ta1 + + v ta ret v tb = v + tb1 + v tb ret (5.0) v tc = v tc1 + + v tc ret The angle of fundamental DVR voltage ( V fa1, V fb1 and V fc1 ) can be extracted a explained above. The magnitude of the fundamental DVR voltage (V fa1, V fb1 and V fc1 ) can be computed uing equation (5.13) and (5.17) for Type 1 and Type control repectively. For example, uing Type control the fundamental phae-a DVR voltage i computed a per following equation. V fa1 a a1 V l V fa1 + V l V + ta1 = 0 (5.1) 181

14 In above equation a a1 + jb a1 = V fa1 and V + ta1 i fundamental poitive equence phae-a terminal voltage a given above in (5.0). Similar expreion can be written for phae-b and phae-c. Thi equation give olution only for fundamental component of the DVR voltage. The ret of the DVR voltage which conit of harmonic and unbalance mut be equal and oppoite to that of the ret part of the terminal voltage i.e., v ta ret, v tb ret and v tc ret. Therefore thee can be given uing following equation. v fa ret = v ta ret v fb ret = v tb ret (5.) v fc ret = v tc ret Thu, the total DVR voltage to be injected can be given a following. v fa = v fa1 + v fa ret v fa = v fb1 + v fb ret (5.3) v fa = v fc1 + v fc ret In above equation, v fa1, v fb1, v fc1 are contructed uing equation (5.19). Once v fa, v fb and v fc are known, thee voltage are yntheized uing uitable power electronic circuit. It will be dicued in the following ection. 5.7 Realization of DVR voltage uing Voltage Source Inverter In the previou ection, a reference voltage of DVR wa extracted uing dicued control algorithm. Thi DVR voltage however hould be realized in practice. Thi i achieved with the help of power electronic converter which i alo known a voltage ource inverter. Variou component of the DVR were lited in the beginning of chapter. They are hown in detail in the Fig The tranformer inject the required voltage in erie with the line to maintain the load bu voltage at the nominal value. The tranformer not only reduce the voltage requirement but alo provide iolation between the inverter. The filter component of the DVR uch a external inductance (L t ) which alo include the leakage of the tranformer on the primary ide and ac filter capacitor on the econdary ide play ignificant role in the performance of the DVR [Saitharan Thei]. The ame DC link can be extended to other phae a hown in Fig The ingle phae equivalent of the DVR i hown in the Fig In Fig and 5.1, v inv denote the witched voltage generated at the inverter output terminal, the inductance, L t repreent the total inductance and reitance including leakage inductance and reitance of tranformer. The reitance, R t model the witching loe of the inverter and the copper lo of the connected tranformer. The voltage ource inverter (VSI) i operated in a witching band voltage control mode to track the reference voltage generated uing control logic a dicued below. Let Vf be the reference voltage of a phae that DVR need to inject in erie with the line with help of the VSI explained above. We form a voltage hyterei band of ±h over thi reference value. Thu, the upper and lower limit within which the DVR ha to track the voltage can be given a 18

15 R L v t v f + v l i l C f v Load bu v p Load + S 1 D 1 S 3 D 3 L t R t i inv V dc C dc v inv S 4 D 4 S D To other phae Fig The DVR circuit detail C f i fac v t v l vinv Xt Rt Fig. 5.1 Equivalent circuit of the DVR following. v f up = v f + h v f dn = v f h (5.4) The following witching logic i ued to yntheize the reference DVR voltage. If v f v fup S 1 S OFF and S 3 S 4 ON ( -1 tate) ele if v f v fdn S 1 S ON and S 3 S 4 OFF ( +1 tate) ele if v fdn v f v fup retain the current witching tatu of witche end. It i to be noted that witche tatu S 1 S ON and S 3 S 4 OFF i denoted by +1 tate 183

16 and it give v inv = +V dc. The witche tatu S 1 S OFF and S 3 S 4 ON correpond to -1 tate providing v inv = V dc a hown in Fig The above witching logic i very baic and ha cope to be refined. For example 0 tate of the witche of the VSI a hown in Fig. 5.11, can alo be ued to have mooth witching and to minimize witching loe. In the zero tate, v inv = 0 and refer witche tatu a S 3 D 1 or S 4 D for poitive inverter current (i inv > 0). Similarly, for negative inverter current (i inv < 0), 0 tate i obtained through S 1 D 3 or S D 4. With the addition of 0 tate, the witching logic become a follow. If v f > 0 if v f v fup 0 tate ele if v f v fdn +1 tate end ele if v f < 0 if v f v fup -1 tate ele if v f v fdn 0 tate end end. In order to improve the witching performance one more term i added in the above equation baed on the feedback of filter capacitor current. v f up = v f + h + α i fac v f dn = v f h + α i fac (5.5) Where α i a proportional gain given to moothen and tabilize the witching performance of the VSI []. The dimenion of α i Ω and i thu i equivalent to virtual reitance, whoe effect to damp out and moothen the DVR voltage trajectory reulted from the witching of the inverter [4]. The value of hyterei band (h) hould be choen in uch a way that it limit witching frequency within the precribed maximum value. Thi kind of voltage control uing VSI i called a witching band control. The actual DVR voltage i compared with thee upper and lower band of the voltage (V f up, V f dn ) and accordingly witching command to the power witch are generated. The witching control logic i decribed in the Table 5.1. To minimize witching frequency of the VSI, three level logic ha been ued. For thi an additional check of polarity of the reference voltage ha been taken into conideration. Baed on thi witching tatu, the inverter upplie +V dc, 0 and V dc level of voltage correponding to the 1, 0 and -1 given in the table, in order to ynthei the reference DVR voltage. In addition to witching band control, an additional loop i required to correct the voltage in the dc torage capacitor againt loe in the inverter and tranformer. During tranient, the dc capacitor voltage may rie or fall from the reference value due to real power flow for a hort 184

17 Table 5.1 Three level witching logic for the VSI Condition Switching value Vf 0 V f > V up 0 Vf 0 V f < V dn 1 Vf < 0 V f > V up -1 Vf < 0 V f < V dn 0 duration. To correct thi voltage deviation, a mall amount of real power mut be drawn from the ource to replenih the loe. To accomplih thi, a imple proportional-plu-integral controller (PI) i ued. The ignal u c i generated from thi PI controller a given below. u c = K p e V dc + K i e V dc dt (5.6) Where, e V dc = V dc ref V dc. Thi control loop need not to be too fat. It may be updated once in a cycle preferably ynchronized to poitive zero croing of phae-a voltage. Baed on thi information the variable u c will be included in generation of the fundamental of DVR voltage a given below. V f1 = V f1 ( I + 90 o u c ) = V f1 (ã 1 + j b 1 ) (5.7) Then the equation (5.17), i modified to the following. V f1 ã 1 V l V f1 + V l V t1 = 0 (5.8) The above equation i ued to find the DVR voltage. It can be found that the phae difference between line current and DVR voltage differ lightly from 90 o in order to account the loe in the inverter. 5.8 Maximum Compenation Capacity of the DVR Without Real Power Support from the DC Link There i direct relationhip between the terminal voltage, power factor of the load and the maximum poible achievable load voltage, with aumption that no real power i required from the dc bu. Referring to quadratic equation in (5.8), for given value of V t1 and a target load bu voltage V l, The equation give two real value of V f1 for feaible olution. In cae olution i not feaible, the equation give two complex conjugate root. Thi conclude that the maximum voltage that DVR can compenate correpond to the ingle olution of the above equation, which i given below. Thi olution correpond to point D in Fig V f1 = ã 1 V l ± ( ã 1 V l ) 4 (Vl Vt1) (5.9) Since, voltage hould not be complex number, the value of the term within quare root mut not be negative. Therefore ( ã 1 V l ) 4 (V l V t1) (5.30) 185

18 The above equation implie that V l V t1 1 ã 1. (5.31) And therefore, the DVR voltage i given by the following equation. With no loe in the VSI, u c = 0, V l V f1 = ã 1 V l (5.3) V t1 1 ã 1 = V t1 1 a 1 (5.33) Since, ã 1 + j b 1 = 1 (90 o + φ l ) = co(90 o + φ l ) + j in(90 o + φ l ) = in φ l + j co φ l. Thi implie ã 1 = in φ l, therefore 1 ã 1 = 1 ( in φ l ) = co φ l. uing thi relation, the above equation can be written a following. V l V t1 co φ l (5.34) Example 5.3 A DVR i hown in Fig The feeder impedance of the line j0.5 pu. Aume i h to be load current repreented by quare waveform approximated by the following expreion. i h = 1.0 in(ω t 30 o ) in(3 ω t 90 o ) pu 1. Find the load voltage v(t) without DVR compenation i.e., v f = 0.. I it poible to maintain load voltage, V l to be 1.0 pu inuoidal waveform? If ye what i the DVR voltage, v f (t)? 3. If no, how much maximum voltage can be maintained at load terminal with the DVR without taking any real power from the dc bu? T T t f l h Fig A DVR compenated ytem 186

19 Solution: 1. When V f = 0 v t = v Z h i h h=1,3 The impedance at the fundamental frequency, Z 1 = j0.5 = o pu. The impedance at third harmonic, Z 3 = j1.5 = o pu. Therefore the voltage drop due to fundamental component of the current, V z1 = (0.1 + j0.5) o = o o = pu. The voltage drop due to third harmonic component of the current, The load voltage thu can be given by Implying that, V z3 = (0.1 + j1.5) o = pu. v t = v (i 1 Z 1 + i 3 Z 3 ) = 1.0 in ωt 0.51 in(ωt o ) }{{} 0.45 in(3 ωt 3.8o ) = in(ωt 8.81 o ) 0.45 in(3 ωt 3.8 o ) pu = v t1 (t) + v th (t). V t1 = o = o pu. With DVR From the above equation, V t1 = With load voltage v l = 1.0 in (ωt φ l ), the DVR voltage V f1 can be olved uing quadratic equation a mentioned in Type control. Further, V f1 = V f1 ( I o ) = V f1 ( 30 o + 90 o ) = V f1 60 o = V f1 (co 60 o + j in 60 o ) = V f1 (0.5 + j0.8666) = V f1 (a 1 + jb 1 ) pu. The above implie a 1 = 0.5, b 1 = Knowing thi, we can olve V f1 uing following quadratic equation. V f1 a 1 V l V f1 + V l V t1 = 0 187

20 From the above, V f1 = a 1 V l ± a 1 Vl (Vl Vt1) = ( ) ± 1 (0.5) = 0.35 ± { ( 1 ) (0.5619) } The above olution i complex quantity, which implie that it i not poible to maintain load voltage at 1.0 in (ωt φ l ). 3. Maximum poible load voltage The maximum load voltage that can be obtained with the DVR, without any real power from the dc bu can be given a following. V l = V t1 = a = pu. In the time domain the load voltage v l = v l1 = in(ωt φ l ) = in(ωt φ l ). For thi load voltage the DVR voltage i given a following. Thi implie V f1 = a 1 V l = = pu. V f1 = o pu. The time domain repreion for the fundamental DVR voltage i given a, v f1 (t) = in(ωt + 60 o ) = in(ωt + 60 o ) pu. The harmonic voltage that DVR compenate i a following. The total DVR voltage i given a below. v fh (t) = v th = 0.45 in (3 ωt 3.8 o ) pu. v f (t) = v f1 (t) + v th (t) = in(ωt + 60 o ) in (3 ωt 3.8 o ) pu Reference [1] A. Ghoh and G. Ledwich, Compenation of ditribution ytem voltage uing dvr, IEEE Tranaction on Power Delivery, vol. 17, no. 4, pp , Oct

21 [] A. Ghoh and G. Ledwich, Structure and control of a dynamic voltage regulator (dvr), in IEEE Power Engineering Society Winter Meeting, vol. 3. IEEE, 001, pp [3] A. Ghoh, A. Jindal, and A. Johi, Deign of a capacitor-upported dynamic voltage retorer (dvr) for unbalanced and ditorted load, IEEE Tranaction on Power Delivery, vol. 19, no. 1, pp , Jan [4] S. Saitharan and Maheh K. Mihra, Contant witching frequency band controller for dynamic voltage retorer, IET Power Electronic, vol. 3, no. 5, pp , Sept [5] S. Saitharan, Maheh K. Mihra, B. Kalyan Kumar, and V. Jayahankar, Rating and deign iue of dvr injection tranformer, International Journal of Power Electronic, vol., no., pp ,